1 VCS Simulation Basics

Learning Objectives

After completing this lab, you should be able to:

倣真 可执 的
形
 Generate a VCS simulation executable by compiling an
existing Verilog design using VCS 编泽
 Simulate the operation of the Verilog design by executing 完成
the simulation binary executable generated by VCS
进制的
—

 Determine whether or not the Verilog design passes

verification by reading the console messages generated
by the Verilog system task calls in the Verilog source code

15 minutes

UNIT
Unit 1

VCS Simulation Basics 1-1

37489-000-S31
二
行
Lab 1

Getting Started

You will be using the following carry-select 8-bit adder for this lab:

add8.v
cin
a[7:0]
add4.v sum[7:0]
b[7:0]
a[0]
b[0] fa.v 1

a[1]
b[1] fa.v 1

a[2]
b[2] fa.v 1

a[3]
b[3] fa.v 1

0
a[7:4]
b[7:4] add4.v 0
1 4
1
add4.v
0
cout
1
1

Figure 1-1: 8-bit Carry Select Adder Block Diagram

Our goal is to use this simple design to take you through the fundamentals of the
two-step VCS simulation process. This lab is divided into three parts. Each part
has its own associated tasks. Here's a preview of what you will be doing:

 Compile the adder Verilog source files to generate a simulation executable.

 Simulate the 8-bit adder by executing the simulation executable.
 Interpret the simulation results displayed on console to determine whether or
not the 8-bit adder is working correctly.
 In Part A, all the Verilog source files for the 8-bit adder reside in the working
directory.
 In Part B, some of the Verilog source files for the 8-bit adder are in the working
directory, and the rest are in a library directory. You will compile them and
then use a compile-time file to simplify the VCS compile command line typing.

1-2 VCS Simulation Basics

Verification with VCS Workshop
Lab 1

Figure 1-2: Flow Diagram of Lab Exercise

Compile the Verilog

source files with VCS

Run simulation by
executing simv

Interpret simulation
results

VCS Simulation Basics 1-3

Verification with VCS Workshop
Lab 1

Part A: The two-step Simulation Process

Task 1 Compile to Generate Simulation Executable

In Part A of the lab1, all the Verilog source files for the 8-bit carry select adder
reside in your lab working directory.

After logging on to the workstation, go into the lab1 Part A directory.

1. shell> cd vcs/lab1/parta

You should see four files: fa.v, add4.v, add8.v, and addertb.v.

2. shell> ls

fa.v, add4.v and add8.v are the Verilog source files for the blocks shown in
Figure 1-1. addertb.v is the testbench used to check the funtionality of the
adder.

Compile the Verilog files and generate the simv simulation binary executatble.

3. shell> vcs addertb.v fa.v add4.v add8.v

When the compilation is done, you should see the message

Simv generation successfully completed

Task 2 Run Simulation

Run the testbench and simulate the design by executing simv.

1. shell> simv

When the simulation is done, you should see the message

$finish at simulation time 13107200

V C S S i m u l a t i o n R e p o r t
Time: 13107200
CPU Time: 0.490 seconds; Data structure size: 0.0 Mb
Mon May 22 09:58:26 2000

(Note: your date & time will be different)

Indicating that the simulation has completed. The CPU time used and the
memory used during the simulation are also reported.

1-4 VCS Simulation Basics

Verification with VCS Workshop
 Lab 1

Task 3 Check Simulation Results

You should also see the following printout generated by Verilog system task calls
embedded in the testbench.

…
*** Testbench Successfully completed! ***
…

This verification run was successful! In Lab 2 we will see how to generate
messages to help us debug code errors.

Task 4 Create Simulation Executable with Different Name

The VCS default simulation executable file name is simv. You can direct VCS
to generate a different executable name by using the –o switch.

Recompile the adder design, this time, generate a simulation executable called
addertest.

Compile the Verilog files and generate the simv simulation binary executatble.
(please note that the switch is the letter “o” not the number “0”)

1. shell> vcs addertb.v fa.v add4.v add8.v –o addertest

Check the content of the parta directory.

2. shell> ls

You should see 6 files including the simulation binary executable addertest.

Execute this simulation binary to make sure that the simulation results remain the
same.

3. shell> addertest

You should once again, see the following print out generated by the testbench.

…
*** Testbench Successfully completed! ***
$finish at simulation time 13107200
V C S S i m u l a t i o n R e p o r t
Time: 13107200
CPU Time: 0.490 seconds; Data structure size: 0.0 Mb
Mon May 22 10:08:21 2000
…

VCS Simulation Basics 1-5

Verification with VCS Workshop
一
 Lab 1

Part B: Working with Library Directories

Task 1 Compile & Simulate using Design Library Directory

In Part B of the lab1, we have moved fa.v and add4.v into a library directory.
The new file directory structure now looks like the following:

User_login_directory

… vcs

… lab1 lib

… partb … fa.v add4.v

addertb.v add8.v

The fa.v and add4.v modules are now modules within the library directory
lib.

Go to lab1 Part B working directory.

1. shell> cd ../partb

2. shell> ls

You now should only see two files: add8.v, and addertb.v.

Compile the design again. Only, this time, we need to reference the library
directory file.

You will also use the –R switch as a shorthand to execute simulation immediately
after compilation.

3. shell> vcs addertb.v add8.v –y ../../lib +libext+.v -R

Notice that because our library files have the .v extension, the +libext switch
is required to get vcs to search the .v extension files.
—

The source file contents have not changed, only the physical placement of the file
has changed, you should see identical simulation results as in part A.

1-6 VCS Simulation Basics

Verification with VCS Workshop
一一
 Lab 1

Task 2 Compiling with –f File Switch

简 命令
Simplify the command line entry by using the –f compile-time switch. First
create a file which contains the names of all the source files or libraries for the
design. When compiling the design, reference this file with the –f switch.
—

引
1. Use any editor you are comfortable with and create the file “adder.f”
containing the following:

addertb.v
add8.v
-y ../../lib +libext+.v

Compile and simulate the design by using the –f switch as follows:

2. shell> vcs –f adder.f -R

The source file contents have not changed, only the physical placement of the file
has changed, you should see identical simulation results as in part A and part B.

You are done! Compilation and simluation using VCS is very simple.

Try out some of what you’ve learned by answering the following questions.

Can you embed the –R switch in the adder.f file? ...................................................

Can you use the –v switch instead of the –y switch? How? .................................

VCS Simulation Basics 1-7

Verification with VCS Workshop
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入
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