Embedded Systems and loT Design 5-14

ARM Processor
5.3 ARM Processor

5.3.1 Features of ARM Processor

" The basic RISCarchitecture concept of the simple hardware with an instruction
combined with a few key CISC features allow ARM processors to suppor
following features
1. Load-store architecture
2. Fixed-length 32-bit instructions
3. 3-address instruction formats
4. High performance
5. Low code size
6. Low power consumption
7. Low silicon area (small core size)
8. It has control over both the Arithmetic Logic Unit (ALU) and shifter in everv
data-processing instruction to maximize the use of an ALUand a shifter.
9. Supports auto-increment and auto-decrement addressing modes to optimize
program loops.
10. Supports Load and Store Multiple instructions to maximize data throughput.
11. Supports conditional execution of all instructions to maximize execution
throughput.
5.3.2 ARM Architecture
An ARM core is an engine within a system that fetches ARM instructions from
memory and executes them.
ARM cores are very small. Typically they occupy a few square millimeters of chip
area.

With advances in modern VLSI technology, it became possible to build additional

system components such as cache memory, memory management unit 0r
application specific hardware on the same chip. Application specific hardware may
include signal processing hardware or further ARM processor cores.
While designing a new system, selecting the correct processor core is one of the
most critical decision.

5.3.2.1 ARM Core Dataflow Model

Fig. 5.3.1 shows the basic structure of ARM core and how data moves between 1
different parts.

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 Embedded Systems and loT Design 5- 15 ARM Processor

Data

Instruction Sign extend

decoder
Write
Read

Register fiie
PC(r15)
Rd
R Rm Bbus
Abus Bpus Barrellshifter
Acc Abus N

MAC
ALU

Result bus

Address Register

incrementer
Address

Fig. 5.3.1 ARM core dataflow model

The ARM core dataflow model shown in Fig. 5.3.1 is Von Neumann
implemerntation of the ARM.
Since ARM processor is basically a RISC processor, it uses a load-store
architecture. This means, it has two instruction types, load and store, for
transferring data in and out of the processor respectively.
LOAD : This instruction copies data from memory to registers in the
procesSor core.
STORE : This instruction copies data from registers in the processor core to
memory.
The ARM processor instruction set does not include the instructions that directly
manipulate data in memory. The data processing is carried out only in registers.
Data bus
The data enters the ARM core through the data bus. The datais either in the form
of an instruction opcode or a data item.
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Embedded Systems and loT Design ARM Processor
Since Von Neumann architecture is used, data items and instructions
same bus. This is in contrast with Hardvard architecture which uses two share the
buses. dif erent
0nstruction decoder
This unit decodes the instruction opcode read from the memory and then
instruction is executed. the
Register file
This is abank of 32-bit registers used for storing data items.
Sign extend :
The ARM core is a 32-bit processor. So most instructions of the ARM processo.
treat registers as holding signed or unsigned 32-bit values.
When the processor reads signed 8-bit or 16-bit numbers from memory, the sien
extend hardware converts these numbers to 32-bit values and then places them in
a register file.
ALU (Arithmetic Logic Unit) and MAC (Multiply-Accumulate Unit)
Most of the ARM instructions are two operand instructions. The two source
registers Rn and Rm are used to store these operands. These source operands are
read from the R, and Rm registers using the internal buses A and B respectively.
The ALUor MAC reads the operand values from R, and Rm registers via A and
B buses respectively, performs the operation and stores the computed result via
internal Cbus in destination register, Rd and then to the register file.
The load and store instructions generate address using ALUand stores it in the
address register.
Address register
This holds the address generated by the load and store
on the address bus.
instructions and places it
Barrel shifter
The contents of the Rm register alternatively can be
preprocessed in the barrel
shifter before applying as an input to the ALU.
A wide range of expressions and addresses can be
shifter and ALU.
calculated using the barrel
incrementer
For load and store instructions, the incrementer updates the
address register before the processor core reads or writes the nextcontents of
from or to the consecutive memory location. register valu

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Embedded Systems and loT Design ARM Processor
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. The processor core continues the execution of instruction. Only when an exception
or interrupt occurs, the normal execution flow is changed.

G33 ARM Programmer's Model

The register file in the ARM core contains all the registers, available to a
programmer. Ihe current mode of the processor decides the availability of the
registers to the programmer.
5:3.3.1 Processor Modes
The processor mode determines which registers are active and the access rights to
the cpsr register itself.
e In the ARM7, there are seven operating modes. These modes are protected or
exception modes which have associated interrupt Sources and their oWn register
set.
1. Supervisor mode (Default) : This is protected mode for running system level
mode after
code tO access hardware or run 0S calls. The ARMZ enters this
reset.

2. FIQ (Fast Interrupt reQuest): This mode supports high speed interrupt
handling.
a
3. IRQ (Interrupt ReQuest): This mode supports all other interrupt sources in
system.
location,
4. Abort : If an instruction or data is fetched from an invalid memory
an abort exception will be generated.
undefined
5. Undefined : If a fetched opcode is not an ARM instruction, an
instruction exception will be generated.
6. User: This mode is used to run the application code. In the user mode we
cannot change the contents of CPSR (Current Program Status Register) and
also
modes can only be changed when an exception is generated. This mode is
known as Unprivileged mode.
7. System : This mode is used for running operating system tasks. It uses the
same registers as user mode.
" All the above modes, except user mode, are privilege modes.
For all operating modes, user registers r0 - r7 are common. However, FIO mode
replaces the r0 - r7 registers by its own registers r8 to r14. Similarly, each of the
other modes have their own rl3 and rl4 registers so that each operating mode has
its own unique stack pointer and link register.

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 Embedded Systems and loT Design 5- 18
ARM Processor
5.3.3.2 Programming Model
Fig. 5.3.2 shows the programming model of ARM processor.

User and
system
ro
r1

r3
r4
r5
Fast
r6
interrupt
r7 request
r8_fiq
9_fig
r10 r10_fiq
r11 r11_fiq Interrupt
r12 r12_fiq request Supervisor Undefined Abort
r13sp r13_fiq r13 irg r13 svC r13 undef r13 abt
r14 Ir r14_fiq r14_irq r14 SVC r14 undef r14 abt
r15 pc

cpsr

spsr_fig spsr_irg spsr_svC spsr_undef spsr abt

Fig. 5.3.2 Programming model of ARM processor

The ARM processor has a total of 37 registers. All registers are 32-bits wide. They
can be classified into two groups as,
General purpose registers
Special purpose registers.
5.3.3.3 General Purpose Registers
Registers r0 to rl2 are used as general purpose registers. Depending upon e
context, registers r13 to r15 can also be used as general purpose registers.
The general purpOse registers hold either data or an address.

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BO34 Speclal Purpose Registers

Registers rl3 to rl5, CPSR (Curre:t Program Status Register) and SPSR (Saved
Program Status Register) are the special purpose registers.
Registers r13 to r15
. In user mode, registers rl3 to r15 are labeled as r13 sp, rl4 Ir and rl5 pc
respectively to differentiate them from other registers. The functions of these
registers are given below.
Stack pointer (r13 sp) : Register r13 is the stack pointer. It stores the top of
the stack in the current processor mode.
Link register (r14 Ir):Register rl4 is the ink register. The processor stores
the return address in this register when a subroutine is called.
Program counter (r15 pc) : Register r15 is the program counter and stores the
address of the next instruction to be fetched from the memory by the
processor.
" It is used in most instructions as a pointer to the instruction which is two
instructions after the instruction being executed.
All ARM instructions are four bytes long (one 32-bit word) and are always
aligned on aword boundary. This means that the bottom two bits of the PC
are always zero, and therefore the PC contains only 30 non-constarnt bits.
" It can often be used in place of one of the general-purpose registers r0 to
r14, and is therefore considered one of the general-purpose registers.
However, there are also many instruction-specific restrictions or special
cases about its use. Usually, the instruction is unpredictable if r15 is used in
a manner that breaks these restrictions.

The Unbanked Registers r0 - r7

Registers r0 to r7 are unbanked registers. This means that each of them refers to
the same 32-bit physical register in all processor modes.
They are completely general-purpose registers, with no special uses implied by the
architecture, and can be used wherever an instruction allows a gerneral-purpose
register to be specified.
The Banked Registers, r8- r14
Registers r8 to r14 are banked registers.
The physical register referred to by each of them depends on the current processor
mode. Where a particular physical register is intended, without depending on the
current processor mode, a more specific name (as described below) is used.

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ARM Processor
Almost all instructions allow the banked registers to be used
general-purpose register is allowed.
Out of 37 registers, 20 registers which are shown shaded in Fig.
wherever
banked registers. Fig. 5.3.2 also shows which banked registers are used 5.3.2 are
mode. Banked registers of a particular mode are denoted by, r number in the
For example, supervisor, mode has banked registers r13_svc, rl4_svc mode. which
On the other hand, abort mode has banked and
registers r13-abt, r14-abt and spsr _SVC.
Registers r8 to r12 have two banked physical registers each.
physical registers are referred to as r8_usr to The first spsr-abt .
r8_fiq to r12_fiq. The r8_usr to rl2_usr r12_usr and the second group of
than FIQ mode, and the other is used ingroup is used in all processor modes groupotheas
FIQ mode.
Registers r13 and r14 have six
and System modes, while eachbanked physical registers each. One is used in User
of the remaining five is
exception modes. used in one of the fitve
The registers ro to r13 are
apply to r0, you can equally orthogonal. This mneans, any instruction which you can
not the case with r14 and well apply to any of the r1 to
rl5 registers. r13 registers. This is
5.3.4 ARM CPSR
The current program status
contains condition code flags,register (cpsr) is accessible in all processor modes. It
and other status and interrupt
control information. disable bits, the current processor mode,
Each exception
to preserve the mode ofalso has a saved program status
value the cpsr when the register (spsr), that is used
Note User mode and associated exception occurs.
exception modes. Allsystem mode do not have an SPSR, because they are not
instructions which read Or
UNPREDICTABLE
Fig.
when executed in User
mode or System
write
mode.
the SPSR are
5.3.3 shows the
Fields format of the cpsr and spsr.
Flags Status
Bits Extension Control
31
28 27
N |Cv 8 7 5 4 0
UNDEFINED
Functions Condition IFT Mode
flags Interrupt Processor
masks mode

Fig. 5.3.3 Thumb

Format of cpsr and spsr state

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0-7)
Control flags (Bits software
The control bits change when an exception arises and can be altered by
only when the processor is in a privileged mode.
Select Bits) : Processor modes
Bits 0 - 4 (Mode
These bits determine the processor mode as shown in able 5.3.1.

Processor mo e Mode Select Bits [4 : 0]

Abort 10111

Fast interrupt request 1000 1

1001 0
Interrupt request
Supervisor 1001 1

1111 1
System
Undefined 1101 1

User 10000

Table 5.3.1 Processor mode

Bit 5 (Thumb State Bit) :

core determines which
This bit gives the state of the core. The state of the
instruction set is being executed.
of the three
There are three instruction sets, ARM, Thumb and Jazelle. One
Thumb state and
instruction set is active when the processor is in ARM state,
Jazelle state respectively.
Bits 6 and 7 (Interrupt Masks) :
There are two interrupts available on the ARM processor core :
Interrupt Request (IRQ) and
Fast Interrupt Request (FIQ).
These are maskable interrupts, and their masking is controlled by bits 6 and 7 of
CPSR. Bit 6(F) controls FIQ, and bit 7(I) controls IRQ.
When a bit is set to binary 1, the corresponding interrupt request is masked, and
when a bit is 0, the interrupt is available.
Condition code flags (Bit 28 - 31) :
These flags in the cpsr can be tested by most instructions to determine whether
the instruction is to be executed.

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ARM Processor
Bit 28 (Overflow flag, V)
It is set in one of two ways :
For an addition or subtraction, Vis set to 1 if signed overflow o
regarding the operands and result as two's
complement signed integers OCCurred,
"For non-addition/subtractions, V is normally left unchanged.
Bit 29 (Carry flag, C)
" It is set in one of four ways :
instruction CMN, Cis set to 1..
For an addition, including the .comparison
overflow), and to
the addition produced a carry (that is, an nsigned
otherwise.
is set to o :*
For a subtraction, including the comparison instruction CMP, C
the subtraction produced a borrow (that is, an unsigned underflow), and to 1
otherwise.

For non-addition/subtractions that incorporate a shift operation, C is set to the

last bit shifted out of the value by the shifter.
For other non-addition/subtractions, C is normally left unchanged.
Bit 30 (Zero flag, Z)
It is set to 1if the result of the instruction is zero (which often indicates an equal
result from a comparison), and to 0otherwise.
Bit 31 (Negative flag, N)
" It is set to bit 31 of the result of the
instruction. If this result is regarded as a
two's complement signed integer, then N = 1if the result is negative and N= 0if
it is positive or zero.

5.3.5 Memory Organization

ARM7 processors have a 32-bit address space,
4,294,967,296 (2) different memory locations. Thisallowing them to address up to
means each address refers to à
byte in memory.
" ARM7 uses byte
memory.
addressing, where
In this scheme, the word 0 is each address points to a single byte
2 is at at location 0, word 1 is at
location 8 and so on. location 4, wo
The Program Counter (PC)
in the ARM7
absence of a branch processor is incremented by 4 in the
(32 bits) long in ARM instruction. This is because
assenmbly and the PC pointseachto the
instruction is typically 4 bytes
next instruction.

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ARM Processor
ARM7 processorS can be
mode. These two modesconfigured to operate in either little-endian or
values) is stored in memory.determine how multi-byte data (e.g., 16-bitbig-endian
or 32-bit
Little-Endian Mode : In little-endian mode, the
significant byte) of a multi-byte value is stored in the lowest-order byte (the least
following bytes are stored in increasing lowest memory address. The
Tnode for ARM memory addresses. This is the default
processors.
Big-Endian Mode : In big-endian mode, the
significant byte) of a multi-byte value is stored in thehighest-order byte (the most
following bytes are stored in increasing memory lowest memory address. The
addresses.
Ox103 78 Ox103 12
Ox102 56
Ox102 34
Ox101 34
Ox101 56
Ox100 12
Ox100 78
Big endian Little endian
Fig. 5.3.1 Word, 0x12345678 stored in memory in
big-endian and little-endian modes
The ARM memory map
Fig. 5.3.2 shows the ARM memory
organization. It shows the
memory where each byte location has a unique number small portion of the
with little-endian'
assignment. (When the lower byte addresses are used for less significant
the word, addressing is called little-endian). bytes of

Bit 31 Bit 0

Half word 23 22 21 20

19 18 17 16

15 14 13 12 Word

11 10 8

7 6 5 4 Half word

3 2 1

Byte 3 Byte 2 Byte 1 Byte 0

Fig. 5.3.2 ARM memory with a "ittle-endian' memory organization

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ARM ProCes
5.3.6 Basic ARM Addressing Modes
Some of the simple ARM addressing modes are :
1. Register
2. Immediate
3. Register indirect (indexed addressing mode)
Register addressing mode
" The register addressing mode uses of registers to hold the data to be manipulato
Example:
MOVR3,R2 ; copy the contents of R2 into R3

Immediate addressing mode

" In the immediate addressing mode, the source operand is a constant, and it comes
immediately after the opcode.
Example:
MOV R1,#0x35 ; load Ox35 into R1.
Register Indirect Addressing Mode (lndexed addressing mode)
" In the register indirect addressing mode, the address of the memory location
where the operand resides is held by a register.
Example :
STR R1, (R2] ; store value of R1 into the memory location pointed by R2.

Review Questions

1. List the features of ARM processors.

2. Explain ARM core data flow model with a neat diagram.
3. Draw and explain the ARM programmer's model.
4. List the special purpose registers of ARM processor.
5. Explain diferent processor modes of ARM processor.
6. Explain the programmer's model of ARM processor with complete register sets available.
7. Explain registers used under various modes.
8. Explain the various fields in the Current Program Status Register (CPSR).
9. What is Big-Endian and Little-Endian ?
10. Write a note on ARM memory organization.
11. Explain some basic addressing modes of ARM.

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