Chapte, 4 Boolean Algebra and Logic Circuit, SS Boolean algebra deals with binary number system. Its very useful in designing logic ercuits used in procesy ¢f computer systems. In this chapter, you will lam about this algebra and elementary logic gates used to build yp {osic circuits of different types for performing necessary arithmetic operations. These logic gates are the building blocks of all logic circuits in a computer, You will also learn how to use Boolean algebra for designing simpl logic circuits used frequently by arithmetic logic unit of almost all computers. BOOLEAN ALGEBRA In mid 1800, George Boole (1815-1864), an English mathematician, developed algebra for simplifying the representation and manipulation of propositional logic. It is known as Boolean algebra afier its developer's name Later, in the year 1938, Claude E. Shannon proposed the use of Boolean algebra in the design of relay switching Circuits. The basic techniques described by Shannon were adopted almost universally for the design and analysis of switching circuits. Owing to analogous relationship between the action of relays and modern electronic cireuits, the same techniques are still used in the design of modern computers. Boolean algebra provides an economical and straightforward approach to the design of relay and other types of switching circuits. Just as an ordinary algebraic expression is simplified by using basic theorems, the expression describing a given switching circuit network is also simplified by using Boolean algebra. Today, Boolean algebra is used extensively in designing electronic circuitry of computers. Fundamental Concepts of Boolean Algebra Boolean algebra is based on the fundamental concepts described below. © scanned with OKEN ScannerBoolean Algebra ____ . se L se of Binary Digits Jpraic expression, a variable can take any numerical value. For example, in the expression JA « variables A, B, and C may have any value from the entire field of real numbers. Since, Be binary number system, the variables used in Boolean equations may have only tac ge ch of the variables A, B, and C may have only a normal alge ina each ofthe gebra deals with aaeeyy (dor 1). For example, in the Boolean equation A + B values the values 0 oF | Logical Addition bol “+ is used for logical addition operator. It is also known as OR’ operator. We can define the ~ {OR operator) by listing all possible combinations of A and B with the resulting value of C for each A+B=C. Since the variables A and B can have only two possible values (0 or 1). The sy symbol ‘combination in the equi tl Be Saly four (22) combinations of inputs are possible (see the table in Figure 6.1). The resulting output values for cach of the four input combinations are given in the table. Such a table is known as a ruth table. Hence, Figure 6.1 is the truth table for logical OR operator. Observe that the result is 0 only when both input variables are 0, It is 1 when any one or both of the input variables are 1. This is the reason why the + symbol does not have the “normal” arithmetic meaning, but is a logical addition operator. This concept of logical addition may be extended to any number of variables. For example, in the equation A 4B+C+D=E, even if A, B,C, and D, all had the value of |, the sum of the values (the result E) would be 1 only. Inputs + Output A oO 0 1 1 The equation A + B = C is normally read as “A or B Figure 6.1. Truth table for logical OR (+) operator. ‘equals C”. Logical Multiplication The symbol “is used for logical multiplication operator. itis also known as ‘AND’ operator. We can define the symbol (AND operator) by listing all possible combinations of A and B with the resulting value of C for ‘each combination in the equation A - B = C. Figure 6.2 shows the truth table for logical AND operator. Observe that the result C is equal to 1 only when both input variables A and B are 1, otherwise itis 0. The equation A- + B=Cis normally read as “A and B equals C”. Figure 6.2. Truth table for logical AND (:) operator. Complementation OR and AND are binary operations because they operate on two variables. Complementation is a unary operation defined on a single variable © scanned with OKEN Scannerfe Chapter 6 Hoolean Alget ba and |, The symbol ‘=" is used for complementation operator, [His alse Known as meaning operator, Hence, we write A “complement of A°, or (A+B) meaning “complement of Ae B.” Complementation of a variable is the reverse of its value Hence, if A= 0, then A = 1 and if A= 1, then A= 0. Figure 6.3 shows the truth table for logical NOT (-) operator. A iS” figure 6.3. Truth table for logical Noy, read as “complement of A” or “not of A” Vey Operator Precedence he two generate different values for A= 1, B=0, ang recedence rules are needed to OM Does A +B + C mean (A +B)- Cor A+ (B because we have (I + 0)-0=0and 1+ (0-0) evaluate Boolean expressions. The precedence rules for Boolean ope! 1. Hence, operator Pr ators are as follows: 1. The expression is scanned from left o right. 2. Expressions enclosed within parentheses are evaluated firs All complement (NOT) operations are performed next. 4, All" (AND) operations are performed after that Finally, all +” (OR) operations are performed in the end. das A +(B + C). Similarly, for the expression 4. j ults are then ANDed. Again, for the expres. first and the result is then complemented, According to these rules, A + B - C should be evaluate complement of A and B are both evaluated first and the rest (AB), the expression inside the parenthesis (A +B) is evaluate Postulates of Boolean Algebra Postulate 4: Associative Law Postulate 1: (a) A=0, if and only if, A is not equal to 1 a) x+(ytaqety +z (b) A= |, ifand only if, A is not equal t0 0 (b) x-(y-2)=(@-y)-z Postulate 2: Postulate 5: Distributive Law (axe (a) x-(y#2)=XYFX-Z (b) x1 (b) x+y 2=(K+y¥)- (+2) Postulate 3: Commutative Law Postulate 6: (@x+y=y+x (axe (b)x-y=yex (b)x-X=0 ‘These postulates are the basic axioms of the algebraic structure that need no proof. They are used to prove tk theorems of Boolean algebra, © scanned with OKEN Scannera ss Boolean I 7 The principle of Duality revise duatity hetween the operators (AND) and + (OR) and the digits 0 and 1 For ool ebra there 1s In Borer g is consider Fit celal instance. let us © ve + with: by intereh hte from the first r the second row is obtai Known as the principle of duality in ¢ 6.4 in which t Sane “0° with “1, This impe ging = Column 3 o+0-0 | ier) Figure 6.4._lustrating the principle of duality in Boolean algebra algebra has its dual obtainable by interchanging ‘dual theorem automatically holds and need not be ple is that any theorem in Boolea ‘The implication of this F Hence, if theorem is proved, its sa? with © and “0° with “T°. proved separately. Theorems of Boolean Algebra Some important theorems of Boolean algebra are stated below along with their proof. a © @.xtxex bx x=x Proof of (a) Proof of (b) LHS. LHS. “x +x =(x+x)-1 by postulate 2(b) =x-x+0 by postulate 2(a) =(x+x):(x+X) —__ by postulate 6(a) by postulate 6(b) axe ® by postulate 5(b) =x-(x+X) by postulate Sia) by postulate 6(b) 1 by postulate 6(a) =x by postulate 2(a) by postulate 2(b) =RHS. Note that Theorem 1(b) is the dual of Theorem 1( c a) and each step of the proof i i By tml theorem can be derived from the proof of its corresponding pairina similar Oe ie a onan the proof of only pat (a) will be given, Interested readers ean apply the princi Te of deal to varus ps ofthe proof of part (a) to obtain the proof of part (b) for any theorem. ee © scanned with OKEN ScannerChapter 6M Book 6a Theorem 3 (Absorption law) (a) X#X-Y=K (b) x. +Y=X aba Proof of (a) LHS. xexey 7 ; By ox: 14x-Y Y postulate 2(4 i y 1 7 by peas Be =x-(l+y) by postulate 5¢a) six tX) by postulate 6(a) x-(y+]) by postulate 3/4) Xede8 by postulate 5(b) ee by theorem 2(a) xe Xoy by postulate 3(b) 7 by postulate 2¢5) axtk by postulate 2(b) =RHS. =I by postulate 6(a) =RAS. Proof of (b) holds by duality Proof of (b) holds by duality ——~ Proof by the Method of Perfect Induction The theorems of Boolean algebra can also be proved by means of truth tables. In a truth table, both sides of ty relation are checked to yield identical results for all possible combinations of variables involved. In Principle, iti, Possible to enumerate all possible combinations of variables involved because Boolean algebra deals with variables having only two values. This method of proving theorems is called exhaustive enumeration oF pera induction. For example, Figure 6.5 is a truth table for proving Theorem 3(a) by perfect induction method. Similarly, Figue 6.6 proves Theorem 3(b) by perfect induction method. x y xy xtey 0 o oO 0. oO 1 0 0 fl o 0 1 1 1 1 1 Figure 6.5, Truth table for proving Theorem 3(a) by perfect induction method. = ‘Truth table for proving Theorem 3(b) by perfect induction method. Figure 6, © scanned with OKEN Scannersz Boolean Algebra a Theorem 4 (Involution Law) x Proof Figure 6.7 proves this theorem by perfect induetion method | Figure 6.7. Truth table for proving Theorem 4 by perfect induction method. Note that Theorem 4 has no dual because it deals with a unary operator (NOT). Theorem $ (@) x: (Rt+y)=x-y Ox FR ye Kty. Proof of (a) Figure 6.8 proves this theorem by perfect induction method. [ y x ty x+y) xy was 0 0 T 7 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 Figure 6.8. Truth table for proving Theorem (a) by perfect induction method. Proof of (b) Figure 6.9 proves is theorem by perfect induction method. ? 0 0 1 1 T 1 T 1 0 i 1 1 0 0 1 0 Figure 63. Truth tabe for proving Theorem S(t) by perfect induction method © scanned with OKEN ScannerChapter 6 6 Boolean Algebra tae, 66 Proof of (a) oa Figure 6.10 proves this theorem by perfect induction method. 0 1 7 o t 1 1 7 1 0 1 0 fo 1 1 i 0 Figure 6.10, Truth tbl or proving Theorem 618) PY perfect induction method. Proof of (b) Figure 6.11 proves this theorem by perfect induction method. 0 0 0 i ri H T 0 H 0 1 i 0 i 1 o 0 1 0 1 i 1 1 1 0 0 oO 0 Figure 6:1. Truth able for proving Theorem 6() by perfect induction method. ‘Theorems 6(a) and 6(b) are important and very useful. They are known as De Morgan’s law. They can ‘extended to n variables as given below: HFK, #Xy bt X, = Xp Xp Ke x, KK Kye Ky Rt Kt tt Ky Figure 6.12 summarizes the basic Boolean identit ae ven in this table to use the algebra coca Le Readers should become well conversant with the idesti® © scanned with OKEN Scannersa Boolean Functions Dual identities A 1=A A0=0 A-A=A a (A+B)+C=A4(B+C) (A-B)-C=A-(B-C) 8 A(B+C)2A-BHA-C A+B-C=(A+B)-(A+C) | »[AeaneA habia | 10 | A+ A-B=A+B A(A+B)=A°B no | AsBaA-B | Figure 6.12, Summary of basic Boolean identities. BOOLEAN FUNCTIONS BOOLEAN®OtN A Boolean function an expression formed with binary variables, Boolean operators (OR, AND, and NOT), parentheses, and equal to sign, Each variable can be either 0 or 1, and for a get of values of the variables the value of the function can also be either 0 or 1. For example, consider the equation W=x+Y-Z Here W is a function of the variables X, Y, and Z, written as W = f(X, Y, Z), and the right hand side of the equation is called an expression. X, Y, and Z are referred to as literals of this function. Given above is an example of a Boolean function represented as an algebraic expression. A truth table can also be used to represestt a Boolean function. The number of rows in the table will be equal to 2°, where 1 is the number of literals (binary variables) in the function, The combinations of Os and 15 for the rows of this table are easily obtained from the binary numbers by counting from 0 to 2"- 1. The value of the function corresponding to each row of the table is listed in a separate column of the table. Figure 6.13 shows such a truth ~ table for the function W = X + Y - Z. Observe that there are @) possible combinations for assigning bits to three variables, The column labeled W is either a 0 or | for each of these combinations. The table shows that out of eight there are five combinations for which W = 1. -|-|ele|-|-lelo} ¢ |-|-|-|-|olo|-lo} 2 Figure 6.13. Truth table for the Boolean function We x+¥.z © scanned with OKEN Scanner68 Chapter 6 Boo given Boolean funes The question that arises now is — “Is an algebraic expression for UN Wonls, “Is it possible to find two algebraic expressions specifying the same Boolean function? pe Actually, in Roolean algebra we often deal with the problem of finding simpler SxPressions fen eXpression. For example, let us consider following two functions: ee Bek -Fe24k-y-z4x-F and B= x-y4xez 2 Figure 6.14 shows the representation of these two Bs y: functions asa truth table. Observe that function F 0 fee One BESO. 's the same as function F; since both have 0 0 1 ‘dentical Os and 1s for each combination of values Cie |amal e of ‘the ‘three binary variables x, y, and 2. In 0 1 1 general. two functions of m binary variables are 1 0 9. Said to be equal if they have the same value for all 1 oO Z Possible 2" combinations of the literals 1 H 4 1 H i Figure 6.14. Truth table for the Boolean functions: Rak -Y-24K-y-24x-¥ and F = x-Faz, Minimization of Boolean Functions Logic gates (discussed later in this chapter) are used to implement Boolean functions. In such implementaty gach term of a function is implemented with agate and each literal ofthe term forms an input tothe gate He, for a given Boolean function, minimization of the number of literals and the number of terms will reat circuit with fewer components. For example, since functions F, and F, of Figure 6.14 are equal Boolean func, and F has fewer terms, it is more economical to implement the F form than the F, form. To find simpler eis one must know how to simplify Boolean expressions to obtain equal and simpler expressions, What consitz the best form of a Boolean function depends on the application, However, we will give consideration ony to criterion of component minimization achieved by literal minimization, There are several methods used to minimize the number of literals in a Boolean function, However, a discus of all these methods is beyond the scope of this book. Hence, here we will consider only the method of alec: manipulations. Unfortunately in this method, there are no specific rules or guidelines to be followed guarantee the final answer. The only method available is cut-and-try procedure by repeated application of the postulates basic theorems of Boolean algebra. Following examples illustrate this procedure, y following Boolean functions to a minimum number of literals, (Continued on next page...) © scanned with OKEN Scannerjs pootean Functions F< Continued from previous page) ( Solution: (a) Fext oy (KX) (Wy) by postulate 5(b) slaty) by postulate 6(a) =(xty)l by postulate 3(b) =xty by postulate 2(b) (b) Fy =x y eX tery by postulate 5(a) =0+x-y by postulate 6(b) =x-y+0 by postulate 3(a) Bxy by postulate 2(a) OF HR 248 -y-24x-7 HE-2(Ftytn7 by postulate 5(a) =E-2- tye 7 by postulate 3(a) Kezltxy by postulate 6(a) =Reztxy by postulate 2(b) ryt Rezty-z =x-yt®ezty-2 by postulate 2(b) =x-ytK-zty-z-(x+R) by postulate 6(a) Sxcyt¥-zty-gexty-z2-¥ by postujate 5(a) ly t Reztxcy-2tR-y-2 by postulate 3(b) ry 14 Bentecy-24 Rey-z by postulate 2(b) Ly Lexy 248 nt k-y-2 by postulate 3(a) sy (l4+a)+®-z-(1+y) by postulate 5(a) Ly-@4 4% 2-41) by postulate (a) fy itz by theorem 2(a) ony: at by postulate 2(b) (K+0-(y+7) OR ae y by duality from (4) i i use dual expressions in corresponding Note that in B; 6.1, functions F, and F, are the dual of each other and-use d in corre rinimization pa raniea shows the equality offnetons Fi and of Fgre 614 Frtion Fitts the fact that an increase in the number of literals sometimes leads to a final simpler exreson. Obsene that fiction Fis the dual of function Fy. Hence, itis not minimized directly and can be derived easly ofthe steps used to derive function Fi. © scanned with OKEN Scanner10 Chapter 6 #1 Boolean ‘ta lee Complement of a Function Complement of @ Boolean function F i F 1s obtained by interchanging Os for 1s and 18 for 0 inthe tn defining the function. For example, Figure 6.15 defines the function F =x -¥ + -zand its compe ae 1 0 T 0 0 0 I I J Figure 6.18. Truth table for the function F =x. + X -z and its complement F Algebraically, complement of a function may be derived from De Morgan’s theorems whose generalized jy are as follows: A-Ay-A,s These theorems state that complement of a function is obtained by interchanging OR and AND operators ‘complementing each literal. The example below illustrates this method. Applying De Morgan's theorems as many times as necessary, the complements are obtained as follows: = 84 (F+2)-(¥+2) =(x+¥+2)-(x+y+7) Sealjaa) an © scanned with OKEN ScannerBoolean Functions i 5 cedure for deriving the complement of a function is to take the du mpler procedure for the dual of the function and then cee ‘cach literal. This method follows from the generalized De Morgan's theorems. Recall that the dual of comix oad by interchanging OR and AND operators and Oe and ts The example hee isemtes his method Solution: (oF, (F-7+y-2) ‘The dual of Fis: (R+y-+2)-(X+¥ +7) The dual of F, is: x+(¥+7)(y +z) ‘Complementing each literal, we get Complementing each literal we get | | R= (x+¥+z)-(x+y+7) XH(y+z)(F+2) Canonical Forms of Boolean Functions Minterms and Maxterms ‘A binary variable may appear either in its normal form (x) or in its complement form (X). Now, consider two binary variables x and y combined with an AND operator. Since each variable may appear in either of the two forms, there are four possible combinations: X-y, x-J,_-x-y_Each of these four AND terms is called a minterm or a standard product. Similarly, n variables can be combined to form 2" minterms. The 2° different minterms are determined by ‘method similar to the one shown in Figure 6.16 for three variables. The binary numbers from 0 to 2°~ | are listed ‘under the n variables. Each minterm is obtained from an AND term of the 7 variables with each variable being primed, ifthe corresponding bit of the binary number is 0, and unprimed, if itis a 1. Figure 6.16, Minterms and Maxterms for three variables. BEE © scanned with OKEN ScannerChapter 6 m Boolean Algebra and 1, ag % «dis of the form m,, where j denotes the decimal ea, on ‘The figure also shows a symbol for cach minterm the binary number of the minterm designated. Jn variable being primed or unprimed, provide >» he n variables forming an OR term, with Similarly called mavierms or standard sums. combination and their symbolic designations. Any 2" max igure 6.16 shows the eight maxterms for three variables : ned from an OR term of the variables, yay Aariables may be determined similarly, Each maxterm is obtain variable being unprimed, if the corresponding bit is a 0, and primed, and vice-versa Note that each maxterm is the complement of its corresponding minterm if itisal. Sum-of-Products 1 several product terms (minterms) log. A sum-of-products expression is a single product term (minterm) o s added (ORed) together. For example, expression x-¥+X-y is a sum-of:produets expression. Following a, sum-of-products expressions: Foll x Following steps are followed to express a Boolean function in its sum-of-projy, form: Construct a truth table for the given Boolean function. xty xty-z , x-ytz 2, Forma minterm for each combination of the variables that produces a |; oe the function. E-Y+x-¥-Z 3, The desired expression is the sum (OR) of all minterms obtained in Si, 2. For example, in the case of function F; of Figure 6.17, following three combinations of the variables produce a 001, 100, and 111 Their corresponding minterms are K-Y-2, “YZ, and X-y-z ‘Taking the sum (OR) bf all these minterms, function F; can be expressed in its sum-of-products form as: Fa k-¥-2te-P-Z4x-y-2 or F, =m, +m, +m, larly, function F; of Figure 6.17 can be expressed in its sum-of-produicts form as: ZAR YZ+MY-Z or m, +m, +m, +m, . © scanned with OKEN Scannergp fioolean Functions Figure 6.17. Truth table for functions F; and F Itis sometimes convenient to express a Boolean function in its sum-of-products form. If it is not in this form, can be converted into this form by first expanding the expression into a sum of AND terms. Each term is then inspected to see if it contains all the variables. If it misses one or more variables, it is ANDed with an expression Solution: The function has three variables A, B, and C. The first term A is missing two variables (B and C), therefore, A=A-(B+B) =A-B+A-B This is still missing one variable (C), therefore, A=A-B-(C+C)+A-B-(C+C) =A-B-C+A-B-C+A-B-C+A-B-C ‘The second term B - Cis missing one variable (A), therefore, Now, by combining all the terms we get F=A-B-C+A-B-C +A-B-C+A-B-C +A-B-C+A-B-C However, the term A:B-C appears twice in this expression and according to Theorem Ia) we have X+x =x, Hence, removing one of them and rearranging the minterms in ascending order we obtain: -B-C+A-B-C+A-B-C+A-B-C+A-B-C (Continued on next page...) © scanned with OKEN ScannerContinued from previews page) 1s sum-of-minterms form +m; lean function in em, +My a8! ress Boo! m,+™ ted in this notatio rotation is omten used 0 OTE ‘Acan be represe™ A shorteut resample 6 ‘The result of F(AB.C)* E4567 : “the numbers following it are th combat “2 eepresents RINE of the terms. n ng it are the ain se eters in parentieses with F form a list of the variables in the fed to an AND term. fe minterm is convert The summation minterms of the onder taken when th 1 sum terms (maxterms) log, Product-of-Sums ) is a product-of-sums expres; ) or several sm (maxterm) ra @wty js a single sum term (ma ion (X + ¥) For example, expressi jons: A. product-of-sums expression multiplied (ANDed) together. 1 are all product-of-sums express Followin: x Following steps are followed to express a Boolean function i (e+y) produci-of-sums form: (%+9)-2 1. Construct a truth table for the given Boolean function, 2. Form a maxterm for each combination of the variables +7) ty) tY iz produce a 0 in the function. (ty) (R+ytz) : 3, ‘The desired expression is the product (AND) of: maxterms obtained in Step 2. For example in the case of function F of Figure 6.17, following five combinations of the variables produce af: 000, 010, 011, 101, and 110 ‘Their comesponding maxterms are: (xt FFF + Z)(KtytZ , and (X + ¥ +2) (xtyt2), function F; can be expressed in its p ‘Taking the product (AND) of all these maxterms, Relxeytz)(xty4z)-(xt 942) (R+y4Z)(RHF +2) oF roduct-of-sums form as: F, =My-M;-M,-Ms-Mg Similarly, function F, of Figure 6.17 can be expressed in its product-of-sums form as: Fra(xtytz)-QtytZ) K+ ¥ +2) (Ktytz2) oF = My°M,-M-M, its product-of-sums form, it must be first expressed as a product of OR et Toerprss 3 Boolean function is is done by using the distributive law. For example, © scanned with OKEN Scanner15 2 Boolean Functions oo xty zesty (tay illustrates the ‘Then any missing variable (say x) in each OR term is ORed with the form xX Following example illustrates Solution At first, the function is converted into product of OR terms by using distributive law Fex-y+ Ney FR) (ey tz) Lr e2 | (NFR) (AR) (RZ) (Yt) X ty)-(x42)-(y+2) The function has three variables (x, y, and z) and each OR term is missing one variable. Therefore, Rtys KE tyt2-Z =(X+y+z)-(X+y+Z) xtzextzty-Y=(xtzty): (x+zt+¥)=(x ty +z): (x + ¥ +2) yrae Rtytz=(+y+2)-(R+y+2) Now by combining all the terms and retaining only one instance of those that appear more than once, we obtain: : F=(xt+y+z)-(x+ ¥ +z)-(X+yt+z)-(X +y+Z) = My-My-My-M, PESE (8) ‘This may be represented in shortcut notation as: 72: F(%y,2)=110,2,4,5) GTS. ‘The product symbol [] represents ANDing of the maxterms. The numbers following it are the maxterms of the function. The sum-of- products and product-of-sums forms of Boolean expressions are known as standard forms. They are preferred for logic circuit design because of their straightforward conversion into simpler logic gate networks that ‘are more desirable from implementation point of view. In their purest and simplest form, they go into two-level ‘networks in which the longest path for any signal to pass from input to output is through two gates. S42 67S University Library, Kurukshetra University KURU OHETRA, © scanned with OKEN Scanner__Chapter 6 Boolean Algebra ang 1, — ~ a ie, Conversion Between Canonical Forms 4 as sum-of-minterms, equals the sum-of-minterms missing from | function is expressed by those minterms that make the function ¢° "i, n is a 0. For example, the function “4, Complement of a fimetion, expressed function. This is because the original fu while ts complement isa | for those minterm ns for which the fun =m) +m, +m, +m, +m, FABRE (LA S6, thas its complement expressed as F(A,B.C)=X(@.2,3)= m, +m, +m, Taking the complement of F by De Morgan's theorem, we obtain F back in a different form: Fe m,+m,+m, = i, ii, i, = M,-M,-M, = 10.2,3) ‘The last conversion follows from the definition of minterms and maxterms shown in Figure 6.16. From the fgy, it is clear that the following relation holds true: 1] ii,=M, That is, the maxterm with subscript is a complement of the minterm with the same subscript j and vice-versa, The last example has demonstrated the conversion of a function, expressed as sum-of-minterms, into : equivalent function in product-of-maxterms form. The conversion from product-of-maxterms form to suns: minterms form is similar. We now state a general conversion procedure: “To convert from one canonical form to another, interchange the symbol (X with IT or IT with ©) and list those numbers (from all possible numbers in the range 0 to 2°-1, where m is the number of binary variables in the function) missing from the original form.” For example, the function F (x, y,2)=11 (0, 2, 4, 5) is expressed in product-of-maxterms form. Its conversion to sum-of-minterms form is: F(x y,z)=Z (1, 3,67) In this case, there are three variables (x, y, and z). Hence, = 3 and the total number of minterms or maxterms (0 t0 7). The missing terms in product-of-maxterms form (1, 3, 6, and 7), therefore, become part of su rminterms form. : : ae | © scanned with OKEN Scanner BLOGIC GATES [All operations within a computer ate carried ont by means of combinations of signals passing through sta blocks of buill-in circuits known as logic gates. In other words, a logic gate is an electronic circuit fone oF more input signals to produce standard output signals. These lectronic cirenits in a computer lard hat operates on ic gates are the building blocks of all Combinations of multiple logic gates of different types are often used to build electronic circuits in computers. Out of many types of logic gates available, we shall study here only some of the most important ones. These are sufficient to introduce the concept of electronic logic circuit design with the use of logic gates AND Gate An AND gate is the physical realization of logical multiplication (AND) operation. It is an electronic circuit that generates an output signal of 1, only if all input signals are also 1 Two or more switches connected in series behave as an AND gate. Observe from Figure 6.18 that the input current will reach the output point only when both the switches (A and B) are in ON(1) state. There will be no ‘output (output = 0) if either one or both the switches are in OFF(0) state Input | A B ‘Output Figure 6.18. Two or more switches connected in series behave as an AND gate, Behaviour of a logic gate (the state of output signal, depending on various combinations of input signals) is represented conveniently by means of a truth table. Figure 6.19 shows the truth table and block diagram symbol for an AND gate for two input signals. Since there are only two inputs (A and B), 2 E cone only four (2°) combinations of inputs are 0 0 0 possible. Notice that the output is | only when. 0 1 0 both inputs are in 1 state, otherwise itis 0. : - 8 | OR Gate Figure 6.19. Block diagram symbol and truth table for an AND gate. ‘An OR gate is the physical realization of logical addition (OR) operation. It is an electronic circuit that generates, an output signal of 1, if any of the input signals is alsu 1. Two or more switches connected in parallel A behave as an OR gate, Observe from Figure 6.20 —»—1 — that the input current will reach the output point Input ‘Output, when any one of the two switches (A or B) are in ON(1) state. There will be no output only when B both the switches are in OFF(0) state. Figure 6.20. Two or more switches connected in parallel behave as an OR gate, © scanned with OKEN Scanner— in Chapter 6 M Boolean Atpehyy and 1 Figure 621 shows the tith table and Mock diagram symbol for an OR gate for two input ied output is T when any of the input signals is 1. Its 0 only when both inputs are 0. als Ni, Figure 6.21. Block diagram symbol and truth table for an OR gate, ‘ust as + and - operations could be extended to several variables by using associative law, Eanes can Also have more than two inputs. Figure 6.22 shows three-input AND and OR gate input combinations for each. Notice that the output of the AND gate with inputs A. B, and C inputs are 1, so that we write the output as A - B- C. Similarly, the OR gate with in ‘fany one of the inputs is 1, so that we write the output as A+B + C. AND sates S and the isa onlyi puts A, B, and C h, Salo. The above argument can be extended. A four-input AND gate has a 1 output only when al four inputs are four-input OR gate has a | output when any of its inputs is a 1. & oer: A B c (@) Three-input AND gate. (©) Three-input OR gate. Figure 6.22. Block diagram symbol and truth table for (a) Three-input AND gate and (b) Three-input OR gate. NOT Gate ; 4 NOT gate is the physical realization of complementation operation. It is an electronic circuit that generatest reverse of the input signal as output signal. It is also known as an inverter because it inverts the input. Figure 6.23 shows the truth table and block diagram symbol for a NOT gate. Recall that complements Ghezition is unary operation defined on a single variable, Hence, a NOT gate always has a single input Fe 6.23 also shows that two NOT gates connected in series give an output equal to the input. This is the counterpart to the law of the double complementation, A=A. © scanned with OKEN ScannerFigure 6.23. (a) Block diagram symbol and truth table for NOT gate, (0) Two NOT gates in series. NAND Gate ‘That is, the output of NAND gate will be 1 if any one of the inputs is a 0, and it when all inputs are 1. ill be 0 only A— ~ : cmat ‘ANAND gate is a complemented AND gate Inputs SEEE Se ye 6.24 shows the truth table and block 7 diagram symbol for a NAND gate. The symbol t i “t? is usually used to represent a NAND operation in Boolean expressions. Hence, g.03.24 gio dagnamaymboland an able fev @ NAND oe Bee igure 6. iagram symbol and truth table for a e ATB=A-B=A+B. 7 Pree ia An AND gate followed by a NOT gate operates as a NAND gate (see Figure 6.25). In the figure, the output of the ‘AND gate will be A-B that in turn is fed as input to the NOT gate, Hence, the final output will be complement of A-B, which.is equal to (A-B) or A+B or AT B. In fact, the small circle on the output of NAND gate (see Figure 6.24) represents complementation. pep Figure 6.25. NAND gate realization with an AND gate and a NOT gate. A B. -B=A+B=ATB Multiple-input NAND gates can be analyzed similarly. A three-input NAND gate with inputs A, B, and C will have an output equal to A-B-C or A+B+C meaning that the output will be 1 ifany of the inputs is a0, and it will be 0 only when all three inputs are 1. NOR Gate A.NOR gate is a complemented OR gate. Tati, the output of a NOR gate willbe 1 only when al inputs are 0, and it will be 0 if any input is a 1. © scanned with OKEN Scannerchapter 6 M Boolean Algebra any, epee mote Alt 204 Lope Figure 6.26 shows the truth table and block diagram symbol for a NOR gate. The symbol «4 ‘Spresent a NOR operation in Boolean expressions, Hence, AL B= A+B = A-B. 7 A.B A B does hone a net pa oO 1 i #5 way Figure 6.26. Block diagram symbol and truth table for a NOR gate. An OR gate followed by a NOT gate operates as a NOR gate (see Figure 6.27). In the figure, the out gate will be A+B th at in turn is fed as input to the NOT gate. Hence, the final output will be g A+B, which is equal to (A+B Put of omple )or A-B or AVB. In fact, the small circle on the output of NOR. -omplementation, Figure 6.26) represents ¢: Multiple-input NOR gates can be analyzed similarly. A three-input NOR gate with inputs A,B, and C wij an output equal to A+B. *C oF A-B-C meaning thatthe output will be | only when all thee inputs ang will be 0 if any of the three inputs is a 1, A B A+B A-B=AlB ‘igure 6.27. NOR gate realization with an OR gate and a NOT gate, LOGIC CIRCUITS © scanned with OKEN ScannerLogie Circuits 81 \ (.. Continued from previous page) olution: Input A is fed to the NOT gate, whose output will be A. Inputs B and C are fed to the OR gate, whose output will be B+ c. These two outputs (A and B+ C) are in tum fed 48 input to the AND gate, whose output will be AB*O), Hence, D = A -(B +C) isthe Bootean expression forthe ‘output of the given logic circuit. Solution: The output of the OR gate is ASB ~ @ The output of the first AND gate is AB 7 ) Expression (b) is fed as input to the NOT gate, whose output will be a ~ (©) Now, expressions (a) and (c) are fed as inpu (A+B): (AB) Hence, C= (A +B)- (A-B) is the logic expression for the ‘output produced by the given logic circuit. 1 to the second AND gate, whose output will be © scanned with OKEN Scanner0 Chapter 6 @ Boolean Algebra and Lo At point 1, the output of the OR gate is A+B wee (@) At point 2, the output of the NOT gate is ce O) At point 3, the output of the NOT gate is ere © ‘The inputs to the AND gate at point 4 are (A + B), C, and D. Henee, its output will be (A+B)-C-D eae = (d) “The inputs to the AND gate at point 5 are (A +B), C, and D. Hence, its output will be (A+B)-C-D -- (e) Finally, the inputs to the OR gate at point 6 are (d) and (¢). Hence, its output will be (A+B)-C-D+(A+B)-C-D Hence, E=(A+B)-C-D +(A+B)-C:D is the Boolean expression for the output of the given logic circuit. © scanned with OKEN Scannerconverting Expressions to Logic Circuits We just now saw few examples that illustrate the method of deriving a Boolean expression for a given logic jit, The reverse problem of constructing a logic circuit for a given Boolean expression is also not difficult ire : ee We Sie three logic gates ~ AND, OR, and NOT are said to be logically complete because any Boolean expression can te realized using these three gates only. The method of constructing logic circuits for Boolean expressions, by ting these three gates only, i illustrated below with a few examples © scanned with OKEN Scanner84 Chapter 6. Boolean Algebra, age eer cr le (+. Continued from previous page) Solution, ytz z The desired logic circuit is shown above and is self-explanatory. ees Solution: ANO (x+y+2} (43) G5) Ana’ Y gets « gate For: ‘The The desired logic circuit is shown above and is self-explanatory. The diag NA The Universal NAND Gate We sal that AND, OR, and NOT gates are logically complete because any Boolean expression can be rit ae lese three gates, However, the NAND gate, introduced in the Previous section, is said to be a univer?! ause itis alone sufficient to implement any Boolean expression, : To show that any Boolean expressi i nted wit ; t Pression can be implemented with NAND gates only, we need to show logical operations AND, OR, and NOT can be implemented with NAND gates. Figure’ 6.28 shows this: © scanned with OKEN Scanner(2) NOT gate implementation A AB \ ABSA B (©) AND gate implementation > B [jos (c) OR gate implementation, —— p A-B=A+B=A-B Figure 6.28. Implementation of NOT, AND, and OR gates by NAND gates. ANOT operation is obtained from a single-input NAND gate that behaves as an inverter. ‘An AND operation requires two NAND gates. The first one produces the inverted AND result and the second one acts as an inverter to obtain the normal AND output. A single-input NAND gate is a normal two-input NAND gate with both inputs combined into one [see Figure 6.28(a)]. For an OR operation the normal inputs A and B are first complemented by using two single-input NAND gates. The complemented variables are then fed to another NAND gate producing the normal ORed output. The implementation of Boolean expressions with NAND gates may be obtained by means of a simple block diagram manipulation technique. The method requires drawing of two other logic diagrams before obtaining the NAND logic diagram. Following steps are to be carried out in sequence: Step 1: From the given Boolean expression, draw a logic diagram with AND, OR, and NOT gates. Assume that both normal (A) and complement (A) inputs are available. Step 2: Draw a second logic diagram with equivalent NAND logic substituted for each AND, OR, and NOT gate. Step 3: Remove all pairs of inverters connected in cascade from the diagram because double inversion does not perform any logical function. Also, remove inverters connected to single external inputs and complement the corresponding input variable. The new logic diagram, so obtained, is the NAND gate implementation of the Boolean expression. © scanned with OKEN ScannerChapter 6. Boolean Algebra and Loy, 86, = Solution: “The AND/OR implementation for the given Boolean expression is drawn in Figure 6,25, Step 2: Now, each AND gate is substituted by two NAND gates [as in Figure 6.28(6)] and each, sme is substituted by three NAND gates [as in Figure 6.28(c)]- Figure 6.290) shows resulting logic diagram. Note that Figure 6.29(b) has seven inverters (single input Nay tzates) and five two-input NAND gates. Each two-input NAND gate has a number in the gate symbol for identification purpose. Pairs of inverters connected in cascade (from each AND box to cach OR box) are Temoves because they form double inversion, which has no meaning. The inverter connected ,, input A is removed and the input variable is changed from A to A . Figure 6.29) sho, the resulting NAND logic diagram with the number inside each NAND gate identifying ,, gate from Figure 6.29(b). Step 1 Step 3: NAND gates required to implement a Boolean expression is, The example demonstrates that the number of ef x to the number of AND/OR gates, provided, both normal and complement inputs are available. Oth, inverters must be used to generate any required complemented input. Solution: Step 1: The AND/OR implementation for the given Boolean expression is drawn in Figur 6.30(a). Step 2: Now, the NAND equivalent of each AND and each OR gate is substituted resultns in Figure 6.30(b). Note that Figure 6.30(b) has six inverters (single input NAND gates) ant four two-input NAND gates. Step 3: One pair of cascaded inverters may be removed. In addition, the three external inputs A B, and E going directly to inverters are complemented and the corresponding inverts are removed. Figure 6.30(c) shows the final NAND gate implementation, so obtained. The number inside each NAND gate of Figure 6.30(c) corresponds to the NAND gate of Figure 6.30(b) having the same number. For this example, the number of NAND gates required is equal to the number of AND/OR gates plus an adit inverter at the output (NAND gate number 5). In general, the number of NAND gates required to implen Boolean expression equals the number of AND/OR gates except for an occasional inverter. Tis is true onl} both normal and complemented inputs are available because the conversion forces certain input variables ‘complemented. a el © scanned with OKEN ScannerAS AB 3_| cE BD) 2p > Lana AtBD . al . C(A+B-D) (@) AND/OR implementation, SABA BD) A-BsC-(4+B-0) E L C-(A+B-D) t D= B+c(a+B-D) v (©) NAND implementation, “Figure 6.29. Step-by-step NAND implementation for the Boolean expression of Example 6.13. © scanned with OKEN ScannerB+C-D (@) ANDIOR implementation. ml ! 1 i (&) Substituting equivalent NAND functions. > #1 .(B+C-D) [*) [pe (c) NAND implementation. oI Figure 6.30. Step-by-step NAND implementation for the Boolean expression of Example 6.14. © scanned with OKEN ScannerThe Universal NOR Gate Jp fanetion is the dual of NAND fisnetion xo : Nene, all procedures and rules for NOR logic form a dual of the corresponding procedures and rules for N. AND logic. Like N AND gate, NOR gate is alsa universal boca fone suTicient to implement any Roofean expressicn 7 alone To show that any Boolean expression can be implemented with NOR gates only. we need to show ¢ logical ions AND. OR, and NOT ean be operat implemented with NOR gates. Figure $7) oa (8) NOT gate implementation 6 A AGB A (©) OR gate implementation, > B +B=B (©) AND gate implementation. Figure 6.31. Implementation of NOT, OR, and AND gates by NOR gates, ANOT operation is obtained from a single-input NOR gate, which is yet another inverter ciruit ‘An OR operation requires two NOR gates. The fi as an inverter to obtain the normal OR output. A inputs combined into one [see Figure 6.31(a)}. rst one produces the inverted OR result and the second one acts gle-input NOR gate is a normal two-input NOR gate with both For an AND operation the normal inputs A and B are first comy iplemented by using two single-input NOR gates. ‘The complemented variables are then fed to another NOR gate pi roducing the normal ANDed output. Like in the case of NAND gate, the implementation of Bo olean expressions with NOR gates may be obtained by ‘carrying out the following steps in sequence: Step 1: For the given Boolean expression, draw a logic diagram with AND, OR, and NOT gates, Assume that both normal (A) and complement (A) inputs are available. Step 2: Draw a second logic diagram with equivalent NOR logic substituted for each AND, OR, and NOT gate. Step 3: Remove all pairs of inverters connected in cascade from the diagram because double inversion does not perform any logical function. Also, remove inverters connected to single extemal inputs and complement the corresponding input variable. The new logic diagram, so obtained, is the NOR gate implementation of the given Boolean expression, © scanned with OKEN ScannerChapter 6. Boolea® Algebra ang 90 . Solution: Step 1: The AND/OR implementation for the given Boolean expression is drawn in Figure Step 2: Now, cach OR gate is substituted by two NOR gates [as in Figure 6.31(b)] and ¢ gate is substituted by three NOR gates [as in Figure 6.31(c)]. Figure 6.32(h) jh resulting logic diagram. Note that Figure 6.32(b) has eight inverters (single input Noy and five two-input NOR gates. Step 3: One pair of cascaded inverters (from the OR box to AND box) may be removed. In the five external inputs A, B, B, D, and C going directly to inverters are complem, the corresponding inverters are removed. A AB | [) +C-(A+B-D) B_4 B-D D A Ay Ws R aay! Addi, ented A+B-D c c-(A+B-D) (2) AND/OR implementation (A+B-D) (b) Substituting equivalent NOR functions. (Continued on next page) © scanned with OKEN Scanner(©) NOR implementation Figure 6.32. Step-by-step NOR implementation for the Boolean expression of Example 6.15 Figure 6.32(c) shows the final NOR gate implementation, so obtained. The number inside each NOR gate of Figure 6.32(c) corresponds to the NOR gate of Figure 6.32(b) ha the same number. The number of NOR gates in this example equals the number of AND/OR gates plus an additional inverter in the output (NOR gate number 6). In general, the number of NOR gates required to implement a Boolean expression equals the number of AND/OR gates except for an occasional inverter. This is true only if both normal and complement inputs are available. Otherwise, inverters must be used to generate any required complemented input. | Combinational circuits are more frequently constructed with NAND or NOR gates than with AND, OR, and NOT gates because NAND and NOR gates can be easily constructed with transistor circuits, and Boolean expressions can be easily implemented with them. Moreover, NAND and NOR gates are considered superior to AND and OR gates because they supply outputs maintaining the signal value without loss of amplitude. OR and AND gates sometimes need amplitude restoration after the signal travels through a few levels of gates. Exclusive-OR and Equivalence Functions Exclusive-OR and equivalence, denoted by ® and ©, respectively, are binary operators that perform following Boolean functions: A@B=A BtA.B AQB=A-B+A-B Figure 6.33 and Figure 6.34, respectively show the truth tables and block diagram symbols for exclusive-OR and ‘equivalence operations. Observe that the two operations are complement of each other. Each is commutative and associative. Because of these two properties, a function of three or more variables can be expressed without Parentheses as follows: (A@®B)®C=A@(BOC)=A@BOC (A@B)OC=AO(BOC)=AOBOC © scanned with OKEN ScannerChapter 6 ® Boolea, A + >— CHA@ROA BEAR oo o $——JD— coronas a Figure 6.33. Block diagram symbols and truth tabh Inputs AOB=A-B+A-B B oO 1 oO +|-lolo] > 1 Figure 6.34. Block diagram symbol and truth table for Equivalence operation, Exclusive-OR and equivalence operations have many excellent characteristics as candidates for jp However. they are expensive to construct with physical components, They are available as standard [got IC packages but are usually constructed internally with other standard gates. For example, Figure 6 the implementation of a two-input, exclusive-OR function with AND, OR, and NOT gates. Figure 6350 NAND gates. 4 at its implementation A (2) Implementation of Exclusive-OR operation with AND/OR/NOT gates. (©) Implementation of Exclusive-OR operation with NAND gates. Figure 6.35. Logic diagrams of Exclusive-OR function. —d © scanned with OKEN Scannerx Design of Combinational Cirewits Only a limited number of Boolean expressions can he expressed exclusively in t f exelusive-OR oF equivalence operations. Nevertheless, these expressions The two functions are particularly useful in arithmetys, DESIGN OF COMBINATIONAL CIRCUITS Design of a combinational circuit starts from the verbal outline of the problem an a logic circuit The procedure involves following steps. See eee 1. State the given problem completely and exactly Imterpret the problem to determine available input and required output variables 3. Assign a letter symbol to each input variable and each output variable 4. Design a truth table that defines the required rel 5. 6. lations between inputs and outputs. Obtain the simplified Boolean expression for each output Draw a logic circuit diagram to implement the Boolean expression. ‘The design procedure is illustrated below with the design of adder circuits because addition is the most basic arithmetie operation for any computer system, The following four rules summarize addition in binary number system: 0+0=0 O+1=1 1+0=1 1+1=10 The first three operations produce a single-digit sum, but when both augend and addend bits are equal to I, the sum consists of two digits. The higher significant bit of this result is called a carry. When both augend and addend numbers contain more than one digit, the carry obtained from addition of two bits at any stage is added to the next pair of significant bits. A combinational circuit that performs the addition of two bits is called a half-adder. One that performs the addition of three bits (two significant bits and previous carry) is called a full-adder. The name of the former comes from the fact that two half-adders can be employed to implement a full-adder. Design of Half-Adder From the definition given above, a half-adder needs two binary inputs and two binary outputs, The input variables designate the augend and addend bits whereas the output variables produce the sum and carry bits. Let A and B be the two inputs and S (for sum) and C (for carry) be the two outputs. The truth table of Figure 6.36 defines the function of a half-adder. Figure 6.36. Truth table for a hal-adder -|-|s|o}> —|e|-lel= ele|e]o} © scanned with OKEN ScannerChapter 6M Boolean Algebra ang eee on ee ble, are: The Boolean expressions for the two outputs, obtained from the truth tal \-B4AB —— — { halfadder is limited in the sense that it can add only two single bits Although, it generates a cary frig higher pair of significant bits it eannot accept a cany generated from the Previous pair of lower significa is full-adder solves this problem, Design of Full-Adder A full-adder forms the arithmetic sum of three input bits, Hence, it consists of three inputs and two outputs Ts of the input variables (A and B) represent the augend and addend bite and the third input variable (D) reps the carry from the previous lower si iti tol. S 0 i i 0 1 0 0 Tt re J © scanned with OKEN Scanner95 sme sum-of products expressions for the two outputs can be obtained directly from the truth table and are given below? - s-A-B-D+A-B-D+A-B-D4A-B.D -B-D+A-B-D+A-B-D+A-B-D we expression for S cannot be simplifie ce athe th is possible to simplify the expression for C as follows’ C=A-B-D+A-B-D+A-B-D+A.B.D AB-D+A-B-D+A-B-D+A-B-D+A-B-D+A-B-D (since x =x =x) =(A-B-D+A-B-D)+(A-B-D+A B-D)+(A-B-D+A-B-D) =(A+A) ‘B-D+(B+B)-A-D+(D+D)-a-B =B-D+A-D+A-B (since x +5 =x) =A-B+A-D+B-D Hence, we obtain the following expressions for the two outputs: A-B-D+A-B-D+A-B-D+A-B.-D C=A-B+A-D+B-D Figure 6.39 shows the logic circuit diagrams to implement these expressions. A-B-D A A c ABD iy DE> UIDI> vIE>! CoD) (2) Logic circuit diagram for sum. (0) Logie circuit diagram for carry. Figure 6.39. Logic circuit diagrams for a ful-adder. A full-adder can also be implemented with two half-adders and one OR gate (see Figure 6.40). as HA (A@B)-D c HA P A@BOD Figure 6.40, Implementation of a full-adder with two half-adders and one OR gate. © scanned with OKEN Scanner36. 7 Chapter 6 ®@ Bo The S output from the second half-adder is the exelusive-OR of D and the output of the first halfadg, ler yiy S=[ABHA B).D+(A-B+A-B)-D =(AB-A-B)-D+A-B-D4A-B-D =[A4 B)(A+B) D+ABD+A-BD =(A+B)(A+B)-D+A-B-D+A-B-D =(A-A+A-B+A-B+B-B)-D+A-B-D+A-B-D u (A-B+A-B)-D+A-B-D+A-B-D =A-B-D+A-B-D+A-B-D+A-B-D =A-B-D+A-B-D+A-B-D+A-B-D The carry output is: C=(A-B+A-B)-D+A-B =A-B-D+A-B-D+A-B-(D+D) =A-B-D+A-B-D+A-B-D+A-B-D This can be simplified, as before, to C=A-B+A-D+B-D A Parallel Binary Adder Parallel binary adders are used to add two binary numbers. For example, if we want to add two four-bit nuns ‘we need to construct a parallel four-bit binary adder (see Figure 6.41). Such an adder requires one halfaite (denoted by HA) and three full-adders (denoted by FA). The binary numbers being added are Ay As Az A; anil By B; By, and the answer is: Ay AS Ay 4 Ce pee pee F [ FA a FA a FA ta I | 8s ! Ss Ss Si Figure 6.41. A parallel four-bit binary adder. at The first column requires only a half-adder. For any column above the first one, there may be a carty f preceding column. Therefore, we must use a full adder foreach column above the fist one _d © scanned with OKEN Scannerfate how the adder of Figure 6.4) yy illus devant of decimal 9 is 1001 and that of equiv inp ‘as shown in the figure, the half-adder adds 1+ jalkadder, which adds 0+ 1+ 1 to geta sum of adds 0-+0+ 1 to get a sum of | and a carry of 0 |, The final output of the system is 10100. Th decimal sum of 9 and 11. The parallel binary adder of Figure 6.41 has limited cap: using tare 1111 and 1111, Hence, its maximum capacity is: 15 Mt #15 +1 30. 110 ” Otks, let us see how it will add two numbers say. 9 and 11. Binary decimal 11 is 1041. F gure 6 1 to give a sum of 0 and a carry I. The carry goes into the first O and a carry of 1. This carry goes into the next full-adder, which The last full-adder adds 1 +1 + 0to get a sum of 0 and a carry of 1¢ decimal equivalent of binary 10100 is 20, which is the correct acity. The largest binary numbers that can be added by The capacity can be increased by connecting more full-adders to the left end of the system. For instance, to add six-bit numbers two more full-adders must be connected, and for adding eight-bit numbers four more full-adders must be connected to the leftmost full-adder of Figure 6.41. Points to Remember 1. Boolean algebra deals with binary number system. ‘That is, the variables used in Boolean equations may have only two possible values (0 and 1). 2. In Boolean algebra the ‘OR’ operator used for logical addition is represented by the symbol “+”; the ‘AND’ ‘operator used for logical multiplication is represented by the symbol “"; and the ‘NOT” operator used for ‘complementation is represented by the symbol ‘— As regards precedence of Boolean operators, “NOT” operator takes precedence over ‘AND’ and ‘OR’ ‘operators, and ‘ANDY operator takes precedence over ‘OR’ operator. ‘The postulates of Boolean algebra are (@) A=0, ifand only if, A is not equal to 1 (b) A= 1, ifand only if, A is not equal to 0 (c) x+0 (@ x. (©) x+y () x (g) x+(y+2)=(K+y)+z (h) xy (X-y)-Z () xQeDR=Kyexee (Ky) (+2) In Boolean algebra, there is a precise duality between the operators - (AND) and + (OR) and the digits 0 and 1 This property is known as the principle of duality Figure 6.12 summarizes the basic Boolean identities. ‘They are very helpful while dealing with Boolean algebra, ‘A Boolean function is an expression formed with binary variables, the two binary operators OR and AND, the unary operator NOT, parentheses, and equal to sign, © scanned with OKEN Scanner98 8, u 12. 13, 14, Complement of a Boolean function F is F and is obtained by interchanging Os for Is and Is for Os in the truth table defining the function A sum-of-products expression is a single product term (minterm), or several product terms (minterms) logically added (ORed) together. For example, Write the dual of following Boolean expressions: (a) A+B () A+B (b)A+B+C () A-(A+B) ()A-B+A-B (f)A+A-B 16 17 Chapter 6 1 Boolean Algebra ang 2% XG i ANAND gate is a complemented AND y output of NAND gate will be 1 if any cae Ta, 10, and willbe 0 only when all inputs arg be 4 A NOR gate is a complemented OR ouput of a NOR gate will be T ony fa: Th, 0, and it will be 0 if any input isa 1, all inp expression XY + Xy is a sum-ofproducts 1g, ‘the logic gates are interconnected to f expression, netorks known a combinational ogi cy 8 A product-of-sums expression is a single sum term 19, The AND, OR, and NOT gates are logical, (maxterm), or several sum terms (maxterms) logically because any Boolean expression can be req multiplied §=(ANDed) together. For example, these three gates. Need expression (X + y) «(x + ¥) is a produetof-sums 4) a any gate is said to be a universal gary expression. is alone sufficient to implement any Boolean <® The sum-of-products and productof-sums forms of Similarly, the NOR gates also a universal se Boolean expressions are known as standard forms. |. Exclusive-OR and equivalen [io ate prefered for logic dsin because 7 clemne OM and umaency sient & a di niga rin rex , are bin . fo their straightforward conversion to very simple gating Bolen faciiots FT fll networks. eS Ade i : it th A@B=A'BtaA.B logic gate is an electronic circuit that operates on =A-B+AeR ‘one or more input signals to produce standard output AOB-A-B+A-B Signals. These logic gates are the building blocks of 22. Design of a combinational circuit starts from the » all electronic circuits in a computer. outline of the problem and ends in a logic ¢ : . diagram. The procedure involves followin; ‘stey ‘An AND gate is the physical realization of logical : B eps multiplication (AND) operation. It is an electroni (@ Biate the given problem completely and ay n (b) Interpret the problem to determine ayat circuit that generates an output signal of 1, only if all , input signals are also 1 ‘input and required output variables, put sigi (©) Assign a letter symbol to each input vatsbe An OR gate is the physical realization of logical each output variable. addition (OR) operation. It is an electronic circuit that (@ Design a truth table that defines the rep generates an output signal of 1, if any of the input relations between inputs and outputs. signals is also 1. (©) Obtain the simplified Boolean expression . each output. A NOT gate is the physical realization of aie ic circuit 7 leme complementation operation. It is an electronic circuit © Etleebet athe tate betes dace that generates the reverse of the input signal as output ™ ' signal. It is also known as an inverter because it inverts the input. Questions Explain the principle of duality in Boolean 3. Write the dual of the rule A + A-B=A+B iigebra. How it is useful? d es eee 4. Prepare truth tables for following Booles" expressions if G@AB+HAB (ABC a ()AB-C+B-C (F)AB-CHABC (A+B )(A+8) (aro (d) A+B+E (h) A-C+A-C ad © scanned with OKEN Scanner5, State_and prove the two asic theorems. De Morgan's 10. 6. Prove following rules by perfect induction method (0) BHABHA ()ALAB= AGB WA(AtC)=a (2) (A+B)-(A-B)=A-Be B.A (©) (A+B)-(A+B)=A-BL ACB 7. Simplify following Boolean expressions and draw logic cireuit diagrams for your simplified 1- expressions by using AND, OR, and NOT ates: (a) RY -24 Ry Zex-FeZtx-Fez (b) Ry-Z4K-F-Zexyezexcyz (©) A-C+A-B+A-B-C4B-C (@) A-B-C+A-B-C+A-B-C+A-B-C+A.B-G (© (A+B+C)-(A+B+C)(A+B42)-(AsB0) (£) (A-B-C)-(A-B-C+A-B-C+A-B-C) 8. Find the expressions: complement of following Boolean (a) AB+A-C “(b) A-B+A-B (0) A-(B-C+B-C) (4) A-(B+C) (e) (A+B)-(B+C)-(A+C) () A.(B+0)-(E+B) (g) A-B+(A-B)-(B-C+B-C) 9. Express following Boolean expressions in their sum- oftproduets form. Ensure that each term has all literals (a) A-(B+C) (b) (A+B)-(B+C) (©) (A+B)-€ (d) (A-B).(A-B-C+A-C) (©) (A+C)-(A+B+0)-(A+B) (1) (A+C)-(A-BHA-C+B-C) Express following Boolean expression: product-of-sums form. Fnsure that each Titerals (@yAsBe (by ABE (AsBec (8) (A-B).(A-C+ B.C) (©) (A-B) (8+) (fF) A+A-B+A-C What will be the outputs of following logic circuits for specified inputs? : DS © t=p)— DVL =a @ : 4)— D7 i= | }- © scanned with OKEN ScannerChapter 6 Boolean Algebra and | Li 100 19, Consrut loge circuit digram fo, ha oe using NOR gates only. be B Why combinational circuits are coy, = a frequently with NAND or NOR eu than : OR, and NOT gates? c 21. Prove that 5. >— @ (A@B)0C=A(BaC) B (6) (40B)OC=A@(BEc) D 22. Construct @ logic circuit diagram for rch, ‘ ing NOR gates only, " 12. Construct logic circuit diagrams for following function by using — oolean expressions by using AND, OR, sd a. Lr diagram fr ex gates: function by using NAND gates only, @ABraAB 24. A logic circuit has three inputs, A, Bang t 7 Generates an output of | only when & =, Boy (©) (A+B) (« 8) 9, or when A= 1, B= 1, co ©. Dee © (ASB)-(As0).(e +8) combinational circuit for this system Re 25. A logic circuit has three inputs, A, B, (4) A-B+(A-B) (8-c+B.0) and : cena et OF Dany igs fol (e) (A+B) (A+c).(Asa) conditions: 13. “AND, OR, and NOT Sales are logically complete”. Discuss, 14, Why NAND and NOR gates are called “universal gates? it for this system, 15, Draw the inplenetaion oF the logical operations 26. ork that will have outputs » OR, and NOT wit =1,B=0,C=0:4° (a) NAND gates only, and 4 (None are to be 1 for alles 16. Construct logic circuit diagrams for the Boolean 27. three-bit messa Gapressions of Question 12 by using NAN ‘ates Parity, Paty 90 e° Pansmitted “a I in IY generator Senerates a pari! only, That eek the total Humber of 1s odd (incluié 17. Construct logic circuit diagrams for the Boolean tis, P=, only when the number of Isint expressions of Question 12 by using NOR gates Sven. Design a combinational li only, 28, arity, SeNerator, 18. Construct logic circuit diagram for a halfadder by using NAND gates only. al logic circuit to generat! Xadecimal digits. © scanned with OKEN Scanner