8086 16-Bit Microprocessor UNIT-I 8086 16-Bit Microprocessor Features of 8086 Microprocessor: 1) Itis a 16 bit microprocessor. 2) 8086 has a 20 bit address bus that can access up to 2” memory locations (1 MB). 3) It has two blocks: BIU and EU, 4) It provides 16-bit registers. AX.BX,CX,DX,CS.SS,DS,ES.BP,SP.SLDLIP & FLAG 5) Ithas multiplexed address and data bus ADO- ADIS and A16 ~ A19. 6) It works in a multiprocessor environment. Control signals are generated by an external BUS Controller 7) 8086 is designed to operate in two modes i.e, Minimum & Maximum, 8) It can pre-fetches up to 6 instruction bytes from memory and queues them in order to speed up instruction execution. 9) Interrupts:-8086 has 256 vectored interrupts. 10) Provides separate instructions for string manipulation. 11) Operating frequency range is 6-10MHz. OR Clock frequencies SMHz, MHz, 10MHz. 12) It can support up to 64K 1/0 ports. 13) It requires +5V power supply. 14) 8086 IC Contains 40 Pins. Pin Description: Pin Signals of 8086 are divided into 3 types: 1. Signals common in Maximum and Minimum mode. 2. Signals used Works in Minimum mode. 3. Signals used Works in Maximum mode.8086 16-Bit Microprocessor enpnef 1 “40 AD,, <>} 2 39 AD, <3) 3 38 AD, <>) 4 37 AD, >| 5 36 AD. <>) 6 35 AD, <4 i 8086 x4 AD, <| 33 AD, <> Pin 2 AD, <> 10 31 AD, <4 11 30 AD, <3} 12 Diagram 5, AD, <3 13 28 AD, <3] 14 27 AD, <> 15 26 AD, <>) 16 25 NMI <4 17 24 INTR—| 18 23 cLk J 19 22 GND {20 21 I Veo <> AD., > AD,,/S, > AD,,/S, > AD../S, > AD,./S, [> BHE/S, \— MN/ MX t—> RD > HOLD > HLDA > WR > M10 [> DT/R > DEN [> ALE > INTA <— TEST — READY J RESET Minimum = Maximum ‘mode signals mode signals (RQ/ GT.) Fig: Pin Diagram of 8086 “Signals common in Maximum and Minimum mode: AD15-AD0 or ADO- ADI5 (Multiplexed Address/Data Bus):- > These signals are active high signals. > These pins act as multiplexed address and data bus of the microprocessor. > Whenever the ALE pin is high (1) these pins carry the address, when the ALE pin is low (0) it carry the data. > During TI state of clock cycle it carries address. > During T2, T3 & Ta state they carry address. A19/S6-A16/83:- > These signals are active high signals.8086 16-Bit Microprocessor > These pins are multiplexed to provide the address signals A19-A16 and the status bits S6- 83. > When ALE= I (High) these pins carry the address and when ALE=0 (Low), they ¢ the status lines, S4 S3 Segment Accessed. 0 0 Extra Segment 0 1 Stack Segment 1 0 Code Segment mt a Data Segment > This is active low signal. BHE/S7 stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using high order data bus D8-DI5. This signal is low during the first clock cycle, thereafter it is active. Itis conjunction with Ao, Ag is analogous for the lower byte of the data bus, pins DO-D7. ‘Ao bit is Low during TI state when a byte is to be transferred on the lower portion of the bus in memory or /O operations. V v vVvvyY BHE Ao Word / Byte access 0 0 | Whole word from even address 0 1 Upper byte from / to odd address 1 0 Lower byte from / to even address 1 1 None RD (Read): > Thisis active low signal. > Used to read data from memory or /O Device generated by the microprocessor. Ready: > Itis active high signal. > It is used as acknowledgement from slower /O device or memory.8086 16-Bit Microprocessor > It is Active high signal, when high; it indicates that the peripheral device is ready to transfer data. > This input is used to insert wait state (Tw) into the timing cycle of the 8086. RESET: > Itis active high signal. It is used to reset the microprocessor itself. > After restart microprocessor starts execution from FFFFOH. INTR (interrupt): > Itis active high signal. > This is a level triggered interrupt request input, checked during last clock cycle of each instruction to determine the availability of request. > If any interrupt request is occurred, the processor enters the interrupt acknowledge cycle. NMI (Non-Maskable Interrupt): > NMI stands for Non Maskable Interrupt > Itis active high signal. > Itis an edge triggered signal. > On this pin causes 8086 to interrupt the program it is executing and execute Interrupt service Procedure. > NMLis Non-maskable by software. > Itis active low signal. > Used to test the status of math processor (Co-processor 8087). > BUSY pin of 8087 is connected to this pin of 8086. CLK (Clock): > Itis active high signal. > CLK stands for Clock Signal > Used to provide basic timing for processor operation. > The range of clock frequency between SMHZ to 10MHZ. Vee: © Itis active high signal. > Used to provide power supply for 8086. GND: > Itis active high signal. > Used to provide Ground for internal circuit.8086 16-Bit Microprocessor MN/MX: © Itis active high/low signal. > This pin is used to select either the minimum mode or maximum mode operation of the 8086. > This is pin is connected to +5V (Vcc) then 8086 operates ground then 8086 operates in maximum mode. in minimum mode or to the + Signals used in Minimum mode: INTA: (Interrupt Acknowledge) > Itis active low signal. > When processor receives INTR signal, the processor complete current machine cycle and acknowledge the interrupt by generating this signal. ALE (Address Latch Enable): > Itis active high signal. ALE stands for Address latch enable. Used to indicate availability of valid address on address/data (ADy-AD}s) lines. This pin is connected to latch enable input of latches (8282 or 74LS373).. vy IN: (Data Enable) > Itis active low signal > Stands for Data Enable. > Used to indicate availability of valid data over ADO-ADIS. > Used to enable transreceivers(bi-directional buffers) 8286 or 74LS245 to separate data from multiplexed address/data signal DT/R: (Data Transt (Receive) » Stands for Data transmit/receive. > This output line is used to decide the direction of data flow through the transceivers (bidirectional buffer) > When the processor sends the data, this signal is high and when the processor is receiving data, this signal is low. MAO (Memory/Input Output): > Stands for Memory/Input output. > This signal is used to differentiate between /O & memory operations. > When it is high, it indicates memory operation and when low, it indicates /O operation.8086 16-Bit Microprocessor WR: (Write) > Thisis active low signal. > Used to write data to memory or HO device. HOLD: > Itis active high signal, > Hold is an active high input signal used by the other master controller (DMA) to request microprocessor for gaining the control of address, data and control buses. > When microprocessor receives HOLD request signal, then microprocessor completes current machine cycle i.e. operation and release bus control for other master in the system. active high signal. > Sands for hold acknowledge. > HLDA is signal used by the microprocessor after receiving the HOLD signal. ‘> Signals used in Maximum mode: RQ /GTO, RQ /GT1: (Request/Grant) > These are active low signals > Stands for Request/Grant. > These pins are used by local bus masters used to for the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the pin is bi-directional RQ/GTO having higher priority than RQ /GT1. v v Toa > Itis an active low pin, > It indicates that other system bus masters have not been allowed to gain control of the system bus while this signal low (0). > This signal will be active until the completion of the next instruction. QS1, QS0 (Queue Status): > These are active high signals. > Stands for Queue Status > These signals indicate the status of the internal 8086 instruction queue according to the table shown below: Qsi_ | Qso Status8086 16-Bit Microprocessor 0 0 No operation 0 1 First byte of op code from queue 1 0 Empty the queue 1 1 Subsequent byte from queue > Active low signals. > These stands for status signals. > ‘These status lines are encoded as given below: Interrupt acknowledge fo fo fi fRead VOT fo [i fo [Wwritevo fo ae] a a a [ro 71 [Read memory | [1 0 Pvrite memory | [TT Tinactive 8086 Architectus Q. Draw functional block diagram of 8086 microprocessor. OR Q. Draw architectural block diagram of 8086 and describe its register organization.8086 16-Bit Microprocessor Figure shows block diagram of 8086 microprocessor. Internal architecture is divided into two parts: 1. Execution Unit (EU). 2. Bus Interface Unit (BIU). Execution Unit (EU): ‘The functions of execution unit are: To tell the BIU for fetch data or instructions. ‘To decode the instructions. To execute the instructions. EU has 16 bit ALU to perform arithmetic and logical operations on & bit as well as 16 bit data EU has 16 bit flag register, which contains 9 flags. It contains general purpose and special purpose registers. vvvy vv Bus Interface Unit (BIU): ‘The functions of BIU are: Fetch data or instruetions from memory. > Write data to memory.8086 16-Bit Microprocessor > Write data to por. > Read data from port. BIU contains segment registers (DS, CS, ES, SS), instruction pool or queue. Instruction queue is used to speed up the exe microprocessor, Register organization of 8086: > All the registers of 8086 are 16-bit registers, > The general purpose registers can be used as either 8-bit registers or 16-bit registers. The register set of 8086 can be categorized into 4 different groups. The register organization of 8086 is shown in the figure. 1) General Purpose Registers of 8086. 2) Segment Registers. 3) Pointers and Index Registers. 4) Flag Register General Purpose Registers ax 8x Accumulator Register Base Register x ox Counter Register Data Register Source Index Register 1 Destination index Register ep Bave Pointer Register ” stack Pointer Register ® Inetrction Pointer Register Segment Registers cs I «cote seamen Reistor 0s EE 0210 segment negiter cs [TTT cate seamen neistr ss [Stack Segment Register rcacs [| | ET TATE TB Fog register fa [S[EIFISIST=1S121110) Postctne vt “© General Purpose Registers of 8086.8086 16-Bit Microprocessor AX (Accumulator): vv AX is used as 16-bit register used as accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated as AH. AL can be used as an 8-bit accumulator for 8-bit operation It is used to store the result for arithmetic / logical operations. AILI/O data transfer using IN & OUT instructions use AH/ AL or AX. BX (Base register): BX is a 16 bit register, but BL indicates the lower 8-bit of BX and BH indicates the higher 8-bit of BX. BX is used as Base register to hold the offset address or data in indirect addressing mode. CX (Counter register): The CX register is 16 bit register, but CL indicates the lower 8-bit of CX and CH indicates the higher 8-bit of CX. The register CX is used default counter in case of string and looping instructions. DX (Data Register): The DX register is 16 bit register, but DL indicates the lower 8-bit of DX and DH indicates the higher 8-bit of DX. Itholds the high 16 bits of the product in multiply (also handles divide operations). OR Used with AX to hold 32 bit values during multiplication and division. Used to hold address of VO port in indirect addressing mode. DX may be used as an implicit operand or destination in case of a few instructions, Segment Registers of 8086. There are four segment register in 8086: 1. BeLD Code segment register (CS). Data segment register (DS). Stack segment register (SS). Extra segment register (ES). Code segment register (CS): Itholds starting address of Code segment. It is used for addressing memory location in the code segment of the memory, where the executable program is stored. Code Segment register holds base address for all executable instructions in a program.8086 16-Bit Microprocessor Data segment register (DS): > Itholds starting address of Data segment. > Itpoints to the data segment of the memory where the data is stored. > Data Segment register is default base address for variables Extra Segment Register (ES): > Itholds starting address of Extra segment. > Italso refers to a segment in the memory which is another data segment in the memory Stack Segment Register (SS): > Itholds starting address of Stack segment. > Itis used for addressing stack segment of the memory. > The stack segment is that segment of memory which is used to store stack data. * Pointer and Index Registers of 8086. The pointers contain offset within the particular segments, Instruction Pointer (IP): > Itcontains the offset of the next instruction to be executed. > The pointer register /P contains offset within the code segment. Base Pointer (BP): > Itcontains an assumed offset from the SS register. > The pointer register BP contains offset within the data segment, Stack Pointer (SP): > Contains the offset of the top of the stack > The pointer register SP contains offset within the stack segment. The index registers are particularly useful for string manipulation, The index registers are used as general purpose registers as well as for offset storage in case of indexed, base indexed and relative base indexed addressing modes. Source Index (SI): > Used in string movement instructions. > The source string is pointed to by the SI register. > The register S/ is used to store the offset of source data in data segment. Destination Index (DI): > Itacts as the desti ation for string movement instructions.8086 16-Bit Microprocessor > The register D/ is used to store the offset of destination in data or extra segment. “> Flag Register: The 8086 flag register contents indicate the results of computation in the ALU, It also contains some flag bits to control the CPU operations. Individual bit positions within register show status of CPU or results of arithmetic operations. A 16 flag register is used in 8086. It is divided into two parts: 1. Condition code or status flags: i) CF-Camy flag ii) PF-Parity flag iii) AP-Auxiliary carry flag iv) ZF-Zero flag v) SF-Sign flag vi) OF-Overflow flag 2. Machine control flags i) Direction flag (D) ii) Interrupt flag (/) iii) Trap flag (7) Q. Draw flag ter of 8086 and explain any four flags. overnow | | | T Gemwrtting Direc! Parity flag Interrupt enable Auxiliary flag Dl Martin are Uae Trap. Zero 6 are status flags Sign 3 are contro! flag Fig: Flag register of 8086 CY or CF (Carry Flag):8086 16-Bit Microprocessor > When up performs addition/subtraction of 8 bit if the carry/borrow is generated from the MSB (i.e D7 bit for 8-bit operation, D1S bit for a 16 bit operation), then the carry flag is set (CY=1), otherwise it resets the carry flag (CY=0), PF-Parity Flag: > This flag is set to 1 if the lower byte of the result contains even number of 1’s otherwise it is reset. > When pp performs addition or logical operations on 8 bit number and if number of I's bit in 8 bit result is even number, then it is called as Even parity and parity flag is set (P=1) otherwise it is called as Odd parity and parity flag is reset (P=0). AC-Auxiliary Carry Flag: > This is set if a carry is generated out of the lower nibble, (i.e. From D3 to Dé bit)to the higher nibble. > When up performs addition of 8 bit number and if the carry is generated from D3bit, then auxiliary carry flag is set, otherwise itis reset. Z-Levo Flag: > This flag is set if the result is zero after performing ALU operations. Otherwise it is reset. > When pip performs arithmetic and logical operation of two 8 bit numbers, if the result obtained is zero, then flag is set (Z=1),otherwise it is reset (2=0). S-Sign Fla; s flag is set if the MSB of the re otherwise itis reset. > When up performs arithmetic and logical operations on signed numbers and if the MSB of the result is 1, then sign flag is set. ie. for negative number sign flag is set (S=1), otherwise it is reset (S=0). It is equal to 1 after performi ig ALU operation , 0-Overflow Flag: > This flag is set if an overflow occurs, ie. if the result of a signed operation is large enough to be accommodated in destination register. Control Flags T-Trap Flag: > If this flag is set, the processor enters the single step execution mode. [-Interrupt Flag: > Itis used to disable or enable the INTR interrupt. When this flag is set, 8086 recognizes interrupt INTR. When it is reset INTR is masked.8086 16-Bit Microprocessor D-Direction Flag: > It selects either increment or decrement mode for DI &/or SI register during string instructions. Concept of Pipelining: What is pipelining? How it improves the processing speed. Explain the concept of pipelining in 8086. State the advantages of pipel Answer: > Process of fetching the next instruction while the current instruction is executing is called pipelining. > The technique used to enable an instruction to complete with each clock cycle. > Normally, on a non-pipelined processor, nine clock cycles are required for fetch, decode and execute cycles for the three instructions as shown in Fig (a). > This takes longer time when compared to pipelined processor. > In pipelining, the fetch, decode and execute operations are performed in parallel, so only five clock cycles are required to execute the same three instructions as shown Fig(b). > In 8086, pipelining is implemented by providing 6 byte queue. 6 one byte instructions can be stored in Byte queue. > So, while executing first instruction in a queue, processor decodes second instruction and fetches 3rd instruction from the memory In this way, 8086 perform fetch, decode and execute operation in parallel i. in single clock cycle as shown in above fig (b) > This reduces the execution time. > In 8086, pipelining is the technique of overlapping instruction fetch and execution mechanism. > To speed up program execution, the BIU fetches as many as six instruction bytes ahead of time from memory. > While executing one instruction other instruction can be fetched. Thus it avoids the waiting time for execution unit (o receive other instruction. > BIU stores the fetched instructions in a 6 level deep FIFO. > This improves overall speed of the processor. v Advantages of pipelining: > More efficient use of processor. > Quicker time of execution of large number of instruction. > In short pipelining eliminates the waiting time of EU and speeds up the processing. > To speed up program execution, the BIU fetches as many as six instruction bytes ahead of time from memory. The size of instruction pre-fetch queue in 8086 is 6 bytes. v8086 16-Bit Microprocessor > This improves overall speed of the processor. F D E Fy D EF D E ChE PEA HEPEPELE LCP z= Cycle fig (a) CE eat D-Decode Clock 1 2 304 5 Cycle fig) Memory Segmentation in 8086: Explain memory segmentation in 8086 and list its advantages. Explain concept of segmentation with diagram, Answer: Memory Segmentation: > In 8086 available physical memory space is IMByte > This physical memory is divided into different logical segments and each segment has its own base address. > The physical memory is divided into 4 segments namely-Data segment, Code Segment, Stack Segment and Extra Segment. > Each segment is 64Kbytes & addressed by one segment register. > Data segment is used to hold data, Code segment for the executable program, Extra segment also holds data specifically in strings and stack segment is used (0 store stack data. > Itcan be addressed by one of the segment registers. The 16 bit segment register holds the starting address of the segment. » The offset address to this segment address is specified as a 16-bit displacement (offset) between 0O00H to FFFFH.8086 16-Bit Microprocessor > Since the memory size of 8086 is IMbytes, total 16 segments are possible with each having 64Kbytes. Advantages of Segmentatio > The size of address bus of 8086 is 20 and is able to address 1 Mbytes of physical memory. > The complete 1 Mbytes memory can be divided into 16 segments, each of 64 Kbytes size. It allows memory addressing capability to be 1 MB. © It gives separate space for Data, Code, Stack and Additional Data segment as Extra segment size. > The offset values are from 00000H to FFFFFH. > Segmentation is used to increase the execution speed of computer system so that processor can able to fetch and execute the data from memory easily and fast Vv Physical aiess_ MEMOrY FEEEE HL [at Hotes tess TEE pol Ban Seget @]| extra 8] | Segment Four segment registers iniU 70000 4 a Socom ct se Segment SRF Tepot Sack Sepnet est] evra tou Noms Ra ot ack Se cs on|zomco a] Stack ss ; o[e]o =) | Segment of2f[o[olfe >so000f socom of Sack Seyret 7 FFF H ep ot ote Sgrent ‘Segment registers hold a|| Code the upper 16 bts ofthe 3] | Segment starting addresses of oe four memory segments > 30000 4 Je Bx f coe Segre that 8086 is working with 2FFEH Teo ot a Segnrt atany panicular time, a] | Data 31) Segment 20000 4 ‘ro fot Seonet8086 16-Bit Microprocessor Physical Address Byte FFFFF H Highest Address Srerem ES = 8000 H 64k 80000 H SFFFF H SS = 6000 H 64k 60000 Hi 2FFFFH CS = 2000 H 20000 H eat FFFF RH DS = 1000H 10000 H 64k 09000 H Physical address generation in 8086: Q. Describe mechanism for generation of physical address in 8086 with suitable example. Q. Define logical and effective address. Describe physical address generation process in 8086. If DS=345AH and SI=13DCH. Calculate physical address. Q List the steps in physical address generation in 8086 microprocessor. Calculate the physical address for the given CS=3420H, IP=689AH. Answer: A logical address: is the address at which an item (memory cell, storage element) appears to reside from the perspective of an executing application program. A logical address may be different from the physical address due to the operation of an address translator or mapping function. Effective Address or Offset Address: The offset for a memory operand is called the operand's effective address or EA. It is a 16 bit number that expresses the operand’s distance in bytes from the beginning of the segment in which it resides. In 8086 we have base registers and index registers.8086 16-Bit Microprocessor Generation of 20 bit physical address in 8086:- > > Segment registers carry 16 bit data, which is also known as base address. BIU appends four 0 bits to LSB of the base address. This address becomes 20-bit address. Any base/pointer or index register carries 16 bit offset. Offset address is added into 20-bit base address which finally forms 20 bit physical address of memory location. Calculate physical Address for the given CS= 3525H, IP= 2455H. cs 3 15/2 IP aE 4 Physical Address 3|7\/6|)A|5 e. 376A5H Example 1: DS=345AH and SI=13DCH. Calculate physical address. 45 A0+13DC = 3597CH8086 16-Bit Microprocessor Example 2: CS: IP =A4FB:4872 calculate Physical address: A4FBO +4872 =A9822 Example 3: If 2135H and IP = 3478H. Calculate Physical Address. Formation of a physical addres CS= 2135H, IP=3478H. CS :21350H O added by BIU +IP: 3478H 247C8H This is the Physical Address Example 4: Assume DS= 2632H, $1=4567H. Calculate Physical Address. DS : 26320H 0 added by BIU(or Hardwired 0) + SI: 4567H 2A887H. Example 5: Calculate the physical address for the given CS=3420H, IP=689AH. CS=3420H IP=689A H Zero is inserted 34200 +6.89A 3A ADA, Calculate the physical address for given: () DS = 73A2H SI =3216H. Gi) 370H IP = 561EH Answer:(i) DS = 73A2H SI =3216H DS 73A20H O is appended by BIU (or Hardwired zero) SI+3216H 76C36H (ii) CS = 7370H IP = 561EH CS 737001 Ois appended by BIU (or Hardwired zero) IP +561EH 78DIEH 8086 16-Bit Microprocessor