Computer architecture notes

FOR 1ST UNIT BASIC STRUCTURE AND FUNCTIONAL INTERCONNECTION AND INSTRUCTION CYCLE

1. Basic Structure of a Digital Computer

A digital computer is made up of five main units:

1. Input Unit:

• Takes data from the user.

• Examples: Keyboard, mouse, scanner.

2. Memory Unit:

• Stores data and instructions.

• Two types:

o Primary Memory:

▪ RAM (temporary)

▪ ROM (permanent)

o Secondary Memory:

▪ Hard disk, SSD (permanent)

3. Arithmetic and Logic Unit (ALU):

• Performs all calculations and logical operations.

• Examples: Addition, subtraction, comparisons.

4. Control Unit (CU):

 • Directs the operation of the processor.

• Tells other parts what to do and when to do it.

5. Output Unit:

• Shows the result to the user.

• Examples: Monitor, printer, speaker.

2. Functional Interconnection

These parts are connected and work together like this:

• Input Unit sends data to Memory.

• Control Unit fetches instructions from Memory.

• ALU processes the data as per the instruction.

• Result is sent back to Memory or to the Output Unit.

System Buses are used to carry data and signals between units:

• Data Bus: Carries data.

• Address Bus: Carries memory addresses.

• Control Bus: Carries control signals.

3. Instruction Cycle

The CPU follows a cycle to execute instructions:

1. Fetch:

• Get the instruction from memory.

2. Decode:

• Understand what the instruction means.

3. Execute:
 • Perform the operation (like add, move, etc.).

4. Store (optional):

• Save the result back in memory if needed.

This cycle repeats again and again for every instruction.

Von Neumann Architecture (VNA)

Definition:

The Von Neumann Architecture is a computer design model that uses a single memory for storing both instructions
(program) and data.

Main Components:

1. Central Processing Unit (CPU):

o ALU (Arithmetic Logic Unit): Performs arithmetic and logical operations.

o Control Unit (CU): Directs the flow of data and instructions.

2. Memory (RAM): Stores data and instructions.

3. Input Devices: Provide data to the computer (e.g., keyboard, mouse).

4. Output Devices: Show results (e.g., monitor, printer).

5. System Bus: Transfers data between CPU, memory, and I/O.

Key Features:

• Program and data share the same memory.

• Instructions are executed sequentially.

• Simpler design compared to Harvard architecture.

Hierarchical Structure of Functional Units

Definition:
It refers to the layered organization of different components (functional units) in a computer system based on their
role and abstraction level.

Hierarchy Levels:

1. Level 1 – Digital Logic:

o Logic gates, flip-flops, registers.

o Basic building blocks of hardware.

2. Level 2 – Microarchitecture:

o ALU, Control Unit, Registers.

o Describes how a CPU executes instructions internally.

3. Level 3 – Instruction Set Architecture (ISA):

o Set of machine-level instructions (e.g., MOV, ADD).

o Interface between hardware and software.

4. Level 4 – Operating System Level:

o Manages hardware resources.

o Includes memory management, process control.

5. Level 5 – High-Level Language (HLL):

o Programming languages (C, Python).

o Translated into machine code using compilers.

6. Level 6 – Application Level:

o User applications like MS Word, browsers.

Interconnections:

Data Bus:

Transfers data between CPU, memory, and I/O.

Address Bus:

Carries memory addresses from CPU to other components.

Control Bus:
Carries control signals (read/write/interrupts).

Would you like a diagram to visualize the architecture and hierarchy?

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also System bus and its various implementations

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Great! Here's a simple and clear explanation of the System Bus and its various implementations:

System Bus in Computer Architecture

Definition:

A System Bus is a communication pathway used to transfer data between different components of a computer, like
the CPU, memory, and input/output (I/O) devices.

It acts like the “highway” for information flow inside a computer.

Types of System Bus:

The system bus is usually divided into three main types:

1. Data Bus

o Transfers actual data between CPU, memory, and I/O.

o Bidirectional (CPU can send/receive).

o Width (e.g., 8, 16, 32, 64 bits) determines how much data is transferred at once.

2. Address Bus

o Carries memory addresses from CPU to memory and I/O.

o Unidirectional (CPU sends address).

o Size determines the maximum addressable memory (e.g., 32-bit = 2³² locations).

3. Control Bus

o Carries control signals (read/write, clock, interrupt, etc.).

o Coordinates operations between CPU and other devices.

 Various Bus Implementations:

1. Single Bus System:

• All components share one bus.

• Simple and cheap, but slow due to traffic congestion.

2. Multiple Bus System:

• Uses separate buses (e.g., one for memory, one for I/O).

• Faster as it reduces congestion.

• More complex and expensive.

3. Dedicated Buses:

• Each component has a dedicated connection.

• High performance, but very costly and complex.

4. Multiplexed Bus:

• Same bus lines used for data and addresses (at different times).

• Saves space and pins, but slows down performance.

Summary Table:

Bus Type Direction Purpose

Data Bus Bidirectional Transfers data

Address Bus Unidirectional Sends memory/I/O addresses

Control Bus Mixed Carries control and timing signals

CPU Structure – Made Easy

The CPU is the brain of the computer. It processes all instructions, performs calculations, and manages data flow.
 Main Components of the CPU:

1. Arithmetic Logic Unit (ALU)

• Performs all calculations and logic operations.

• Examples:

o Addition, Subtraction (arithmetic)

o AND, OR, NOT (logic)

• Like a calculator inside your CPU.

2. Control Unit (CU)

• Manages and controls all activities of the CPU.

• Tells other parts what to do.

• Fetches instructions from memory and tells ALU or registers to act.

3. Registers

• Very small, very fast memory inside the CPU.

• Temporarily stores data, addresses, and instructions.

• Types:

o Accumulator (ACC) – holds intermediate results from ALU.

o Program Counter (PC) – keeps track of the instruction being executed.

o Instruction Register (IR) – holds the current instruction.

o Memory Address Register (MAR) – holds the address to access in RAM.

o Memory Data Register (MDR) – holds data fetched from or to be written to RAM.

4. Cache Memory

• Tiny but super-fast memory closer to the CPU than RAM.

 • Stores frequently used data to speed up access.

• Levels:

o L1 (fastest, smallest)

o L2 (slower, bigger)

o L3 (even slower, shared among cores)

5. System Bus Interface

• Connects CPU to memory and I/O via buses:

o Data Bus

o Address Bus

o Control Bus

CPU Cycle (Fetch–Decode–Execute):

1. Fetch – Get the instruction from memory.

2. Decode – Interpret the instruction.

3. Execute – Perform the instruction (via ALU or CU).

CPU in a Nutshell:

Part Function

ALU Performs math and logic

Control Unit Directs operations and fetches instructions

Registers Temporarily store important values

Cache Speeds up data access

System Bus Connects CPU with other components

 Key CPU Registers and Their Functions

Register Abbreviation Function

Holds the address of the next instruction to fetch from

Program Counter PC
memory.

Instruction Register IR Stores the instruction currently being executed.

Holds the memory address of the data or instruction to

Memory Address Register MAR
be accessed.

Memory Buffer Register (or Memory Data Temporarily holds data read from or written to
MBR / MDR
Register) memory.

How They Work Together in Instruction Cycle (Fetch–Decode–Execute):

1. Fetch Phase:

o PC holds the address of the next instruction.

o This address is loaded into the MAR.

o Memory sends the instruction at that address to the MBR/MDR.

o Instruction is then moved to the IR.

o PC is incremented for the next instruction.

2. Decode Phase:

o IR sends the instruction to the Control Unit for decoding.

3. Execute Phase:

o CPU carries out the instruction (using ALU, memory, or I/O depending on what’s required).

Summary Points:

• PC: Keeps track of where the CPU is in the instruction sequence.

• MAR: Tells the CPU where to go in memory.

• MBR/MDR: Temporarily holds what was found at that memory location.

 • IR: Holds what to do (the instruction itself).

Execution of a Complete (Basic) Instruction

Three Phases of Instruction Execution (Fetch–Decode–Execute Cycle):

1. Fetch:

o CPU uses the Program Counter (PC) to fetch the next instruction from memory.

o Address in PC → placed in Memory Address Register (MAR).

o Data (instruction) → fetched into Memory Buffer Register (MBR/MDR).

o Then loaded into Instruction Register (IR).

2. Decode:

o Control Unit (CU) decodes the instruction in IR.

o Identifies operation type (e.g., ADD, LOAD) and operands.

3. Execute:

o Operation is performed by ALU, memory, or I/O as per instruction.

o Results may be stored in Accumulator or registers.

This cycle repeats for each instruction.

Instruction Set Architecture (ISA)

Definition:

ISA is the interface between hardware and software. It defines:

• The set of machine language instructions a CPU can execute.

• The data types, registers, addressing modes, and control instructions.

Components of ISA:

• Instruction format (opcode + operands)

• Instruction types:

o Data transfer (e.g., MOV, LOAD)

 o Arithmetic/logic (e.g., ADD, SUB)

o Control flow (e.g., JMP, CALL)

• Addressing modes (e.g., immediate, direct, indirect)

• Registers available

Think of ISA as the vocabulary a CPU understands.

Instruction Cycle

The Instruction Cycle is the complete process by which the CPU fetches, decodes, and executes an instruction.

Phases:

1. Fetch – Get instruction from memory.

2. Decode – Understand what the instruction means.

3. Execute – Perform the action (via ALU, CU, or memory).

4. (Optional) Memory Access / Write-back – If result is stored in memory or register.

CPU repeats this cycle continuously to run programs.

CISC vs RISC

Feature CISC (Complex Instruction Set Computer) RISC (Reduced Instruction Set Computer)

Instruction Size Large and variable length Small and fixed size

Instruction Count Fewer instructions needed per task More instructions, but simpler

Complexity Complex hardware (microcoded) Simpler hardware

Speed Slower (due to instruction decoding time) Faster (one instruction per clock cycle possible)

Memory Use Less program memory required More program memory due to more instructions

Example Architectures Intel x86, VAX ARM, MIPS, RISC-V

Summary:

• CISC: Fewer, more powerful instructions. Slower, complex hardware.

• RISC: Many simple instructions. Faster, efficient for modern embedded systems.
 Quick Summary Table:

Topic Key Idea

Instruction Execution Fetch → Decode → Execute

ISA Hardware-level instruction set interface

Instruction Cycle CPU’s recurring process of instruction handling

CISC vs RISC Trade-off between complex/simple instructions and speed/hardware simplicity