Computer Organization and Architecture

UNIT – II (12 Lectures)

BASIC COMPUTER ORGANIZATION AND DESIGN: Instruction codes, computer
registers, computer instructions, instruction cycle, timing and control,
memory-reference instructions, input-output and interrupt.
Book: M. Moris Mano (2006), Computer System Architecture, 3rd edition, Pearson/PHI,
India: Unit-5 Pages: 123-157

Central processing unit: stack organization, instruction formats, addressing modes,

data transfer and manipulation, program control, reduced instruction set computer
(RISC).
Book: M. Moris Mano (2006), Computer System Architecture, 3rd edition, Pearson/PHI,
India: Unit-8 Pages: 241-297

Instruction Codes
Computer instructions are the basic components of a machine language program. They
are also known as macro operations, since each one is comprised of sequences of
micro operations. Each instruction initiates a sequence of micro operations that fetch
operands from registers or memory, possibly perform arithmetic, logic, or shift
operations, and store results in registers or memory.

Instructions are encoded as binary instruction codes. Each instruction code

contains of a operation code, or opcode, which designates the overall purpose of the
instruction (e.g. add, subtract, move, input, etc.). The number of bits allocated for the
opcode determined how many different instructions the architecture supports.

In addition to the opcode, many instructions also contain one or more operands,
which indicate where in registers or memory the data required for the operation is
located. For example, and add instruction requires two operands, and a not instruction
requires one.
15 12 11 65 0
+-----------------------------------+

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| Opcode | Operand | Operand |

+-----------------------------------+

The opcode and operands are most often encoded as unsigned binary numbers in
order to minimize the number of bits used to store them. For example, a 4-bit opcode
encoded as a binary number could represent up to 16 different operations.

The control unit is responsible for decoding the opcode and operand bits in the
instruction register, and then generating the control signals necessary to drive all
other hardware in the CPU to perform the sequence of microoperations that comprise
the instruction.

Basic Computer Instruction Format:

The Basic Computer has a 16-bit instruction code similar to the examples described
above. It supports direct and indirect addressing modes.
How many bits are required to specify the addressing mode?
15 14 12 11 0
+------------------+
| I | OP | ADDRESS |
+------------------+
I = 0: direct
I = 1: indirect

Computer Instructions
All Basic Computer instruction codes are 16 bits wide. There are 3 instruction code
formats:
Memory-reference instructions take a single memory address as an operand, and
have the format:
15 14 12 11 0
+-------------------+
| I | OP | Address |
+-------------------+

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If I = 0, the instruction uses direct addressing. If I = 1, addressing in indirect.

How many memory-reference instructions can exist?

Register-reference instructions operate solely on the AC register, and have the

following format:
15 14 12 11 0
+------------------+
| 0 | 111 | OP |
+------------------+

How many register-reference instructions can exist? How many memory-

reference instructions can coexist with register-reference instructions?

Input/output instructions have the following format:

15 14 12 11 0
+------------------+
| 1 | 111 | OP |
+------------------+

How many I/O instructions can exist? How many memory-reference

instructions can coexist with register-reference and I/O instructions?

Timing and Control

All sequential circuits in the Basic Computer CPU are driven by a master clock, with
the exception of the INPR register. At each clock pulse, the control unit sends control
signals to control inputs of the bus, the registers, and the ALU.

Control unit design and implementation can be done by two general methods:
 A hardwired control unit is designed from scratch using traditional digital logic
design techniques to produce a minimal, optimized circuit. In other words, the
control unit is like an ASIC (application-specific integrated circuit).

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 A micro-programmed control unit is built from some sort of ROM. The desired
control signals are simply stored in the ROM, and retrieved in sequence to drive
the micro operations needed by a particular instruction.

Micro programmed control:

Micro programmed control is a control mechanism to generate control signals by
using a memory called control storage (CS), which contains the control
signals. Although micro programmed control seems to be advantageous to CISC
machines, since CISC requires systematic development of sophisticated control
signals, there is no intrinsic difference between these 2 control mechanisms.

Hard-wired control:
Hardwired control is a control mechanism to generate control signals by using
appropriate finite state machine (FSM). The pair of "microinstruction-register" and
"control storage address register" can be regarded as a "state register" for the
hardwired control. Note that the control storage can be regarded as a kind of
combinational logic circuit. We can assign any 0, 1 values to each output
corresponding to each address, which can be regarded as the input for a
combinational logic circuit. This is a truth table.

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Instruction Cycle
In this chapter, we examine the sequences of micro operations that the Basic
Computer goes through for each instruction. Here, you should begin to understand
how the required control signals for each state of the CPU are determined, and how
they are generated by the control unit.
The CPU performs a sequence of micro operations for each instruction. The sequence
for each instruction of the Basic Computer can be refined into 4 abstract phases:
1. Fetch instruction
2. Decode
3. Fetch operand
4. Execute
Program execution can be represented as a top-down design:
1. Program execution
a. Instruction 1
i. Fetch instruction
ii. Decode
iii. Fetch operand
iv. Execute
b. Instruction 2
i. Fetch instruction
ii. Decode
iii. Fetch operand
iv. Execute
c. Instruction 3 ...
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Program execution begins with:

PC ← address of first instruction, SC ← 0
After this, the SC is incremented at each clock cycle until an instruction is completed,
and then it is cleared to begin the next instruction. This process repeats until a HLT
instruction is executed, or until the power is shut off.

Instruction Fetch and Decode

The instruction fetch and decode phases are the same for all instructions, so the
control functions and micro operations will be independent of the instruction code.
Everything that happens in this phase is driven entirely by timing variables T0, T1 and
T2. Hence, all control inputs in the CPU during fetch and decode are functions of these
three variables alone.
T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
T2: D0-7 ← decoded IR(12-14), AR ← IR(0-11), I ← IR(15)
For every timing cycle, we assume SC ← SC + 1 unless it is stated that SC ← 0.
The operation D0-7 ← decoded IR(12-14) is not a register transfer like most of our
micro operations, but is actually an inevitable consequence of loading a value into the
IR register. Since the IR outputs 12-14 are directly connected to a decoder, the outputs
of that decoder will change as soon as the new values of IR(12-14) propagate through
the decoder.

Note that incrementing the PC at time T 1 assumes that the next instruction is at
the next address. This may not be the case if the current instruction is a branch
instruction. However, performing the increment here will save time if the next
instruction immediately follows, and will do no harm if it doesn't. The incremented PC
value is simply overwritten by branch instructions.

In hardware development, unlike serial software development, it is often

advantageous to perform work that may not be necessary. Since we can perform
multiple micro operations at the same time, we might was well do everything
that might be useful at the earliest possible time. Likewise, loading AR with the

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address field from IR at T2 is only useful if the instruction is a memory-reference

instruction. We won't know this until T 3, but there is no reason to wait since there is
no harm in loading AR immediately.

Input-Output and Interrupt

Hardware Summary
The Basic Computer I/O consists of a simple terminal with a keyboard and a
printer/monitor.
The keyboard is connected serially (1 data wire) to the INPR register. INPR is a shift
register capable of shifting in external data from the keyboard one bit at a time. INPR
outputs are connected in parallel to the ALU.
Shift enable
|
v
+-----------+ 1 +-------+
| Keyboard |---/-->| INPR <|--- serial I/O clock
+-----------+ +-------+
|
/8
| | |
v v v
+---------------+
| ALU |
+---------------+
|
/ 16
|
v
+---------------+
| AC <|--- CPU master clock
+---------------+

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How many CPU clock cycles are needed to transfer a character from the keyboard to
the INPR register? (tricky)
Are the clock pulses provided by the CPU master clock?
RS232, USB, Firewire are serial interfaces with their own clock independent of the
CPU. ( USB speed is independent of processor speed. )
 RS232: 115,200 kbps (some faster)
 USB: 11 mbps
 USB2: 480 mbps
 FW400: 400 mbps
 FW800: 800 mbps
 USB3: 4.8 gbps
OUTR inputs are connected to the bus in parallel, and the output is connected serially
to the terminal. OUTR is another shift register, and the printer/monitor receives an
end-bit during each clock pulse.

I/O Operations
Since input and output devices are not under the full control of the CPU (I/O events
are asynchronous), the CPU must somehow be told when an input device has new
input ready to send, and an output device is ready to receive more output. The FGI flip-
flop is set to 1 after a new character is shifted into INPR. This is done by the I/O
interface, not by the control unit. This is an example of an asynchronous input event
(not synchronized with or controlled by the CPU).

The FGI flip-flop must be cleared after transferring the INPR to AC. This must be
done as a micro operation controlled by the CU, so we must include it in the CU design.
The FGO flip-flop is set to 1 by the I/O interface after the terminal has finished
displaying the last character sent. It must be cleared by the CPU after transferring a
character into OUTR. Since the keyboard controller only sets FGI and the CPU only
clears it, a JK flip-flop is convenient:
+-------+
Keyboard controller --->| J Q |----->
| | |

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+--------\-----\ | |
) or >----->|> FGI |
+--------/-----/ | |
| | |
CPU-------------------->| K |
+-------
How do we control the CK input on the FGI flip-flop? (Assume leading-edge
triggering.)
There are two common methods for detecting when I/O devices are ready,
namely software polling and interrupts. These two methods are discussed in the
following sections.
Stack Organization
Stack is the storage method of the items in which the last item included is the first one
to be removed/taken from the stack. Generally a stack in the computer is
a memory unit with an address register and the register holding the address of the
stack is known as the Stack Pointer (SP). A stack performs Insertion and Deletion
operation, were the operation of inserting an item is known as Push and operation of
deleting an item is known as Pop. Both Push and Pop operation results in
incrementing and decrementing the stack pointer respectively.

Register Stack
Register or memory words can be organized to form a stack. The stack pointer is
a register that holds the memory address of the top of the stack. When an item need
to be deleted from the stack, item on the top of the stack is deleted and the stack
pointer is decremented. Similarly, when an item needs to be added, the stack pointer is
incremented and writing the word at the position indicated by the stack pointer. There
are two 1 bit register; FULL and EMTY that are used for describing the
stack overflow and underflow conditions. Following micro-operations are performed
during inserting and deleting an item in/from the stack.

Insert:
SP <- SP + 1 // Increment the stack pointer to point the next higher address//

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M[SP] <- DR // Write the item on the top of the stack//

If (SP = 0) then (Full <- 1) // Check overflow condition //
EMTY <- 0 // Mark that the stack is not empty //

Delete:
DR <- M[SP] //Read an item from the top of the stack//
SP <- SP 1 //Decrement the stack pointer //
If (SP = 0) then (EMTY <- 1) //Check underflow condition //
FULL <- 0 //Mark that the stack is not full //

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Register Stack:-
A stack can be placed in a portion of a large memory as it can be organized as a
collection of a finite number of memory words as register.

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In a 64- word stack, the stack pointer contains 6 bits because 26 = 64.
The one bit register FULL is set to 1 when the stack is full, and the one-bit register
EMTY is set to 1 when the stack is empty. DR is the data register that holes the binary
data to be written into on read out of the stack. Initially, SP is decide to O, EMTY is set
to 1, FULL = 0, so that SP points to the word at address O and the stack is masked
empty and not full.
PUSH SP ® SP + 1 increment stack pointer
M [SP] ® DR unit item on top of the Stack
It (SP = 0) then (FULL ® 1) check it stack is full
EMTY ® 0 mask the stack not empty.
POP DR ® [SP] read item trans the top of stack
SP ® SP –1 decrement SP
It (SP = 0) then (EMTY ® 1) check it stack is empty
FULL ® 0 mark the stack not full.

A stack can be placed in a portion of a large memory or it can be organized as

a collection of a finite number of memory words or registers. Figure X shows the
organization of a 64-word register stack. The stack pointer register SP contains a
binary number whose value is equal to the address of the word that is currently on
top of the stack.

Three items are placed in the stack: A, B, and C in the order. item C is
on the top of the stack so that the content of sp is now 3. To remove the top item, the
stack is popped by reading the memory word at address 3 and decrementing the
content of SP. Item B is now on top of the stack since SP holds address 2. To insert a
new item, the stack is pushed by incrementing SP and writing a word in the next
higher location in the stack. Note that item C has read out but not physically removed.
This does not matter because when the stack is pushed, a new item is written in its
place.

In a 64-word stack, the stack pointer contains 6 bits because 26=64. since SP
has only six bits, it cannot exceed a number greater than 63(111111 in binary). When

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63 is incremented by 1, the result is 0 since 111111 + 1 =1000000 in binary, but SP

can accommodate only the six least significant bits. Similarly, when 000000 is
decremented by 1, the result is 111111. The one bit register Full is set to 1 when the
stack is full, and the one-bit register EMTY is set to 1 when the stack is empty of
items. DR is the data register that holds the binary data to be written in to or read out
of the stack.

Initially, SP is cleared to 0, Emty is set to 1, and Full is cleared to 0, so that SP

points to the word at address o and the stack is marked empty and not full. if the stack
is not full , a new item is inserted with a push operation. the push operation is
implemented with the following sequence of micro-operation.
SP ←SP + 1 (Increment stack pointer)
M(SP) ← DR (Write item on top of the stack)
if (sp=0) then (Full ← 1) (Check if stack is full)
Emty ← 0 ( Marked the stack not empty)

The stack pointer is incremented so that it points to the address of the next-higher
word. A memory write operation inserts the word from DR into the top of the stack.
Note that SP holds the address of the top of the stack and that M(SP) denotes the
memory word specified by the address presently available in SP, the first item stored
in the stack is at address 1. The last item is stored at address 0, if SP reaches 0, the
stack is full of item, so FULLL is set to 1.

This condition is reached if the top item prior to the last push was in location 63
and after increment SP, the last item stored in location 0. Once an item is stored in
location 0, there are no more empty register in the stack. If an item is written in the
stack, obviously the stack cannot be empty, so EMTY is cleared to 0.

DR← M[SP] Read item from the top of stack

SP ← SP-1 Decrement stack Pointer
if( SP=0) then (Emty ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full

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The top item is read from the stack into DR. The stack pointer is then decremented. if
its value reaches zero, the stack is empty, so Empty is set to 1. This condition is
reached if the item read was in location 1. Once this item is read out, SP is
decremented and reaches the value 0, which is the initial value of SP. Note that if a
pop operation reads the item from location 0 and then SP is decremented, SP changes
to 111111, which is equal to decimal 63. In this configuration, the word in address 0
receives the last item in the stack. Note also that an erroneous operation will result if
the stack is pushed when FULL=1 or popped when EMTY =1.
Memory Stack :
A stack can exist as a stand-alone unit as in figure 4 or can be implemented in
a random access memory attached to CPU. The implementation of a stack in the CPU
is done by assigning a portion of memory to a stack operation and using a processor
register as a stack pointer. Figure shows a portion of computer memory partitioned in
to three segment program, data and stack. The program counter PC points at the
address of the next instruction in the program. The address register AR points at an
array of data. The stack pointer SP points at the top of the stack. The three register
are connected to a common address bus, and either one can provide an address for
memory. PC is used during the fetch phase to read an instruction. AR is used during
the execute phase to read an operand. SP is used to push or POP items into or from
the stack.

As show in figure :4 the initial value of SP is 4001 and the stack grows with
decreasing addresses. Thus the first item stored in the stack is at address 4000, the
second item is stored at address 3999, and the last address hat can be used for the
stack is 3000. No previous are available for stack limit checks.
We assume that the items in the stack communicate with a data register DR. A new
item is inserted with the push operation as follows.

SP← SP-1
M[SP] ← DR

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The stack pointer is decremented so that it points at the address of the next word. A
Memory write operation insertion the word from DR into the top of the stack. A new
item is deleted with a pop operation as follows.
DR← M[SP]
SP←SP + 1

The top item is read from the stack in to DR. The stack pointer is then incremented to
point at the next item in the stack. Most computers do not provide hardware to check
for stack overflow (FULL) or underflow (Empty). The stack limit can be checked by
using two processor register: one to hold upper limit and other hold the lower limit.
After the pop or push operation SP is compared with lower or upper limit register.

REVERSE POLISH NOTATION

For example: A x B + C x D is an arithmetical expression written in infix notation, here
x (denotes multiplication). In this expression A and B are two operands and x is an
operator, similarly C and D are two operands and x is an operator. In this expression +

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is another operator which is written between (A x B) and (C x D). Because of the

precedence of the operator multiplication is done first. The order of precedence is as:
1. Exponentiation have precedence one.
2. Multiplication and Division has precedence two.
3. Addition and subtraction has precedence three.

Reverse polish notation is also known as postfix notation is defined as: In postfix
notation operator is written after the operands. Examples of postfix notation are AB+
and CD-. Here A and B are two operands and the operator is written after these two
operands. The conversion from infix expression into postfix expression is shown
below.
 Convert the infix notation A x B + C x D + E x F into postfix notation?
SOLUTION
AxB+CxD+ExF
= [ABx] + [CDx] + [EFx]
= [ABxCDx] + [EFx]
= [ABxCDxEFx]
= ABxCDxEFx
So the postfix notation is ABxCDxEFx.
 Convert the infix notation {A – B + C x (D x E – F)} / G + H x K into postfix
notation?
{A – B + C x (D x E – F)} / G + H x K
= {A – B + C x ([DEx] – F)} / G + [HKx]
= {A – B + C x [DExF-]} / [GHKx+]
= {A – B + [CDExF-x]} / [GHKx+]
= {[AB-] + [CDExF-x]} / [GHKx+]
= [AB-CDExF-x+] / [GHKx+]
= [AB-CDExF-x+GHKx+/]
= AB-CDExF-x+GHKx+/
So the postfix notation is AB-CDExF-x+GHKx+/.
Now let’s how to evaluate a postfix expression, the algorithm for the evaluation of
postfix notation is shown below:

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ALGORITHM:
(Evaluation of Postfix notation) This algorithm finds the result of a postfix expression.
Step1: Insert a symbol (say #) at the right end of the postfix expression.
Step2: Scan the expression from left to right and follow the Step3 and Step4 for each of
the symbol encountered.
Step3: if an element is encountered insert into stack.
Step4: if an operator (say &) is encountered pop the top element A (say) and next to
top element B (say) perform the following operation x = B&A. Push x into the top of
the stack.
Step5: if the symbol # is encountered then stop scanning.
 Evaluate the post fix expression 50 4 3 x 2 – + 7 8 x 4 / -?

SOLUTION
Put symbol # at the right end of the expression: 50 4 3 x 2 – + 7 8 x 4 / – #.

Postfix expression Symbol Stack

scanned
50 4 3 x 2 – + 7 8 x 4 / – # _ _
43x2–+78x4/–# 50 50
3x2–+78x4/–# 4 50, 4
x2–+78x4/–# 3 50, 4, 3
2–+78x4/–# x 50, 12
–+78x4/–# 2 50, 12, 2
+78x4/–# – 50, 10
78x4/–# + 60
8x4/–# 7 60, 7
x4/–# 8 60, 7, 8
4/–# x 60, 56
/–# 4 60, 56, 4
–# / 60, 14

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# – 46
_ # Result = 46

INSTRUCTION FORMATS
The most common fields found in instruction format are:-
(1) An operation code field that specified the operation to be performed
(2) An address field that designates a memory address or a processor registers.
(3) A mode field that specifies the way the operand or the effective address is
determined.
Computers may have instructions of several different lengths containing varying
number of addresses. The number of address field in the instruction format of a
computer depends on the internal organization of its registers. Most computers fall
into one of three types of CPU organization.
(1) Single Accumulator organization ADD X AC ® AC + M [×]
(2) General Register Organization ADD R1, R2, R3 R ® R2 + R3
(3) Stack Organization PUSH X

Three address Instruction

Computer with three addresses instruction format can use each address field to
specify either processor register are memory operand.
ADD R1, A, B A1 ® M [A] + M [B]
ADD R2, C, D R2 ® M [C] + M [B] X = (A + B) * (C + A)
MUL X, R1, R2 M [X] R1 * R2
The advantage of the three address formats is that it results in short program when
evaluating arithmetic expression. The disadvantage is that the binary-coded
instructions require too many bits to specify three addresses.

Two Address Instruction

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Most common in commercial computers. Each address field can specify either a
processes register on a memory word.
MOV R1, A R1 ® M [A]
ADD R1, B R1 ® R1 + M [B]
MOV R2, C R2 ® M [C] X = (A + B) * ( C + D)
ADD R2, D R2 ® R2 + M [D]
MUL R1, R2 R1 ® R1 * R2
MOV X1 R1 M [X] ® R1

One Address instruction

It used an implied accumulator (AC) register for all data manipulation. For
multiplication/division, there is a need for a second register.
LOAD A AC ® M [A]
ADD B AC ® AC + M [B]
STORE T M [T] ® AC X = (A +B) × (C + A)
All operations are done between the AC register and a memory operand. It’s the
address of a temporary memory location required for storing the intermediate result.
LOAD C AC ® M (C)
ADD D AC ® AC + M (D)
ML T AC ® AC + M (T)
STORE X M [×]® AC

Zero – Address Instruction

A stack organized computer does not use an address field for the instruction ADD and
MUL. The PUSH & POP instruction, however, need an address field to specify the
operand that communicates with the stack (TOS ® top of the stack)
PUSH A TOS ® A
PUSH B TOS ® B
ADD TOS ® (A + B)
PUSH C TOS ® C
PUSH D TOS ® D
ADD TOS ® (C + D)

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MUL TOS ® (C + D) * (A + B)
POP X M [X] TOS

Addressing Modes
The operation field of an instruction specifies the operation to be performed. This
operation must be executed on some data stored in computer register as memory
words. The way the operands are chosen during program execution is dependent on
the addressing mode of the instruction. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction between the operand is
activity referenced. Computer use addressing mode technique for the purpose of
accommodating one or both of the following provisions.
(1) To give programming versatility to the uses by providing such facilities as
pointer to memory, counters for top control, indexing of data, and program relocation.
(2) To reduce the number of bits in the addressing fields of the instruction.

Addressing Modes: The most common addressing techniques are

• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement
• Stack

All computer architectures provide more than one of these addressing modes.
The question arises as to how the control unit can determine which addressing mode
is being used in a particular instruction. Several approaches are used. Often, different
opcodes will use different addressing modes. Also, one or more bits in the instruction

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format can be used as a mode field. The value of the mode field determines which
addressing mode is to be used.

What is the interpretation of effective address. In a system without virtual

memory, the effective address will be either a main memory address or a register. In a
virtual memory system, the effective address is a virtual address or a register. The
actual mapping to a physical address is a function of the paging mechanism and is
invisible to the programmer.
Opcode Mode Address
Immediate Addressing:
The simplest form of addressing is immediate addressing, in which the
operand is actually present in the instruction:
OPERAND = A
This mode can be used to define and use constants or set initial values of
variables. The advantage of immediate addressing is that no memory reference other
than the instruction fetch is required to obtain the operand. The disadvantage is that
the size of the number is restricted to the size of the address field, which, in most
instruction sets, is small compared with the world length.

Direct Addressing:
A very simple form of addressing is direct addressing, in which the address field
contains the effective address of the operand:

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EA = A
It requires only one memory reference and no special calculation.

Indirect Addressing:
With direct addressing, the length of the address field is usually less than the
word length, thus limiting the address range. One solution is to have the address field
refer to the address of a word in memory, which in turn contains a full-length address
of the operand. This is known as indirect addressing:
EA = (A)

Register Addressing:
Register addressing is similar to direct addressing. The only difference is that
the address field refers to a register rather than a main memory address:
EA = R

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The advantages of register addressing are that only a small address field is
needed in the instruction and no memory reference is required. The disadvantage of
register addressing is that the address space is very limited.

The exact register location of the operand in case of Register Addressing

Mode is shown in the Figure 34.4. Here, 'R' indicates a register where the operand is
present.
Register Indirect Addressing:
Register indirect addressing is similar to indirect addressing, except that the
address field refers to a register instead of a memory location. It requires only one
memory reference and no special calculation.
EA = (R)

Register indirect addressing uses one less memory reference than indirect
addressing. Because, the first information is available in a register which is nothing
but a memory address. From that memory location, we use to get the data or
information. In general, register access is much more faster than the memory access.

Displacement Addressing:
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A very powerful mode of addressing combines the capabilities of direct

addressing and register indirect addressing, which is broadly categorized as
displacement addressing:
EA = A + (R)
Displacement addressing requires that the instruction have two address fields,
at least one of which is explicit. The value contained in one address field (value = A)
is used directly. The other address field, or an implicit reference based on opcode,
refers to a register whose contents are added to A to produce the effective address.

The general format of Displacement Addressing is shown in the Figure 4.6.

Three of the most common use of displacement addressing are:
• Relative addressing
• Base-register addressing
• Indexing

Relative Addressing:
For relative addressing, the implicitly referenced register is the program
counter (PC). That is, the current instruction address is added to the address field to
produce the EA. Thus, the effective address is a displacement relative to the address
of the instruction.

Base-Register Addressing:

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The reference register contains a memory address, and the address field
contains a displacement from that address. The register reference may be explicit or
implicit. In some implementation, a single segment/base register is employed and is
used implicitly. In others, the programmer may choose a register to hold the base
address of a segment, and the instruction must reference it explicitly.

Indexing:
The address field references a main memory address, and the reference
register contains a positive displacement from that address. In this case also the
register reference is sometimes explicit and sometimes implicit.
Generally index register are used for iterative tasks, it is typical that there is a
need to increment or decrement the index register after each reference to it. Because
this is such a common operation, some system will automatically do this as part of the
same instruction cycle.
This is known as auto-indexing. We may get two types of auto-indexing: -one is
auto-incrementing and the other one is -auto-decrementing. If certain registers are
devoted exclusively to indexing, then auto-indexing can be invoked implicitly and
automatically. If general purpose register are used, the auto index operation may need
to be signaled by a bit in the instruction.

Auto-indexing using increment can be depicted as follows:

EA = A + (R)
R = (R) + 1
Auto-indexing using decrement can be depicted as follows:
EA = A + (R)
R = (R) - 1

In some machines, both indirect addressing and indexing are provided, and it is
possible to employ both in the same instruction. There are two possibilities: The
indexing is performed either before or after the indirection. If indexing is performed
after the indirection, it is termed post indexing
EA = (A) + (R)

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First, the contents of the address field are used to access a memory location
containing an address. This address is then indexed by the register value.
With pre indexing, the indexing is performed before the indirection:
EA = ( A + (R)
An address is calculated, the calculated address contains not the operand, but the
address of the operand.

Stack Addressing:
A stack is a linear array or list of locations. It is sometimes referred to as a
pushdown list or last-in-first-out queue. A stack is a reserved block of locations. Items
are appended to the top of the stack so that, at any given time, the block is partially
filled. Associated with the stack is a pointer whose value is the address of the top of
the stack. The stack pointer is maintained in a register. Thus, references to stack
locations in memory are in fact register indirect addresses.
The stack mode of addressing is a form of implied addressing. The machine
instructions need not include a memory reference but implicitly operate on the top of
the stack.
Value addition: A Quick View
Various Addressing Modes with Examples

The most common names for addressing modes (names may differ
among architectures)
Addressing Example
Meaning When used
modes Instruction
When a value is
Register Add R4,R3 R4 <- R4 + R3
in a register
Immediate Add R4, #3 R4 <- R4 + 3 For constants
Add R4, R4 <- R4 + Accessing local
Displacement
100(R1) Mem[100+R1] variables
Accessing using
Register a pointer or a
Add R4,(R1) R4 <- R4 + M[R1]
deffered computed
address
Useful in array
addressing:
Add R3, (R1 R3 <- R3 + R1 - base of
Indexed
+ R2) Mem[R1+R2] array
R2 - index
amount

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Useful in
Add R1,
Direct R1 <- R1 + Mem[1001] accessing static
(1001)
data
If R3 is the
Memory Add R1, R1 <- R1 + address of a
deferred @(R3) Mem[Mem[R3]] pointer p, then
mode yields *p
Useful for
stepping
through arrays
Auto- Add R1, R1 <- R1 +Mem[R2] in a loop.
increment (R2)+ R2 <- R2 + d R2 - start of
array
d - size of an
element
Same as
autoincrement.
Both can also
Auto- Add R1,- R2 <-R2-d
be used to
decrement (R2) R1 <- R1 + Mem[R2]
implement a
stack as push
and pop
Used to index
arrays. May be
applied to any
Add R1, R1<-
Scaled base
100(R2)[R3] R1+Mem[100+R2+R3*d]
addressing
mode in some
machines.

Notation:
<- - assignment
Mem - the name for memory:
Mem[R1] refers to contents of memory location whose address is given by the
contents of R1
Source: Self

Data Transfer & Manipulation

Computer provides an extensive set of instructions to give the user the flexibility to
carryout various computational task. Most computer instruction can be classified into
three categories.
(1) Data transfer instruction
(2) Data manipulation instruction
(3) Program control instruction
Data transfer instruction cause transferred data from one location to another without
changing the binary instruction content. Data manipulation instructions are those that
perform arithmetic logic, and shift operations. Program control instructions provide

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decision-making capabilities and change the path taken by the program when
executed in the computer.

(1) Data Transfer Instruction

Data transfer instruction move data from one place in the computer to another
without changing the data content. The most common transfers are between memory
and processes registers, between processes register & input or output, and between
processes register themselves
(Typical data transfer instruction)
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

(2) Data Manipulation Instruction

It performs operations on data and provides the computational capabilities for the
computer. The data manipulation instructions in a typical computer are usually
divided into three basic types.
(a) Arithmetic Instruction
(b) Logical bit manipulation Instruction
(c) Shift Instruction.
(a) Arithmetic Instruction
Name Mnemonic
Increment INC
Decrement DEC
Add Add

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Subtract Sub
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Basses SUBB
Negate (2’s Complement) NEG

(b) Logical & Bit Manipulation Instruction

Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-Or XOR
Clear Carry CLRC
Set Carry SETC
Complement Carry COMC
Enable Interrupt ET
Disable Interrupt OI
(c) Shift Instruction
Instructions to shift the content of an operand are quite useful and one often provided
in several variations. Shifts are operation in which the bits of a word are moved to the
left or right. The bit-shifted in at the and of the word determines the type of shift used.
Shift instruction may specify either logical shift, arithmetic shifts, or rotate type shifts.
Name Mnemonic
Logical Shift right SHR
Logical Shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR

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Rotate left ROL

Rotate right through carry RORC
Rotate left through carry ROLC

Introduction About Program Control:-

A program that enhances an operating system by creating an environment in which
you can run other programs. Control programs generally provide a graphical
interface and enable you to run several programs at once in different windows.
Control programs are also called operating environments.

The program control functions are used when a series of conditional or

unconditional jump and return instruction are required. These instructions allow the
program to execute only certain sections of the control logic if a fixed set of logic
conditions are met. The most common instructions for the program control available
in most controllers are described in this section.
Introduction About status bit register:-
A status register, flag register, or condition code register is a collection of
status flag bits for a processor. An example is the FLAGS register of the computer
architecture. The flags might be part of a larger register, such as a program status
word (PSW) register.

The status register is a hardware register which contains information about the
state of the processor. Individual bits are implicitly or explicitly read and/or written
by the machine code instructions executing on the processor. The status register in a
traditional processor design includes at least three central flags: Zero, Carry, and
Overflow, which are set or cleared automatically as effects of arithmetic and bit
manipulation operations. One or more of the flags may then be read by a subsequent
conditional jump instruction (including conditional calls, returns, etc. in some
machines) or by some arithmetic, shift/rotate or bitwise operation, typically using the
carry flag as input in addition to any explicitly given operands. There are also
processors where other classes of instructions may read or write the fundamental
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zero, carry or overflow flags, such as block-, string- or dedicated input/output

instructions, for instance.

Some CPU architectures, such as the MIPS and Alpha, do not use a dedicated flag
register. Others do not implicitly set and/or read flags. Such machines either do not
pass implicit status information between instructions at all, or do they pass it in a
explicitly selected general purpose register.
A status register may often have other fields as well, such as more specialized
flags, interrupt enable bits, and similar types of information. During an interrupt, the
status of the thread currently executing can be preserved (and later recalled) by
storing the current value of the status register along with the program counter and
other active registers into the machine stack or some other reserved area of memory.
Common flags:-
This is a list of the most common CPU status register flags, implemented in almost all
modern processors.

Flag Name Description

Indicates that the result of arithmetic or logical
Z Zero flag
operation (or, sometimes, a load) was zero.
Enables numbers larger than a single word to be
added/subtracted by carrying a binary digit from a less
significant word to the least significant bit of a more
C Carry flag
significant word as needed. It is also used to extend bit
shifts and rotates in a similar manner on many
processors (sometimes done via a dedicated X flag).
Indicates that the result of a mathematical operation is
negative. In some processors, the N and S flags are
Sign flag
distinct with different meanings and usage: One
S/N Negative
indicates whether the last result was negative whereas
flag
the other indicates whether a subtraction or addition
has taken place.

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Indicates that the signed result of an operation is too

Overflow
V/O/W large to fit in the register width using twos complement
flag
representation.

Introduction About Conditional branch instruction:-

Conditional branch instruction:-
Conditional branch instruction is the branch instruction bit and BR instruction is the
Program control instruction.
The conditional Branch Instructions are listed as Bellow:-

Mnemonics Branch Instruction Tested control

BZ Branch if Zero Z=1
BNZ Branch if not Zero Z=0
BC Branch if Carry C=1
BNC Branch if not Carry C=0
BP Branch if Plus S=0
BM Branch if Minus S=1
BV Branch if Overflow V=1
BNV Branch if not Overflow V=0

Unsigned Compare(A-B):-
Mnemonics Branch Instruction Tested control
BHI Branch if Higher A>B
BHE Branch if Higher or Equal A >= B
BLO Branch if Lower A<B
BLE Branch if Lower or Equal A <= B
BE Branch if Equal A=B
BNE Branch if not Equal A not = B

Signed Compare(A-B):
Mnemonics Branch Instruction Tested control

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BGT Branch if Greater Than A>B

BGE Branch if Greater Than or Equal A >= B
BLT Branch if Less Than A<B
BLE Branch if Less Than or Equal A <= B
BE Branch if Equal A=B
BNE Branch if not Equal A not = B

Introduction About program interrupt:-

When a Process is executed by the CPU and when a user Request for another Process
then this will create disturbance for the Running Process. This is also called as
the Interrupt.

Interrupts can be generated by User, Some Error Conditions and also by

Software’s and the hardware’s. But CPU will handle all the Interrupts very carefully
because when Interrupts are generated then the CPU must handle all the Interrupts
Very carefully means the CPU will also Provide Response to the Various Interrupts
those are generated. So that When an interrupt has Occurred then the CPU will handle
by using the Fetch, decode and Execute Operations.

Interrupts allow the operating system to take notice of an external event, such
as a mouse click. Software interrupts, better known as exceptions, allow the OS to
handle unusual events like divide-by-zero errors coming from code execution.

The sequence of events is usually like this:

Hardware signals an interrupt to the processor
The processor notices the interrupt and suspends the currently running software
The processor jumps to the matching interrupt handler function in the OS
The interrupt handler runs its course and returns from the interrupt
The processor resumes where it left off in the previously running software
The most important interrupt for the operating system is the timer tick interrupt. The
timer tic interrupt allows the OS to periodically regain control from the currently
running user process. The OS can then decide to schedule another process, return back
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to the same process, do housekeeping, etc. The timer tick interrupt provides the
foundation for the concept of preemptive multitasking.

TYPES OF INTERRUPTS
Generally there are three types of Interrupts those are Occurred For Example
1) Internal Interrupt
2) External Interrupt.
3) Software Interrupt.

1.Internal Interrupt:
• When the hardware detects that the program is doing something wrong, it will
usually generate an interrupt usually generate an interrupt.
– Arithmetic error - Invalid Instruction
– Addressing error - Hardware malfunction
– Page fault – Debugging
• A Page Fault interrupt is not the result of a program error, but it does require the
operating system to get control.

The Internal Interrupts are those which are occurred due to Some Problem in
the Execution For Example When a user performing any Operation which contains any
Error and which contains any type of Error. So that Internal Interrupts are those
which are occurred by the Some Operations or by Some Instructions and the
Operations those are not Possible but a user is trying for that Operation. And The
Software Interrupts are those which are made some call to the System for Example
while we are Processing Some Instructions and when we wants to Execute one more
Application Programs.

2.External Interrupt:
• I/O devices tell the CPU that an I/O request has completed by sending an interrupt
signal to the processor.
• I/O errors may also generate an interrupt.

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• Most computers have a timer which interrupts the CPU every so many interrupts the
CPU every so many milliseconds.

The External Interrupt occurs when any Input and Output Device request for any
Operation and the CPU will Execute that instructions first For Example When a
Program is executed and when we move the Mouse on the Screen then the CPU will
handle this External interrupt first and after that he will resume with his Operation.

3.Software interrupts:
These types if interrupts can occur only during the execution of an instruction. They
can be used by a programmer to cause interrupts if need be. The primary purpose of
such interrupts is to switch from user mode to supervisor mode.

A software interrupt occurs when the processor executes an INT instruction.

Written in the program, typically used to invoke a system service. A processor
interrupt is caused by an electrical signal on a processor pin. Typically used by devices
to tell a driver that they require attention. The clock tick interrupt is very common; it
wakes up the processor from a halt state and allows the scheduler to pick other work
to perform.

A processor fault like access violation is triggered by the processor itself when it
encounters a condition that prevents it from executing code. Typically when it tries to
read or write from unmapped memory or encounters an invalid instruction.

CISC Characteristics
A computer with large number of instructions is called complex instruction set
computer or CISC. Complex instruction set computer is mostly used in scientific
computing applications requiring lots of floating point arithmetic.
 A large number of instructions - typically from 100 to 250 instructions.
 Some instructions that perform specialized tasks and are used infrequently.
 A large variety of addressing modes - typically 5 to 20 different modes.
 Variable-length instruction formats

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 Instructions that manipulate operands in memory.

RISC Characteristics
A computer with few instructions and simple construction is called reduced
instruction set computer or RISC. RISC architecture is simple and efficient. The major
characteristics of RISC architecture are,
 Relatively few instructions
 Relatively few addressing modes
 Memory access limited to load and store instructions
 All operations are done within the registers of the CPU
 Fixed-length and easily-decoded instruction format.
 Single cycle instruction execution
 Hardwired and micro programmed control

Example of RISC & CISC

Examples of CISC instruction set architectures are PDP-11, VAX, Motorola 68k,
and your desktop PCs on intel’s x86 architecture based too .
Examples of RISC families include DEC Alpha, AMD 29k, ARC, Atmel AVR,
Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power (including PowerPC),
SuperH, SPARC and ARM too.

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Which one is better ?

We cannot differentiate RISC and CISC technology because both are suitable at its specific
application. What counts is how fast a chip can execute the instructions it is given and how well it
runs existing software. Today, both RISC and CISC manufacturers are doing everything to get an
edge on the competition.

http://www.laureateiit.com/projects/bacii2014/projects/coa_anil/i_o_interface.html

UNIT – III (12 Lectures)

MICRO-PROGRAMMED CONTROL: Control memory, address sequencing, micro-program
example, design of control unit.
Book: M. Moris Mano (2006), Computer System Architecture, 3rd edition, Pearson/PHI,
India: Unit-7 Pages: 213-238

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