MODULE-4

CMOS Circuit and Logic Design

STATIC CMOS:

The static CMOS is a combinational circuit with pull-up network (PUN) and pull-down
network (PDN). Static CMOS is particularly used for designing the high-level integrated
circuits. The static CMOS consumes low power and gives reliable performance in a system.
 Static CMOS circuits can take up more silicon area compared to dynamic circuits due to
the need for multiple transistors per gate.
 Static CMOS circuits may have slower switching speeds compared to dynamic CMOS
circuits because of the need for more complex transistors.

PSEUDO NMOS LOGIC:

 This logic structure consists of the pull up circuit being replaced by a single pull up
pmos whose gate is permanently grounded.
 This actually means that pmos is all the time on and that now for a n input logic we
have only n+1 gates. This technology is equivalent to the depletion mode type and
preceded the CMOS technology and hence the name pseudo.
 The disadvantage is that since the pMOS is always on, static power dissipation occurs
whenever the nmos is on. Hence the conclusion is that in order to use pseudo logic a
tradeoff between size & load or power dissipation has to be made.
Example of Pseudo nMOS logic:

DYNAMIC CMOS DESIGN:

In this section, an alternate logic style called dynamic logic is presented that obtains a similar
result, while avoiding static power consumption. With the addition of a clock input, it uses a
sequence of precharge and conditional evaluation phases.

The basic construction of an (n-type) dynamic logic gate is shown in Figure. The PDN (pull-
down network) is constructed exactly as in complementary CMOS. The operation of this circuit
is divided into two major phases: precharge and evaluation, with the mode of operation
determined by the clock signal CLK.
Precharge :-

When CLK = 0, the output node Out is precharged to VDD by the PMOS transistor. During that
time, the evaluate NMOS transistor is off, so that the pull-down path is disabled. The evaluation
FET eliminates any static power that would be consumed during the precharge period (this is,
static current would flow between the supplies if both the pulldown and the precharge device
were turned on simultaneously).

Evaluation:-

For CLK = 1, the precharge transistor is off, and the evaluation transistor is turned on. The
output is conditionally discharged based on the input values and the pull-down topology. If the
inputs are such that the PDN conducts, then a low resistance path exists between Out and GND
and the output is discharged to GND.
There are solutions to overcome cascading issue in dynamic CMOS logic:
4-phase logic
Domino logic
NORA/NP domino logic

4-PHASE LOGIC:

 Pz is the precharge node.

 Z is the final output node.
 Precharge is controlled by -clk12.
 Evaluation happens when clk23 goes high.
 Transmission gate passes Pz to z when clk23 is high.
 Timing phases: clk1 to clk4.

Step-by-step Operation using Timing Diagram

1. clk1 phase

 clk1 = HIGH, so clk12 = HIGH → -clk12 = LOW

 This LOW on -clk12 turns ON the PMOS at Pz
 ⇒ Pz is precharged to Vdd (logic high)

2. clk2 phase

 clk2 = HIGH, so clk12 remains HIGH → -clk12 = still LOW

 Precharge continues to hold Pz at high.
 Meanwhile, clk23 goes HIGH during clk2
 ⇒ Evaluation logic starts to pull down Pz based on input conditions (a, b, c, d)
3. clk3 phase

 clk1 and clk2 are LOW ⇒ clk12 = LOW → -clk12 = HIGH

 Precharge PMOS turns OFF (precharge ends)
 clk23 = still HIGH → Evaluation continues
o If pull-down network is ON (based on input logic), Pz is discharged to 0
o If pull-down network is OFF, Pz remains high

4. clk4 phase

 clk4 = HIGH ⇒ Transmission gate turns ON

 Now, the value on Pz is transferred to z
o If Pz was discharged → z = 0
o If Pz stayed charged → z = 1

At this point: z holds valid data

 Output z is valid during clk4 and clk1, as stated in the note.

This diagram shows how gates operating on different clock phases can be safely connected.
  TYPE 1 to TYPE 4 gates correspond to gates clocked by φ₁ to φ₄ .
 Arrows indicate allowable connections (safe signal transfers between gates).
 Rules:
o A gate clocked by φ₁ can feed a gate clocked by φ₂ (and so on in a clockwise
manner).
o This avoids timing hazards like race conditions or data corruption.
o Cross connections (diagonal) are also allowed under certain setups but should
obey the timing constraints.

DOMINO LOGIC :

 A Domino logic module consists of an n-type dynamic logic block followed by a static
inverter.
 During precharge, the output of the n type dynamic gate is charged up to VDD, and the
output of the inverter is set to 0.
 During evaluation, the dynamic gate conditionally discharges, and the output of the
inverter makes a conditional transition from 0 to 1.
There are also some other limitations associated with domino CMOS logic gates:

First, only non inverting structures can be implemented using domino CMOS. If necessary,
inversion must be carried out using conventional CMOS logic. Also, charge sharing between the
dynamic stage output node and the intermediate nodes of the n MOS logic block during the
evaluation phase.

Example of domino logic gate:

NORA CMOS LOGIC (NP-DOMINO LOGIC) :

.
 The advantage of NORA CMOS logic is that a static CMOS inverter is not required at the
output of every dynamic logic stage. Instead, direct coupling of logic blocks is feasible by
alternating nMOS and pMOS logic blocks.
• The second important advantage of NORA CMOS logic is that it allows pipelined
system architecture.
• As in all dynamic CMOS structures, NORA CMOS logic gates also suffer from
charge sharing and leakage.
CLOCKED CMOS LOGIC:

It’s a type of CMOS circuit that uses a clock signal to control when the logic evaluates. It’s a
combination of complementary CMOS logic and clocked transistors. Clocking the logic
allows better timing control and power gating. Only the required stages are activated at a time,
saving energy.
For example, in the C²MOS structure, logic evaluation only occurs when the clock allows it,
avoiding unwanted transitions.

Phase 1: Precharge (when clk = 0)

 The PMOS at the top turns ON.

 The NMOS at the bottom turns OFF.
 Output node is charged to Vdd (logic 1).
 No logic operation happens now, just charging.
Phase 2: Evaluation (when clk = 1)

 The PMOS at the top turns OFF.

 The NMOS at the bottom turns ON.
 Now, the logic circuit evaluates based on inputs.
o If the inputs form a conducting path → output discharges → logic 0.
o If not → output stays high → logic 1.

Only one of these happens during a clock cycle, reducing unnecessary transitions → saves
power.

A limitation is that series clocking transistors (those controlled by the clock) add resistance,
which slows down signal transitions (increases rise and fall times).

CASCADE VOLTAGE SWITCH LOGIC:

CVSL is a differential CMOS logic style, meaning it uses both the true and complement
forms of input signals. It differs from standard CMOS logic in its structure and performance
characteristics.
How it works:

 Two complementary NMOS switch structures are used.

 These are connected to a pair of cross-coupled PMOS (pull-up) transistors.
 When the input signals (true and complement) are applied:
o One NMOS network will conduct, pulling its corresponding output node low.
o The cross-coupled PMOS pair will then pull the other output node high through
positive feedback, ensuring a fast transition and strong output levels.
 The output is differential two nodes and (complement), one high and one low.

Advantages: Can create complex logic functions with fewer transistors in the logic tree, making
CVSL advantageous for logic density.

PASS TRANSISTOR:

Pass Transistor circuits typically require fewer transistors than standard CMOS logic (which
uses both pull-up and pull-down networks).
Leads to smaller area and lower capacitance.
ELECTRICAL AND PHYSICAL DESIGN OF LOGIC GATES:
Physical layout design using Euler’s graph:
BODY EFFECT:

 Every MOSFET (transistor) has four terminals: Gate, Source, Drain, and Body (also
called substrate).
 Normally, the body is connected to the lowest voltage (usually ground for NMOS).
 The threshold voltage (V_th) of a MOSFET is the voltage required at the
gate to turn it ON.
 But if the source of the transistor is not at 0V, then the voltage difference between the
source and body causes the threshold voltage to increase.
This is known as the body effect.

As Vth increases, Vth increases ⇒ harder to turn ON the transistor.

Look at Figure 5.24 (a) – this is a multiple input NMOS gate, such as a NAND gate.

Working:

 Inputs A, B, C are connected to NMOS transistors in series.

 If all inputs are HIGH (logic 1), then the output should be pulled LOW through the
NMOS path.
 BUT — because they’re in series:
o The source of each transistor is at a different voltage, not at 0V.
o For example, in the bottom transistor (connected to OUT), the source is the OUT
node itself.
o The source of the next transistor up is the drain of the one below.
o This causes V ≠ 0, and due to the body effect, Vth increases for upper transistors.
o So they turn ON more slowly or weakly ⇒ gate becomes slower.
 The fall time (time to discharge the output) increases.
 The gate takes longer to switch from HIGH to LOW.
 This is worse in series connections, like 3-input NAND/NOR gates.
 It leads to slower performance and more power dissipation.

1. Reduce number of transistors in series: Less body effect.

2. Reordering A, B, C inputs to minimize body effect.
3. That putting the critical input closer to GND helps.