1. What is computer architecture?

a) set of categories and methods that specify the functioning, organisation, and implementation of
computer systems

b) set of principles and methods that specify the functioning, organisation, and implementation of
computer systems

c) set of functions and methods that specify the functioning, organisation, and implementation of
computer systems

d) None of the mentioned

View Answer

Answer: b

Explanation: A set of principles and methods that specify the functioning, organisation, and
implementation of computer systems is known as computer architecture. A system’s architecture
refers to its structure in terms of the system’s individually specified components and their
interrelationships.

2. What is computer organization?

a) structure and behaviour of a computer system as observed by the user

b) structure of a computer system as observed by the developer

c) structure and behaviour of a computer system as observed by the developer

d) All of the mentioned

View Answer

Answer: a

Explanation: The structure and behaviour of a computer system as observed by the user is the
subject of computer organisation.

3. Which of the following is a type of computer architecture?

a) Microarchitecture

b) Harvard Architecture

c) Von-Neumann Architecture

d) All of the mentioned

View Answer

Answer: d
Explanation: Below are the types of Computer Architecture:

i) Von-Neumann Architecture

ii) Harvard Architecture

iii) Instruction Set Architecture

iv) Microarchitecture

v) System Design

4. Which of the following is a type of architecture used in the computers nowadays?

a) Microarchitecture

b) Harvard Architecture

c) Von-Neumann Architecture

d) System Design

View Answer

Answer: c

Explanation: John von Neumann proposed this architecture. The architecture of today’s computers is
based on von Neumann architecture. It is based on a few ideas.

5. Which of the following is the subcategories of computer architecture?

a) Microarchitecture

b) Instruction set architecture

c) Systems design

d) All of the mentioned

View Answer

Answer: d

Explanation: The three main subcategories of computer architecture are:

i) Microarchitecture

ii) Instruction set architecture

iii) Systems design

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6. Which of the architecture is power efficient?

b) ISA

c) IANA

d) CISC

View Answer

Answer: a

Explanation: Hence the RISC architecture is followed in the design of mobile devices.

7. What does CSA stands for?

a) Computer Service Architecture

b) Computer Speed Addition

c) Carry Save Addition

d) None of the mentioned

View Answer

Answer: b

Explanation: The CSA is used to speed up the addition of multiplicands.

8. If an exception is raised and the succeeding instructions are executed completely, then the
processor is said to have ______

a) Generation word

b) Exception handling

c) Imprecise exceptions

d) None of the mentioned

View Answer

Answer: c

Explanation: The processor since as executed the following instructions even though an exception
was raised, hence the exception is treated as imprecise.

9. To reduce the memory access time we generally make use of ______

a) SDRAM’s

b) Heaps

c) Cache’s
d) Higher capacity RAM’s

View Answer

Answer: c

Explanation: The time required to access a part of the memory for data retrieval.

10. The IA-32 system follows which of the following design?

a) CISC

b) SIMD

c) RISC

d) None of the mentioned

View Answer

Answer: a

Explanation: This system architecture is used to reduce the steps involved in execution by
performing complex operations in one step.

11. Which of the following architecture is suitable for a wide range of data types?

a) IA-32

b) ARM

c) ASUS firebird

d) 68000

View Answer

Answer: a

Explanation: IA-32 architecture is suitable for a wide range of data types.

12. In IA-32 architecture along with the general flags, which of the following conditional flags are
provided?

a) TF

b) IOPL

c) IF

d) All of the mentioned

View Answer
Answer: d

Explanation: These flags are basically used to check the system for exceptions.

13. The VLIW architecture follows _____ approach to achieve parallelism.

a) SISD

b) MIMD

c) MISD

d) SIMD

View Answer

Answer: b

Explanation: The MIMD stands for Multiple Instructions Multiple Data.

14. What does VLIW stands for?

a) Very Long Instruction Width

b) Very Large Instruction Word

c) Very Long Instruction Width

d) Very Long Instruction Word

View Answer

Answer: d

Explanation: It is the architecture designed to perform multiple operations in parallel.

15. In CISC architecture most of the complex instructions are stored in _____

a) CMOS

b) Register

c) Transistors

d) Diodes

View Answer

Answer: c

Explanation: In CISC architecture more emphasis is given on the instruction set and the instructions
take over a cycle to complete.

16. Both the CISC and RISC architectures have been developed to reduce the ______
a) Time delay

b) Semantic gap

c) Cost

d) All of the mentioned

View Answer

Answer: b

Explanation: The semantic gap is the gap between the high level language and the low level
language.

17. ________ are the different type/s of generating control signals.

a) Hardwired

b) Micro-instruction

c) Micro-programmed

d) Both Micro-programmed and Hardwired

View Answer

Answer: d

Explanation: The above is used to generate control signals in different types of system architectures.

18. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is
(Where S is term of the Basic performance equation).

a) 2

b) ~1

c) ~7

d) 2

View Answer

Answer: b

Explanation: The value will be much lower in case of multiple BUS organisation.

19. The small extremely fast, RAM’s all called as ________

a) Heaps

b) Accumulators

c) Stacks
d) Cache

View Answer

Answer: d

Explanation: Cache’s are extremely essential in single BUS organisation to achieve fast operation.

20. For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution?

a) ANSA

b) Super-scalar

c) ISA

d) All of the mentioned

View Answer

Answer: b

Explanation: In super-scalar architecture, the instructions are set in groups and they’re decoded and
executed together reducing the amount of time required to process them.

21. What is the full form of ISA?

a) Industry Standard Architecture

b) International Standard Architecture

c) International American Standard

d) None of the mentioned

View Answer

Answer: c

Explanation: The ISA is an architectural standard developed by IBM for its PC’s.

22. Which of the following is the fullform of CISC?

a) Complex Instruction Sequential Compilation

b) Complete Instruction Sequential Compilation

c) Computer Integrated Sequential Compiler

d) Complex Instruction Set Computer

View Answer
Answer: d

Explanation: The CISC machines are well adept at handling multiple BUS organisation.

23. The reason for the cells to lose their state over time is ________

a) Use of Shift registers

b) The lower voltage levels

c) Usage of capacitors to store the charge

d) None of the mentioned

View Answer

Answer: c

Explanation: Since capacitors are used the charge dissipates over time.

24. In order to read multiple bytes of a row at the same time, we make use of ______

a) Memory extension

b) Cache

c) Shift register

d) Latch

View Answer

Answer: d

Explanation: The latch makes it easy to ready multiple bytes of data of the same row simultaneously
by just giving the consecutive column address.

25. The difference in the address and data connection between DRAM’s and SDRAM’s is _______

a) The requirement of more address lines in SDRAM’s

b) The usage of a buffer in SDRAM’s

c) The usage of more number of pins in SDRAM’s

d) None of the mentioned

View Answer

Answer: b

Explanation: The SDRAM uses buffered storage of address and data.

26. The chip can be disabled or cut off from an external connection using ______
a) ACPT

b) RESET

c) LOCK

d) Chip select

View Answer

Answer: d

Explanation: The chip gets enabled if the CS is set otherwise the chip gets disabled.

27. The controller multiplexes the addresses after getting the _____ signal.

a) INTR

b) ACK

c) RESET

d) Request

View Answer

Answer: d

Explanation: The controller gets the request from the device needing the memory read or write
operation and then it multiplexes the address.

28. The data is transferred over the RAMBUS as _______

a) Blocks

b) Swing voltages

c) Bits

d) Packets

View Answer

Answer: b

Explanation: By using voltage swings to transfer data, the transfer rate along with efficiency is
improved.

29. The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______

a) CMOS

b) Memory sticks

c) Blue-ray devices
d) Flash memory

View Answer

Answer: d

Explanation: The flash memory functions similar to the EEPROM but is much cheaper.

30. The flash memory modules designed to replace the functioning of a hard disk is ______

a) RIMM

b) FIMM

c) Flash drives

d) DIMM

View Answer

Answer: c

Explanation: The flash drives have been developed to provide faster operation but with lesser space.

31. The drawback of building a large memory with DRAM is ______________

a) The Slow speed of operation

b) The large cost factor

c) The inefficient memory organisation

d) All of the mentioned

View Answer

Answer: a

Explanation: The DRAM’s were used for large memory modules for a long time until a substitute was
found.

32. In a 4K-bit chip organisation has a total of 19 external connections, then it has _______ address if
8 data lines are there.

a) 10

b) 12

c) 9

d) 8

View Answer
Answer: c

Explanation: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 4K =
512 x 8 organisation).

33. What does ISO stands for?

a) International Software Organisation

b) Industrial Software Organisation

c) International Standards Organisation

d) Industrial Standards Organisation

View Answer

Answer: c

Explanation: The ISO is yet another architectural standard, used to design systems.

34. The bit used to signify that the cache location is updated is ________

a) Flag bit

b) Reference bit

c) Update bit

d) Dirty bit

View Answer

Answer: d

Explanation: When the cache location is updated in order to signal to the processor this bit is used.

35. During a write operation if the required block is not present in the cache then ______ occurs.

a) Write miss

b) Write latency

c) Write hit

d) Write delay

View Answer

Answer: a

Explanation: This indicates that the operation has missed and it brings the required block into the
cache.
36. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for
________

a) Id

b) Word

c) Tag

d) Block

View Answer

Answer: c

Explanation: The tag is used to identify the block mapped onto one particular cache block.

37. The bit used to indicate whether the block was recently used or not is _______

a) Reference bit

b) Dirty bit

c) Control bit

d) Idol bit

View Answer

Answer: b

Explanation: The dirty bit is used to show that the block was recently modified and for a
replacement algorithm.

38. The number successful accesses to memory stated as a fraction is called as _____

a) Access rate

b) Success rate

c) Hit rate

d) Miss rate

View Answer

Answer: c

Explanation: The hit rate is an important factor in performance measurement.

1. The smallest entity of memory is called _______

a) Cell

b) Block
c) Instance

d) Unit

View Answer

Answer: a

Explanation: Each data is made up of a number of units.

2. The collection of the above mentioned entities where data is stored is called ______

a) Block

b) Set

c) Word

d) Byte

View Answer

Answer: a

Explanation: Each readable part of the data is called blocks.

3. An 24 bit address generates an address space of ______ locations.

a) 1024

b) 4096

c) 248

d) 16,777,216

View Answer

Answer: d

Explanation: The number of addressable locations in the system is called as address space.

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4. If a system is 64 bit machine, then the length of each word will be _______

a) 4 bytes

b) 8 bytes

c) 16 bytes

d) 12 bytes
View Answer

Answer: b

Explanation: A 64 bit system means, that at a time 64 bit instruction can be executed.

5. The type of memory assignment used in Intel processors is _____

a) Little Endian

b) Big Endian

c) Medium Endian

d) None of the mentioned

View Answer

Answer: a

Explanation: The method of address allocation to data to be stored is called as memory assignment.

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6. When using the Big Endian assignment to store a number, the sign bit of the number is stored in
_____

a) The higher order byte of the word

b) The lower order byte of the word

c) Can’t say

d) None of the mentioned

View Answer

Answer: a

Explanation: None.

7. To get the physical address from the logical address generated by CPU we use ____________

a) MAR

b) MMU

c) Overlays

d) TLB

View Answer
Answer: b

Explanation: Memory Management Unit, is used to add the offset to the logical address generated
by the CPU to get the physical address.

8. _____ method is used to map logical addresses of variable length onto physical memory.

a) Paging

b) Overlays

c) Segmentation

d) Paging with segmentation

View Answer

Answer: c

Explanation: Segmentation is a process in which memory is divided into groups of variable length
called segments.

9. During the transfer of data between the processor and memory we use ______

a) Cache

b) TLB

c) Buffers

d) Registers

View Answer

Answer: d

Explanation: None.

10. Physical memory is divided into sets of finite size called as ______

a) Frames

b) Pages

c) Blocks

d) Vectors

View Answer

Answer: a

Explanation: None
1. The decimal numbers represented in the computer are called as floating point numbers, as the
decimal point floats through the number.

a) True

b) False

View Answer

Answer: a

Explanation: By doing this the computer is capable of accommodating the large float numbers also.

2. The numbers written to the power of 10 in the representation of decimal numbers are called as
_____

a) Height factors

b) Size factors

c) Scale factors

d) None of the mentioned

View Answer

Answer: c

Explanation: These are called as scale factors cause they’re responsible in determining the degree of
specification of a number.

3. If the decimal point is placed to the right of the first significant digit, then the number is called
________

a) Orthogonal

b) Normalized

c) Determinate

d) None of the mentioned

View Answer

Answer: b

Explanation: None.

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4. ________ constitute the representation of the floating number.

b) Significant digits

c) Scale factor

d) All of the mentioned

View Answer

Answer: d

Explanation: The following factors are responsible for the representation of the number.

5. The sign followed by the string of digits is called as ______

a) Significant

b) Determinant

c) Mantissa

d) Exponent

View Answer

Answer: c

Explanation: The mantissa also consists of the decimal point.

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6. In IEEE 32-bit representations, the mantissa of the fraction is said to occupy ______ bits.

a) 24

b) 23

c) 20

d) 16

View Answer

Answer: b

Explanation: The mantissa is made to occupy 23 bits, with 8 bit exponent.

7. The normalized representation of 0.0010110 * 2 9 is _______

a) 0 10001000 0010110

b) 0 10000101 0110

c) 0 10101010 1110
d) 0 11110100 11100

View Answer

Answer: b

Explanation: Normalized representation is done by shifting the decimal point.

8. The 32 bit representation of the decimal number is called as ___________

a) Double-precision

b) Single-precision

c) Extended format

d) None of the mentioned

View Answer

Answer: b

Explanation: None.

9. In 32 bit representation the scale factor as a range of ________

a) -128 to 127

b) -256 to 255

c) 0 to 255

d) None of the mentioned

View Answer

Answer: a

Explanation: Since the exponent field has only 8 bits to store the value.

10. In double precision format, the size of the mantissa is ______

a) 32 bit

b) 52 bit

c) 64 bit

d) 72 bit

View Answer

Answer: b
Explanation: The double precision format is also called as 64 bit representation.

1. ______ have been developed specifically for pipelined systems.

a) Utility software

b) Speed up utilities

c) Optimizing compilers

d) None of the mentioned

View Answer

Answer: c

Explanation: The compilers which are designed to remove redundant parts of the code are called as
optimizing compilers.

2. The pipelining process is also called as ______

a) Superscalar operation

b) Assembly line operation

c) Von Neumann cycle

d) None of the mentioned

View Answer

Answer: b

Explanation: It is called so because it performs its operation at the assembly level.

3. The fetch and execution cycles are interleaved with the help of ________

a) Modification in processor architecture

b) Clock

c) Special unit

d) Control unit

View Answer

Answer: b

Explanation: The time cycle of the clock is adjusted to perform the interleaving.

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4. Each stage in pipelining should be completed within ___________ cycle.

a) 1

b) 2

c) 3

d) 4

View Answer

Answer: a

Explanation: The stages in the pipelining should get completed within one cycle to increase the
speed of performance.

5. In pipelining the task which requires the least time is performed first.

a) True

b) False

View Answer

Answer: b

Explanation: This is done to avoid starvation of the longer task.

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6. If a unit completes its task before the allotted time period, then _______

a) It’ll perform some other task in the remaining time

b) Its time gets reallocated to a different task

c) It’ll remain idle for the remaining time

d) None of the mentioned

View Answer

Answer: c

Explanation: None.

7. To increase the speed of memory access in pipelining, we make use of _______

a) Special memory locations

b) Special purpose registers

c) Cache
d) Buffers

View Answer

Answer: c

Explanation: By using the cache we can reduce the speed of memory access by a factor of 10.

8. The periods of time when the unit is idle is called as _____

a) Stalls

b) Bubbles

c) Hazards

d) Both Stalls and Bubbles

View Answer

Answer: d

Explanation: The stalls are a type of hazards that affect a pipelined system.

9. The contention for the usage of a hardware device is called ______

a) Structural hazard

b) Stalk

c) Deadlock

d) None of the mentioned

View Answer

Answer: a

Explanation: None.

10. The situation wherein the data of operands are not available is called ______

a) Data hazard

b) Stock

c) Deadlock

d) Structural hazard

View Answer

Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.