Chapter 2

I/O Organization

| Computer |
| Architecture |
2 Outline

 I nt r o ducti on

 P e r i phera l De v i ces

 I np ut - Output I nt er f ace

 I nt er na l S t r uct ure o f a n I / O I nt er f ace

 Dat a T r a ns f er Me t hod s

 As y nchro nous Da t a Tr a ns f er
3 Introduction

 This chapter discusses the techniques that

computers use to communicate with input and

output devices.

 The procedure for asynchronous transfer of either

parallel or serial data is explained.

4 Introduction

 The most familiar means of entering information into

a computer is through a keyboard that allows a

person to enter alphanumeric information directly.

 The fastest possible speed for entering information

this way depends on the person's typing speed.

5 Computer Peripherals

 On the other hand, the central processing unit (CPU)

is an extremely fast device capable of performing
operations at very high speed.

 The processor will be idle most of the time while

waiting for the information to arrive via a slow
keyboard.
6 Computer Peripherals

 To use a computer efficiently, a large amount of

programs and data must be prepared in advance
and transmitted into a storage medium.
 The information in the storage medium is then
transferred into computer memory at a rapid rate.
 Results of programs are also transferred into a high-
speed storage, such as disks, from which they can be
transferred later into a printer.
7 Computer Peripherals

 Input or output devices attached to the computer

are called peripherals.
 Among the most common peripherals are keyboards,
display units, and printers.
 Peripherals that provide auxiliary storage for the
system are magnetic, solid-state drives (SSD) – which
are semiconductor-based storage devices - and
optical disks.
8 Input-Output Interface

 Peripherals connected to a computer need special

communication links for interfacing them with the
central processing unit (CPU).

 The purpose of the communication link is to resolve

the differences that exist between the CPU and
each peripheral.
9 Input-Output Interface

 The major differences are:

▪ The data transfer rate of peripherals is usually slower

than the transfer rate of the CPU, and consequently,
a synchronization mechanism may be needed.

▪ Data codes and formats in peripherals differ from

the word format in the CPU and memory.
10 Input-Output Interface

 To resolve these differences, computer systems

include special hardware components between the
CPU and peripherals to supervise and synchronize
all input and output transfers.

 These components are called interface units

because they interface between the processor bus
and the peripheral device.
11 I/O Bus and Interface Modules

 A typical communication link between the processor

and several peripherals is shown in the figure below.
 The I/O bus consists of data lines, address lines, and
control lines.
 Each peripheral has associated with it an interface unit.
 Each interface decodes the address and control
received from the I/O bus and provides signals for the
peripheral controller.
12 I/O Bus and Interface Modules
13 I/O Bus and Interface Modules

 It also synchronizes the data flow and supervises the

transfer between peripheral and processor.
 The I/O bus from the processor is attached to all
peripheral interfaces. To communicate with a
particular device, the processor places a device
address on the address lines.
 Each interface attached to the I/O bus contains an
address decoder that monitors the address lines.
14 I/O Bus and Interface Modules

 When the interface detects its own address, it

activates the path between the bus lines and the
device.
 At the same time that the address is made available
on the address lines, the processor provides a function
code in the control lines.
 The function code is referred to as an I/O command.
 There are four types of commands that an interface
may receive.
15 Types of I/O Commands

 A control command is issued to activate the peripheral

and to inform it what to do.
 A status command is used to test various status
conditions in the interface and the peripheral.
 A data output command causes the interface to
respond by transferring data from the bus into one of its
registers.
 The data input command is the opposite of the data
output.
16 I/O and Memory Communication

 In addition to communicating with I/O, the

processor must communicate with the memory unit.

 Like the I/O bus, the memory bus contains data,

address, and read/write control lines.

 There are three ways that computer buses can be

used to communicate with memory and I/O.
17 I/O and Memory Communication

 The three ways that computer buses can be used to

communicate with memory and I/O are:
▪ Use two separate buses, one for memory and the
other for I/O.
▪ Use one common bus for both memory and I/O
but have separate control lines for each.
▪ Use one common bus for memory and I/O with
common control lines.
18 Isolated versus Memory-Mapped I/O

 In the isolated I/O, the CPU has distinct input and

output instructions. The isolated I/O method isolates
memory and I/O addresses.
 Other alternative is to use the same address space
for both memory and I/O. This is the case in
computers that do not distinguish between memory
and I/O addresses. This configuration is referred to as
memory-mapped I/O.
19 Isolated versus Memory-Mapped I/O

 In a memory-mapped I/O, The computer treats an

interface register as being part of the memory system.
This reduces the memory address range available.
 Also, there are no specific input or output instructions
in a memory-mapped I/O.
 The CPU can manipulate I/O data residing in interface
registers with the same instructions that are used to
manipulate memory.
20 Example of I/O Interface

 An example of an l/O interface unit is shown in the block

diagram below.
 It consists of two data registers called ports, a control
register, a status register, bus buffers, and timing and
control circuits.
 The interface communicates with the CPU through the
data bus. The chip select and register select inputs
determine the address assigned to the interface.
21 Example of I/O Interface
22 Example of I/O Interface

 The l/O read and write are two control lines

that specify an input or output, respectively.
 The four registers communicate directly with the l/O device
attached to the interface.
 The l/O data to and from the device can be transferred into
either port A or port B.
 The interface may operate with an output device or with an
input device, or with a device that requires both input and
output.
23 I/O Interface Example

 Control is sent to the control register,

status information is received from the
status register, and data are transferred to and from ports A
and B registers.
 Thus, the transfer of data, control, and status information is
always via the common data bus.
 The distinction between data, control, or status information is
determined from the particular interface register with which
the CPU communicates.
24 Asynchronous Data Transfer

 A CPU and an I/O interface are designed

independently of each other.
 If the registers in the interface share a common clock
with the CPU registers, the transfer between the two
units is said to be synchronous.
 If the internal timing in any unit is independent from the
other (each uses its own private clock for internal
registers), the two units are said to be asynchronous to
each other.
25 Asynchronous Data Transfer

 Asynchronous data transfer between two independent

units requires that control signals be transmitted
between the communicating units to indicate the time
at which data is being transmitted.

 Two asynchronous data transfer methods can be used:

➢ Strobe method (source- or destination-initiated).

➢ Handshaking method (source-initiated or destination-

initiated).
26 Asynchronous Data Transfer

 The CPU is the source unit during an output or a write

transfer, and the CPU is the destination unit during an
input or a read transfer.
 The asynchronous transfer between two independent
units can be specified by a timing diagram.
 The timing diagram shows the timing relationship that
must exist between the control signals and the data in
the buses.
27 Method 1: Strobe Control

 The strobe control method of asynchronous data transfer

employs a single control line to time each transfer.
 The strobe may be activated by either the source or the
destination unit. The figure below shows a source-
initiated transfer.
 The data bus carries the data from the source unit to the
destination unit.
 The strobe signal informs the destination unit when a
valid data is available in the bus.
28 Method 1: Strobe Control
29 Method 1: Strobe Control

 The figure below shows a data transfer initiated by the

destination unit.

 In this case the destination unit activates the strobe

pulse, informing the source to provide the data.

 The source unit responds by placing the requested

binary information on the data bus.
30 Method 1: Strobe Control
31 Method 1: Strobe Control

 The data must be valid and remain in the bus long

enough for the destination unit to accept it.

 The strobe could be a write control signal from the

CPU to a peripheral.
32 Disadvantages of Strobe Method

 The source unit that initiates the transfer has no way of

knowing whether the destination unit has actually
received the data item that was placed in the bus.

 Similarly, a destination unit that initiates the transfer has

no way of knowing whether the source unit has
actually placed the data on the bus.

 The handshake method solves these problems.

33 Two-Wire Handshaking

 The handshake method solves this problem by

introducing a second control signal that provides a
reply to the unit that initiates the transfer.
 There are two control lines: one control line in the same
direction as the data flow in the bus from the source to
the destination.
 It is used by the source unit to inform the destination unit
whether there are valid data in the bus.
34 Source Initiated Handshaking

 The other control line is in the other direction from the

destination to the source. It is used by the destination
unit to inform the source whether it can accept data.
 The figure below shows the data transfer procedure
when initiated by the source.
 The two handshaking lines are data valid, which is
generated by the source unit, and data accepted,
generated by the destination unit.
35 Source Initiated Handshaking

Source initiated transfer using handshaking.

36 Destination Initiated Handshaking

 The destination-initiated transfer using handshaking lines

is shown in the figure below.
 The name of the signal generated by the destination
unit has been changed to ready for data to reflect its
new meaning.
 The source unit in this case does not place data on the
bus until after it receives the ready for data signal from
the destination unit.
37 Destination Initiated Handshaking

Destination initiated transfer using handshaking.

38 Advantages of Handshaking

 The handshaking scheme provides a high degree of

reliability because the successful completion of a data
transfer relies on active participation by both units.

 If one unit is faulty, the data transfer will not be completed.

 Such an error can be detected by means of a timeout

mechanism, which produces an alarm if the data transfer
is not completed within a predetermined time.
39 Advantages of Handshaking

 The timeout is implemented by means of an internal

clock that starts counting time when the unit enables
one of its handshaking control signals.
 If the return handshake signal does not respond within
a given time period, the unit assumes that an error has
occurred.
 The timeout signal can be used to interrupt the
processor and hence execute a service routine that
takes appropriate error recovery action.
40 Asynchronous Serial Transfer

 The transfer of data between two units may be done in

parallel or serial.
 In parallel data transmission, each bit of the message
has its own path, and the total message is transmitted at
the same time (n-bit message uses n conductor paths).
 In serial data transmission, each bit in the message is
sent in sequence one at a time.
 This method requires the use of one pair of conductors.
41 Asynchronous Serial Transfer

 Parallel transmission is faster but requires many wires.

 It is used for short distances and where speed is
important.
 Serial transmission is slower but is less expensive since it
requires only one pair of conductors.
 Serial transmission can be synchronous or asynchronous.
 In synchronous transmission, the two units share a
common clock and bits are transmitted continuously at
the rate dictated by the clock pulses.
42 Asynchronous Serial Transfer

 In long-distant serial transmission, each unit is driven by a

separate clock (asynchronous) of the same frequency.
 The line remains idle when there is no information to be
transmitted.
 A serial asynchronous data transmission technique
employs special bits that are inserted at both ends of
the character code.
 Each character consists of three parts: a start bit, the
character bits, and stop bits.
43 Asynchronous Serial Transfer

 The first bit, called the start bit, is always a 0 and is used
to indicate the beginning of a character.
 The last bit called the stop bit is always a 1.
 An example of this format is shown in the figure below.
44 Asynchronous Serial Transfer

 Transmitted character can be detected by the receiver

from knowledge of the following transmission rules:
1. When a character is not being sent, the line is kept in
the 1-state.
2. The initiation of a character transmission is detected
from the start bit, which is always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a
stop bit is detected when the line returns to the 1-
state for at least one bit time.
45 Asynchronous Serial Transfer

 Using these rules, the receiver can detect the start bit
when the line goes from 1 to 0. A clock in the receiver
examines the line at proper bit times.
 The receiver knows the transfer rate of the bits and the
number of character bits to accept.
 After the character bits are transmitted, one or two stop
bits are sent.
 The stop bits are always in the 1-state and frame the
end of the character to signify the idle state.
46 Baud Rate

 For example,
Consider the serial transmission of a terminal whose
transfer rate is 10 characters per second.
 Each transmitted character consists of a start bit, eight
information bits, and two stop bits, for a total of 11 bits.
47 Baud Rate

 The baud rate is the rate at which serial information is

transmitted (the data transfer in bits per second).
 Ten characters per second with an 11-bit format has a
transfer rate of 110 baud.
 ICs are available to provide the serial interface
between computer and terminals.
 Such a circuit is called a Universal Asynchronous
Receiver-Transmitter (UART).
48 References

[1] William Stallings (2016), Computer Organization

and Architecture- designing for performance, 10th

edition, Pearson Education.

[2] M. Morris Mano (2006), Computer System

Architecture, 3rd edition, Pearson/PHI, India.