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Exp 1 - Vlsi Design Lab

The document outlines the VLSI Design Laboratory course for the academic year 2024-2025, detailing experiments on digital circuits including half adder, full adder, half subtractor, and full subtractor using Xilinx EDA tools. It includes procedures for simulation and implementation, along with Verilog code examples for each circuit. The aim is to study the simulation and synthesis of various digital circuits using Xilinx Vivado 2020.1.

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sriranganvel2004
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3 views10 pages

Exp 1 - Vlsi Design Lab

The document outlines the VLSI Design Laboratory course for the academic year 2024-2025, detailing experiments on digital circuits including half adder, full adder, half subtractor, and full subtractor using Xilinx EDA tools. It includes procedures for simulation and implementation, along with Verilog code examples for each circuit. The aim is to study the simulation and synthesis of various digital circuits using Xilinx Vivado 2020.1.

Uploaded by

sriranganvel2004
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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RECORD NOTE

ACADEMIC YEAR 2024 - 2025

DEPARTMENT OF ECE

LAB CODE / LAB NAME : 20EC6202 / VLSI DESIGN LABORATORY


YEAR / SEMESTER/CLASS : III YEAR / VI SEMESTER/B.E. ECE

STUDENT NAME :
REGISTER NUMBER :
INDEX

EXP.NO DATE NAME OF THE EXPERIMENT MARKS SIGNATURE


.
Logic diagram: Half Adder

Program:
//Half Adder
module half_add(sum,carry,a,b);
input a,b;
output sum,carry;
xor(sum,a,b);
and(carry,a,b);
endmodule
Simulation Output: -

Device Utilization and Power Report:


EXP. NO.: 01
DATE :
DESIGN AND IMPLEMENTATION OF LOGIC GATES AND ADDER
AIM:
To perform the simulation and implementation for a half adder, full adder, half subtractor and full subtractor
circuits using Xilinx EDA tool.
APPARATUS REQUIRED:
1. Personal Computer 2. XILINX 2020.1 software 3. Xilinx Spartan 7 FPGA
THEORY:
Simulation is functional emulation of the circuit design through software programs that uses
models to replicate how a system will perform in terms of timings and results.
Xilinx ISE tool supports the following simulation tools:
 HDL Bencher is an automated test bench creation tool. It is fully integrated
with Project Navigator.
 ModelSim from Model Technology, Inc, is integrated in Project Navigator to simulate the
design at all steps (Functional and Timing). ModelSim XE, the Xilinx Edition of Model
Technology, Inc.’s ModelSim application, can be installed from the MTE CD included in your
ISE Tool.
Synthesis describes the process of transformation of the model of a design, from one level of
abstraction in one domain [say HDL] to a lower level of abstraction in same or other domain.

PROCEDURE:
Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using the
Start Programs Xilinx 2020.1.
Step 2: Create a new project and Select File menu and then select New project.
Step3: Specify the project name and location in pop up window and click NEXT.
Step4: Select Device. Select the required family, device, package, speed grade, Synthesis tool
Simulator from new project wizard pop up window. Click NEXT. Project summary will be
displayed.
Step 5: Click FINISH to start Project.
Step6: To create new V file Right click on the device name and select NEW SOURCE
Step 7: Select VERILOG MODULE in NEW SOURCE WIZARD and give suitable name for the
Project. Click NEXT for the DEFINE MODULE Window Assign required ports in this Window.
Step 8: Write the Behavioural VERILOG Code in VERILOG Editor Sample code is given below for
this experiment.
Step 9: SIMULATION using ISE tool creating a test bench file and verify the operation of the
design
before

Logic Diagram: Half Subtractor

Program:
//half subtractor
module half_sub(diff,borrow,a,b);
input a,b;
output diff,borrow;
wire n1;
xor(diff,a,b);
not(n1,a);
and(borrow,n1,b);
endmodule
Simulation Output: -

Device Utilization and Power Report:


Logic Diagram:
Full adder:

PROGRAM:
//Full adder
module fulladd(a, b, cin, sum, cout);
input a,b,cin;
output sum,cout;
wire s1,a1,a2;
xor x2(s1,a,b);
xor x1(sum,s1,cin);
and an1(a1,a,b);
and an2(a2,cin,s1);
or r1(cout,a1,a2);
endmodule
Simulation Output: -

Device Utilization and Power Report:


Logic Diagram: Full subtractor:

Program:
//Full subtractor
module fullsub(diff,borrow,a,b,c);
input a,b,c;
output diff,borrow;
wire s1,a1,a2,n1,n2;
not nn1(n1,a);
not nn2(n2,s1);
xor x1(s1,a,b); xor x2(diff,s1,c);
and an1(a1,a,b); and an2(a2,c,s1);
or r2(borrow,a1,a2);
endmodule
Simulation Output: -

Device Utilization and Power Report:


Verilog Code for 8-bit adder:
module ripplemod(a, b, cin, sum, cout);
input [07:0] a;
input [07:0] b;
input cin;
output [7:0]sum;
output cout;
wire[6:0] c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);
fulladd a2(a[1],b[1],c[0],sum[1],c[1]);
fulladd a3(a[2],b[2],c[1],sum[2],c[2]);
fulladd a4(a[3],b[3],c[2],sum[3],c[3]);
fulladd a5(a[4],b[4],c[3],sum[4],c[4]);
fulladd a6(a[5],b[5],c[4],sum[5],c[5]);
fulladd a7(a[6],b[6],c[5],sum[6],c[6]);
fulladd a8(a[7],b[7],c[6],sum[7],cout);
endmodule

Simulation Output: -

Device Utilization and Power Report:


Result:
Thus, the simulation & synthesis of various digital circuits was studied using Xilinx
Vivado 2020.1 using Verilog HDL.

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