2024 The 9th International Conference on Integrated Circuits and Microsystems

Formal Verification and Verilog Code Generation

for Coq-based Carry-Lookahead Adder Algorithm
Kexin Chen Gang Chen
Nanjing University of Aeronautics and Astronautics Nanjing University of Aeronautics and Astronautics
Nanjing, China Nanjing, China
0009-0006-1961-1129 [email protected]
2024 9th International Conference on Integrated Circuits and Microsystems (ICICM) | 979-8-3315-0945-3/24/$31.00 ©2024 IEEE | DOI: 10.1109/ICICM63644.2024.10814122

Abstract—This article describes the application of customized TABLE I

proof techniques for proving theorems related to arithmetic A DVANTAGES OF T HEOREM P ROVING
circuits in the Coq theorem prover and generating Verilog code
from Coq. By illustrating the correctness verification process of Specificities Advantage Analysis
mathematical proof Have rigorous mathematical proofs
a carry-lookahead adder (CLA) as an example, this set of proof
versatility Not limited by circuit size or complexity
strategies not only significantly simplifies the proof process but highly customisable Can customise verification rules and properties
also enhances the efficiency of Coq formal verification in general. deep formal validation Can probe deeply into the formalisation of properties
It is also possible to generate Verilog code for CLA of arbitrary accuracy guarantee Ensure that the property being verified is absolutely true
size (up to 128 bits) based on Signal type. Additionally, the Verilog
code for CLA generated from Coq can be run directly, has been
synthesized and simulated in Quartus.
Index Terms—Coq Meta-proof, Custom Proof Strategies, In our prior research papers, the mathematical derivations
Hardware Formal Verification, Verilog, Arithmetic Circuits elucidating the principles of high-speed parallel adders have
been described [1]–[3]. However, these papers have not pro-
vided a comprehensive analysis of the key techniques and
I. I NTRODUCTION
strategic foundations employed during the Coq proof process.
As modern society continues to rely increasingly on digital In this paper, we have developed a plethora of reusable proof
circuits and embedded systems, the reliability and correctness strategies and tools aimed at automating the proof process and
of arithmetic circuits have become paramount. Arithmetic enhancing its efficiency. Based on the completion of the proof,
circuits find widespread applications across various domains, a Verilog code generator for CLA based on Coq has been
including computer processors, communication systems, med- made, which is capable of automatically generating Verilog
ical devices, and automatic control systems. In traditional cir- code for CLA with no more than 128 bits. We summarize our
cuit design, the validation of arithmetic circuit correctness typ- main contributions as follows.
ically relies on methods such as testing and simulation. While • We have provided a comprehensive exposition of the
these methods can help uncover certain design flaws, they process and intricacies involved in the Coq proof of a carry-
cannot provide complete correctness assurance. To address this lookahead adder. This serves to enhance the comprehension
challenge, formal verification methods have emerged. Formal of the design principles underlying high-speed parallel adders
verification is a mathematical and logic-based approach aimed and other arithmetic circuits.
at providing a formal proof of correctness for hardware • This paper provides a substantial supplement by offering
circuits. Unlike simulation-based methods, formal verification detailed Coq proofs and key techniques for the mathematical
offer proofs of correctness for all possible scenarios, thereby deduction and verification of the principles behind high-speed
providing a higher level of assurance. parallel adders, filling an important gap in the literature.
Formal verification can be roughly classified into two • On the basis of proving the correctness of the CLA,
classes. The first class is automated formal verification. The a code generator was developed independently, which can
main techniques include SAT, BDD, and model checking. The automatically generate the Verilog code of the CLA (the size
second class is based on theorem proving, which requires of the CLA does not exceed 128 bits) from the Coq.And
human machine interaction. the generated Verilog code can be synthesised and simulated
Automated equivalence checking based on SAT and BDD directly in Quartus.
are now well established and can effectively verify the correct- • We distil a reusable Coq library from correctness proofs of
ness of adder circuits. However, theorem proving techniques carry-lookahead adders, including a set of lemmas, and Ltac-
are still valuable in order to understand the principles of defined proof strategies, a library that will help support future
complex high-speed adders, to support the design of novel formal verification of arithmetic circuits.
addition circuits, to build formal hardware design libraries, and Related Works. Extensive work has also been conducted
to support modular formal hardware construction. In Table I, on the correctness proof of carry-lookahead adders. T. Lynch
we state the advantages of the theorem proving method. et al [4] proposed a 64-bit spanning tree carry-lookahead

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 adder (STCLA) with a hybrid carry-lookahead/carry-select introduce the basics of Coq theorem proving and the relevant
structure. Yuke Wang et al [5] also proposed a new hybrid principles.
carry-lookahead/carry-select scheme based on Ling’s carries In the Coq library, lemmas are defined as follows: they
and complemented the group carry terms to gain speed. are declared using the Lemma keyword (or T heorem, Goal,
J. O’Donnell and G. Rnger [6] employed high-order func- etc.) followed by the lemma’s name, and then a proposition
tional combinators to represent carry-lookahead adder and expression is provided after the colon.
the correctness is established by algebraic transformations. Lemmas provide a structured, step-by-step approach to
[7]considered formal verification of adder circuits for multiple- proving the correctness of a mathematical or logical assertion.
valued logic and prove that for different types of adder By breaking down a larger proof into smaller lemmas, the
circuits polynomial-time verification can be performed based proof can be more easily understood and validated. Addition-
on decision diagrams (DDs), which is also for fast adders like ally, Coq lemmas can be reused in other proofs, making them
the conditional sum adder and the carry- lookahead adder. a powerful tool for building up a library of proven results that
Quad trees-trees with four branches, are used to abstractly de- can be used to establish new assertions. Lemma reuse can
scribe tree-structured carry-lookahead adders using 4-bit com- make proofs more efficient. Below is an example of a simple
ponents. The specification and implementation descriptions are Coq lemma definition we customised:
parametrized and tree-structured adders having arbitrarily large
inputs and outputs are described. The descriptions are formally Lemma plus comm : f orall n m : nat, n + m = m + n.
verified using the HOL theorem power [8]. To prove this lemma, Coq’s tactics are employed to con-
The carry-lookahead adder is based on the principle of struct the proof:
parallel computation and shares similarities with many parallel
adders. Parallel adders are widely used in high-performance intros n m.rewrite N at.add comm.ref lexivity.Qed.
computer design and hardware acceleration for large-scale data In the above example, Introduce two variables and rewrite
processing. In the adder design theory, a key property of the the expression using the commutativity property of natural
group propagated carry and the group generated carry is based number addition. Finally, the ref lexivity tactic is employed
on the two recurrence equations. The property is fundamental to prove the equality.
to many parallel prefix adders [9]–[13]. [2]provided a formal Coq provides the Ltac sublanguage for users to construct
proof regarding Gi and Pi. The proof granted a solid under- customized proof strategies. Ltac can assist Coq users in
pinning for a formal verification methodology for ubiquitous automating tedious and repetitive proof steps, thereby making
parallel adders [1], [3], [14]–[16]. [17]computed of carries in proofs more accessible, faster, and more reliable. The basic
parallel, they were segmented into smaller pieces. It used carry syntax of Ltac is as follows:
propagate and generate as intermediate signals. [18]Device
used Xilinx 14.7 and the designs were simulated using ISim Ltac tactic name := tactic def inition.
Simulator and Altera Modelsim 10.1d. A comparison was
The fundamental principle of Ltac revolves around matching
made about the efficiency of KSA with Carry Look Ahead
and substitution. When defining tactics, a variety of different
adder (CLA) and Carry Skip Adder (CSA) with respect to
commands can be used such as intros, apply, rewrite,
speed and number of slice LUT’s used.
simpl, split, lef t, right, and so forth. These commands
The remainder of this article is organized as follows. Section
can be combined to form complex tactics that simplify proof
II introduces the basics of Coq theorem proving facilities,
process.
while Section III summarizes some of the self-developed
For example, here is an our customised tactic:
lemmas and strategies utilized in proving the correctness of
the carry-lookahead adder. The lemma repository established Ltac truth table tactic3 a b c :=
in this paper will be of significant assistance in future proofs intros; destruct a; destruct b; destruct c; trivial.
of more complex arithmetic circuits. Section IV presents the
application of our internally developed automated proof tech- When this tactic is applied to a proof goal, it matches a
niques in the verification of carry-lookahead adders. Section V pattern that introduces three variables and discusses all their
introduces in detail the automatic generation of CLA’s Verilog possible Boolean values in a categorical manner. Following
code of any length (no more than 128 bits) from Coq based this pattern, the custom strategy can achieve automated proofs
on the correctness proof of the carry-lookahead adder, and for equations involving any number of Boolean variables,
conducts synthesize and simulate in Quartus. Finally, Section simplifying the proof process for multi-variable Boolean equa-
VI concludes the paper. tions.
III. S ELF - DEVELOPED P ROOF S TRATEGIES AND L EMMAS
II. T HE BASICS OF C OQ T HEOREM P ROVING FOR C ARRY- LOOKAHEAD ADDER
In Coq, both Lemmas and Tactics are essential compo- The formal verification of CLA involves intricate mathemat-
nents in constructing formal proofs, utilized for deducing and ical expressions,inductive assumptions, and recursive struc-
demonstrating specific propositions or goals. This section will tures in parallel computation. It necessitates handling com-

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 plex mathematical substitutions and expression simplifica- The proof of using the auxiliary function doubleListRect
tions.While existing proof tactics may be capable of complet- to handle recursion. It handles comparisons and operations on
ing the proof for these specific requirements, the process can two lists, The different cases are controlled by the parameters.
become exceedingly cumbersome. Hence, it necessitates the
customization of a new set of tactics and lemmas to streamline C. Apply a Binary Function to Succesive Pairs of a List
and enhance the proof process. Simultaneously, they can also In formal proofs of arithmetic circuits, such as adder
be applied in other contexts of formal verification of arithmetic operations, two input lists of signals need to be merged
circuits. one by one. The resulting new list of signals participates in
the next computational step. So we customised two func-
A. Customised Dual Inductive Lemma
tions pairwise apply and pairwise pure, where function
During the formal verification of CLA, different cases of pairwise apply can be used to merge two lists of unequal
input signals may need to be considered when proving a length bit by bit; function pairwise pure can be used to
property of a circuit, e.g. a proof involving recursive properties merge two lists of equal length bit by bit. Applying these two
for multiple input variables or multiple states may require the binary functions to successive pairs of a list, we customise two
simultaneous consideration of multiple combinations of input lemmas, pairwise apply redr and pairwise pure redr,
and output signals. In that case analysing them one by one and their Coq codes are as follows:
using the inductive method would result in a large number of
subgoals and the situation would become very complicated. Lemma pairwise apply redr :
Therefore, we customise a new theorem nat ind2 to use f orall (l1 l2 : list A) (x y : A),
double induction to complete the proof, and its Coq code is
len eq l1 l2 →
as follows:
pairwise apply (l1 : +x) (l2 : +y) =
T heorem nat ind2 : f orall (P : nat → P rop), (pairwise apply l1 l2) : +(op x y).
(P 0) → (P 1) → (f orall (n : nat),
(P n) → (P (S (S n)))) → (f orall n, (P n)). The proof procedure for lemma pairwise pure redr is the
same. These two theorems can be used to verify the correctness
The goal of the theorem is to show that property P holds for of data signal propagation, circuit bit-level synthesis, and are
all natural numbers n. Use the lemma nat split to decompose applicable in logic synthesis.
the natural number n into two cases: n is odd or n is even.
For the case where n = 0, this can be proved directly using IV. A PPLICATION OF C USTOM AUTOMATED P ROOF
(P 0) in the prerequisite. If n is even, rewrite the expression T ECHNIQUES IN THE V ERIFICATION OF
using the lemma simple.even succ. If n is odd, rewrite the C ARRY-L OOKAHEAD A DDERS
condition and discuss the classification of n again, rewrite In this section, we introduce the basic principles and design
the substitution using Lemma simple.even succ and lemma features of the carry-lookahead adder. Next, we will delve into
succ add1, and finally complete the proof. the difficulties encountered in the proof process and present
In formal proofs of arithmetic circuits, this double induction independently developed proof strategies for such problems.
helps to prove some recursive properties or properties that We combine mathematical derivations to systematically dissect
require analysis of the natural numbers. the proof process.
B. Simultaneous Induction of Double Lists
A. Principles and Design of Carry-Lookahead Adders
When verifying the correctness of multi-digit arithmetic,
The core concept of a carry-lookahead adder (CLA) in-
cascade circuits, adders and multipliers, datapaths, etc., it is
volves two variables: Gi and Pi , where i represents the i-th
necessary to perform simultaneous induction on a double list
bit of the input data. G stands for Generator, and P stands
of inputs. One approach is to define new inductive theorems
for P ropagator. To illustrate the design principle, let’s take
tailored to address inductive proofs of such complex struc-
a 4-bit carry-lookahead adder as an example.
tures. Here, we introduce a custom inductive theorem named
doubleListInd, designed to simultaneously induct upon both Gi is defined as Ai &&Bi , representing the carry generate
a and b lists. It internally categorizes the possibility of whether signal, and Pi as Ai Bi , representing the carry propagate signal.
the lists are empty, encapsulating the fundamental handling Their generation process is depicted in Fig 1. Fig 2 shows the
methods for double equally sized lists. Its implementation in circuit diagram for generating the carry signal C4 in CLA.
Coq is as follows: CLA initiates the calculation of all carries as soon as
the input signals A and B reach the ports. The gate delay
T heorem doubleListInd : of a 4-bit carry-lookahead adder includes 3 gate levels for
P nil nil → (f orall la, P la nil) → computing C3 and an additional 1 gate level for the final GP
generator, totaling 4 gate levels. This represents more than a
(f orall lb, P nil lb) → (f orall a b la lb, P la lb →
50% reduction in gate levels compared to a 4-bit ripple carry
P (a :: la) (b :: lb)) → (f orall la lb, P la lb). adder with 9 gate levels of delay.

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 modeling approach, treating vectors as functions from natural
numbers to Boolean values. Thus, input vectors x and y are
both functions of type nat → bool.

V ariables x y : nat → bool.

Fig. 1. The generation process of G and P We introduce a natural number n, representing the upbound
of x and y:

V ariable n : nat.

To access vectors using the index variable i we need to

ensure that the index satisfies 0 ≤ i ≤ n. Therefore, we
introduce a predicate valid to check the legality of the index.

Def inition valid (i : nat) (n : nat) := (i >= 0) ∧ (i <= n).

Because we represent vectors using functions in Coq, it

is common to denote the i-th element of vector x as x(i),
indicating that the function x is applied to i. However, in Coq,
we can omit the parentheses and simply write it as x i.

Fig. 2. Schematic diagram of a 4-bit carry-lookahead adder Def inition p (i : nat) : bool := x i (+) y i.
Def inition g (i : nat) : bool := x i && y i.
The structural diagram of a 4-bit carry-lookahead adder is Since the vectors used in the circuit have a fixed length,
shown in Fig 3. It takes two input lists, A and B, as well as which we denote as n, the input parameters i for functions
the carry C0 from the least significant bit. The outputs consist like p and g must be within the interval [0, n]:
of a list of Si and the carry generate signals Gi and carry
propagate signals Pi , generated by each circuit structure as Lemma P : f orall i, valid i n → (p i) = (x i (+) y i).
shown in Fig 1. When combined with a carry generator, they Lemma G : f orall i, valid i n → (g i) = (x i && y i).
form the 4-bit carry-lookahead adder as depicted in Fig 3.
These two lemmas are easy to prove using the definition.
B. Formalizing Carry-Lookahead Adder in Coq The carry ci+1 = gi + pi &&ci is calculated using a recursive
The challenge in proving the correctness of a carry- function, where c 0 is equal to the input value cin:
lookahead adder in Coq lies in inductive proofs and formalised
bitwise operations. F ixpoint c (i : nat) : bool := match i with
In Coq, we define gi , pi , ci and si , where the latter | O ⇒ cin
represents the carry and sum for the ith bit. The inputs to the | S i ⇒ (g i || p i && c i) end.
adder are vectors of Boolean values, where the AND operator
∗ is implemeted by the Coq operator &&, the XOR operator Lemma c0 eq cin : c 0 = cin.
⊕ by (+) , and the OR operator + by ||. Lemma Carry : f orall i, valid i n → (c (S i))
First we introduce some variables that serve as vectors, and = (g i || p i && c i).
we specify their data types and legal ranges. In Coq, there are
various ways to model vectors. Here, we adopt a convenient These two lemmas are easy to prove using the definition.
Define the generated sum for each bit:

Def inition s (i : nat) : bool := p i (+) c i.

Lemma Sum : f orall i, valid i n → (s i) = (p i (+) c i).

There is an important property: when x and y are boolean

values, the following mathematical relationship holds: x+y =
x ∗ y ∗ 2 + x(+)y.The following is the proof process in Coq:

Lemma binary addition :

f orall x y : bool, x + y = x ∗ y ∗ 2 + x (+) y.

This lemma can be proved by using the trutht ablet actic2

Fig. 3. 4-bit carry-lookahead adder structural diagram strategy mentioned in Part II.

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 C. Proving the Carry-Lookahead Adder x, 1 ∗ x = x, x ∗ 0 = 0, 0 ∗ x = 0, x + x = 2 ∗ x,
The correctness of the carry-lookahead adder can be de- and so on. The relevant definition of the BasicArith tactic
scribed using the following mathematical formulas: in Coq is as follows:
Pk−1 i Pk−1 i Pk−1 i k
i=0 xi 2 + i=0 yi 2 + c0 = i=0 si 2 + ck 2 (1) ♯[export] Hint Rewrite
Equation (1) is expressed in Coq as follows: plus 0 l plus 0 r a plus a minus n O
mult 0 r mult 0 l mult 1 l mult 1 r : base arith.
T heorem cla correctness : f orall k, valid k n →
Ltac BasicArith := autorewrite with base arith.
sigma2 k x + sigma2 k y + c 0
= sigma2 k s + c (S k) ∗ power2 (S k). After applying the BasicArith tactic, the subgoal is sim-
plified to:
The definition in Coq is a generalisation of the mathematical
expression to indicate that it holds for all legal arguments x0 + y0 + c0 = s0 + c1 ∗ 2
k. The scope of the subscripts of the variables needs to
2) To Automate the Proof of Boolean Equations:
be checked in the reasoning used, so the valid predicate
ensures the legitimacy of the reasoning and definitions. We use rewrite valid Sum; rewrite valid Carry.
the function sigma2 to represent the summation calculation,
rewrite binary addition in | − ∗.
which achieves this through recursive computation using an
auxiliary function called sigma2 aux. Its implementation in rewrite valid P ; rewrite valid Q;
Coq is as follows: truth table tactic3 (x 0) (y 0) (c 0).
F ixpoint sigma2 aux Continuing to prove subgoal x 0 + y 0 + c 0 = s 0 + c 1 ∗
(n : nat) (f : nat → bool) (result : nat) struct n := 2.which requires the expansion of the variables s and c. We
match n with have developed a novel proof strategy named rewrite valid.
The primary function of this strategy is twofold: it conducts
| 0 ⇒ f 0 + result rewriting operations while concurrently ensuring the validity
|S i⇒ of variables within the [0, k] interval.The relevant definition
sigma2 aux i f ((f n) ∗ power2 n + result) end. of the rewrite valid tactic in Coq is as follows:
Def inition sigma2 (n : nat) (f : nat → bool) := Ltac rewrite valid eq :=
sigma2 aux n f 0. rewrite eq; [idtac|apply valid zero].
Psigma2
k i
k x is equivalent to the mathematical formula After applying the rewrite valid tactic, the subgoal is
i=0 x i 2 , power2 (S k) is equivalent to the mathematical simplified to:
formula 2n . When k=0, the equation is: x0 +y0 +c0 = s0 +2c1 .
It is possible to derive the equivalence by substituting all the x0 + y0 + c0 =
parameters in the equation with g0 , p0 , and c0 . This case can p 0 (+) c 0 + (g 0 || p 0 && c 0) ∗ 2
be easily proved.
Next are the subgoals to be proved and an analysis of the Next, the rewrite valid strategy is used to rewrite the
difficulties: arguments S 0 and c 1 of the Boolean equation as an
1) Automated Arithmetic Expression Simplification: expression containing g 0 and p 0. Then we rewrite the lemma
binary addition proved in section IV into the expression,
P roof. induction k. intro;
and then we use the rewrite valid strategy to rewrite the
unf old sigma2 in | − ∗; simpl in | − ∗. BasicArith. arguments p 0 and g 0 of the Boolean equation as an
Firstly, we generalise k, introduce multiple premises of the expression containing x 0 and y 0. The proof is completed
objective to be proved into the hypothesis by intro, expand using the truth table tactic3 strategy proved in Section II.
the sigma2 function and simplify expressions, and isolate the Next use the induction step to continue to derive the
first sub-objective to be proved: the case k = 0. conclusion that holds for all positive integers.
Various arithmetic expressions that can be simplified may When n=k, assuming Equation (1) holds:
arise during the proof. For the case of k = 0, after Coq Pk−1 i Pk−1 i Pk−1 i k
i=0 xi 2 + i=0 yi 2 + c0 = i=0 si 2 + ck 2 (2)
simplification, we obtain the subgoal:
We should proof that the equation still holds when n=k+1:
x 0 + 0 + (y 0 + 0) + c 0 = s 0 + 0 + c 1 ∗ 2
Pk i Pk i Pk i k+1
We have defined a new proof strategy called BasicArith. i=0 xi 2 + i=0 yi 2 + c0 = i=0 si 2 + ck+1 2 (3)
Its purpose is to simplify expressions using a set of arithmetic Subtracting equation (2) from equation (3) gives:
simplification rules. These simplification rules include equa-
tions such as x + 0 = x, 0 + x = x, x − 0 = x, x ∗ 1 = xk 2k + yk 2k = sk 2k + ck+1 2k+1 − ck 2k (4)

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 Further simplification gives: Applying our custom lemma sigma2 aux result to the
parameters x, y, and s yields new subgoals:
xk + yk + ck = sk + 2ck+1 (5)
x (S k) ∗ (2 ∗ power2 k) + sigma2 aux k x 0
Substituting ck+1 = gk + pk ck ,sk = pk ⊕ ck ,xk + yk = + (y (S k) ∗ (2 ∗ power2 k) + sigma2 aux k y 0)
2xk yk + xk ⊕ yk = 2gk + pk , we can see that this equation +c 0 =
holds true. At this point the case n = k + 1 is proved. The s (S k) ∗ (2 ∗ power2 k) + sigma2 aux k s 0
mathematical derivation is next verified in Coq, analysing the
+ c (S (S k)) ∗ (2 ∗ (2 ∗ power2 k))
difficulties of proof and custom proofing techniques will be
introduced. Next are the subgoals to be proved and an analysis
of the difficulties: At this stage, all the polynomial factors associated with
3) Factorisation and Simplification of Sums of Polynomials: the k=0 case have been isolated, and a new proof strategy
plusGroup is customised, which is used for the grouping cal-
culation of specific additive terms.The code for the plusGroup
strategy is as follows:
unf old sigma2 in | − ∗. simpl in | − ∗; BasicArith.
unf old sigma2 in IHk. Ltac plusGroup a := match a with
rewrite (sigma2 aux result k x), |(?y + ?z) + ?x ⇒ M vLef t plus x; plusGroup (y + z);
(sigma2 aux result k y), rewrite (f un u ⇒ plus assoc u x)
(sigma2 aux result k s)in | − ∗. |(?y + ?x) ⇒ M vLef t plus x; M vLef t plus y;
plusGroup(sigma2 aux k x 0 + sigma2 aux k y 0 + c 0). rewrite (f un u => plus assoc u x)
| ⇒ idtac end.
Handling the summation of polynomials for the case n=k
poses a particularly intricate challenge, and the ingenious
Applying the plusGroup strategy to the group of addends
application of conclusions previously established in the case
sigma2 aux k x 0 + sigma2 aux k y 0 + c 0, which
of k=0 becomes paramount. This represents the most arduous
collectively represent the initial states of the adders x0, y0,
aspect of proving the correctness of the carry-lookahead adder.
and c0, we effectively treat them as x 0 + y 0 + c 0 =
Prove the current subgoal:
s 0 + c 1 ∗ 2, a result we have previously proven when
k=0. This allows us to replace the entire group of addends
sigma2 (S k) x + sigma2 (S k) y + c 0 = in the subgoal with the established result.After applying the
sigma2 (S k) s + c (S (S k)) ∗ power2 (S (S k)) plusGroup strategy, we obtain the following new subgoal:

First, by encapsulating the sigma2 aux function within the sigma2 aux k s 0 + c (S k) ∗ power2 (S k) +
sigma2 function, with the initial accumulation value set to 0. (x (S k) ∗ (2 ∗ power2 k) + y(S k) ∗ (2 ∗ power2 k))
We then customise a new proof lemma sigma2 aux result, = s (S k) ∗ (2 ∗ power2 k)
which functions like a linear property, being able to transform
+ (sigma2 aux k s 0 + c (S (S k)) ∗ (2 ∗ (2 ∗ power2 k)))
a product of polynomials into the form of a sum of two
polynomials, and in doing so we help simplify the process of
proof by separating out the expression for the case of k=0, and 4) Identical factor elimination for Boolean equations:
thus replacing it with the conclusion we have already proved in
the previous section. The definition for sigma2 aux result RmP lusT m (sigma2 aux k s 0);
is as follows:
RmM ultT m (power2 k). RmM ultT m 2.

Lemma sigma2 aux result : f orall n f r,

In the next steps of the proof, the rewrite strategy applies
sigma2 aux n f r = r + sigma2 aux n f 0. the inductive hypothesis IHk to the current goal of the proof,
helping to change the form of the goal. The power2 S
The proof starts by expanding the sigma2 function and lemma is rewritten into the expression in order to extract the
using the BasicArith strategy to simplify the Boolean equa- common factors. The parameter c is rewritten as an expression
tion. Then we rewrite the arguments x, y, and s using the containing g and p.
sigma2 aux result lemma to split the polynomial product Eliminating completely identical factors and redundant
into several polynomial sums, Finally, all the factors for the parentheses from Boolean equations allows for further sim-
case of k = 0 are separated out from the polynomial. plification. We introduce two custom proof strategies: the

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 RmP lusT m tactic and the RmM ultT m tactic, defined in e is returned; otherwise, the original named signal is returned.
Coq as follows: The following code shows the partial definitions:
Ltac RmP lusT m a := F ixpoint subst (s : Signal) (v : string) (e : Signal) :
M vLef t plus a; apply (f equal2 plus); Signal := let st s := subst s v e in match s with
[ref lexivity | idtac]. | Bit0 ⇒ Bit0
Ltac RmM ultT m a := | Bit1 ⇒ Bit1
M vLef t mult a; | And2 r1 r2 ⇒ And2 (st r1) (st r2)
repeat(rewrite ← mult plus distr l); | Letb v e1 e2 ⇒ subst e1 v e2
apply (f equal2 mult); [ref lexivity | idtac]. | Bitv v ′ ⇒ if eqb v v ′ then e else s end.
These two tactics are used to simplify additive and multi-
plicative terms, respectively, and they simplify the proof by 3) Using Infix Operators to Represent Logical Operations:
proving that the factors on both sides are equal by shifting the
terms, expanding the operator, etc., and thus eliminating the The snippet declares a scope called Signal scope and
same factor on both sides of the equation.The subgoal after defines a series of midfix operators that are used to represent
sufficient simplification is: c (S k) + (x (S k) + y (S k)) = logical operations within that scope.These operators can be
s (S k) + 2 ∗ (g (S k) || p (S k) && c (S k)) used for symbolic representation in logical expressions, im-
The above are examples of the complexities and difficulties proving readability and expressiveness.For example:
in proving the process and some specific applications of
customised techniques. Declare Scope Signal scope. Inf ix “||” :=
Or2 (at level 50, lef t associativity) : Signal scope.
V. G ENERATING V ERILOG C ODE FROM C OQ
The steps to generate Verilog code for CLA in Coq are as B. Conversion between Signal Types and Verilog Code
follows:
1) Converts an Expression of Type Signal to the Verilog
A. Signal Vector Modeling and Parameterization String Representation:
The following code shows the partial definitions:
1) Define the Signal Type to Represent elements in Verilog:
F ixpoint gv (s : Signal) : string := match s with
Use Coq’s Inductive type to define the Signal type and
define logical operations such as and, or, different or etc.It | Bit0 ⇒ “1′ b0”
is also necessary to define Signal P air to represent signal | Bit1 ⇒ “1′ b1”
pairs for the inputs of partial and full adders. The following | Bitv v ⇒ v
code shows the partial definitions:
| N ot1 r ⇒ “ (“ + + (gv r) + + ”)”
Inductive Signal : Set := | And2 r1 r2 ⇒ “(“ + + (gv r1) + + ”)&
| And2 : Signal → Signal → Signal (“ + + (gv r2) + + ”)” end.
| Bitv : string → Signal
| Letb : string → Signal → Signal → Signal 2) Expand Each Element of the Array:
The mk names function generates a list of arrays prefixed
with Signal P air : Set :=
with the string c (the name of the array) followed by a string of
| Spair : Signal → Signal → Signal P air natural numbers with subscripts ranging from 0 to n-1. If n is
| Letb2 : string → Signal → zero, the result list is returned; if n is not zero, the mk names
Signal P air → SignalP air. function is called recursively, and the result is passed as a new
argument with n minus 1,and the new string is added to the
2) Replace Signal Patterns to Facilitate Parametric: beginning of the result list. For example, if the value of c is g
Using the recursive function subst the input signal s are re- and the value of n is 4, calling mk names g 4 [] will return
placed accordingly to their type. For Bit0 and Bit1 signals,the the list of strings [“g[0]”; “g[1]”; “g[2]”; “g[3]”].
signal itself is returned directly. For logic gates with two sub-
signals,the subst function is called recursively to replace the F ixpoint mk names (c : string) (n : nat) (result : liststring)
sub-signals.When the matched signal is a locally bound signal list string := match n with
Letb,recursively perform the substitution operation on the
O ⇒ result
bound value e1 and e2 while keeping the bound variable name
v unchanged.For named signals of type Bitv,if the naming is | Sm ⇒
the same as the signal name to be replaced, the replaced signal mk names c m ((c + +(writeN at (n − 1))) :: result) end.

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 3) Converts the Adder Output Signal Pair Into the Verilog D. Generating Verilog Code and Simulation for n-bit CLA
Assignment Statements: from Coq
The function gv adder out generates Verilog code based 1) Generate Verilog code of Carry-Lookahead Adder of Size
on the provided list of output variable names, and the output n:
signals of the adder. Initially, it combines each output variable First a variable named z is defined to represent the input
name with its corresponding adder output signal. Then, for carry. bitvc[0] creates a bit vector named c[0] which is the
each combination, it invokes the function gv assign to gener- input carry in the CLA. The mka dderi on ames function is
ate assignment statements. These statements are concatenated called next, which generates the names of the input and output
into a single string using the f lat str list function. Sub- ports of the n-bit adder. These names are bound to the tuple
sequently, the function handles the adder’s carry-out signal (ab, c), where ab is a list of the names of the adder ports and
by invoking gv assign, appending the resulting assignment c is the names of the output ports, equivalent to the gi list, the
statement to the previously generated string. This process pi list, and the ci list. Next a new variable abv is created, and
yields a complete Verilog code string. each element of the input port name list ab is converted to a
bit vector by the mk bvar2 function.
Def inition gv adder out
Next the gv adder out function is called, which generates
(out vars : list string) (ss : tpAdderOut) Verilog code based on the input port names and the output
: string := let ′ (sums, cout) := ss in let vs rounding of the CLA. The call to the f ast carry function
:= List.combine outv ars sums computes the output rounding sequence of the CLA and passes
it to the gv adder out function. gv addern function returns
in (f lat str list (List.map gv assign vs))
the output Verilog code, which is the body of the generated
+ + (gv assign (“cout”, cout)). Verilog code for the CLA of size n.
C. Calculate the Output Carry Signal Def inition gv addern (n : nat) : string :=
1) Calculate the qi Generated by each carry Generator: let z := Bitv “c[0]” in
As shown in Fig 3, the carry generation signal Gi and let ′ (ab, c) := mk adder io names n in let abv :=
the carry propagation signal Pi generated by each circuit List.map mk bvar2 ab in gv adder out c (f ast carry abv z).
structure will enter the Carry generator, and each component
will generate a carry signal. f ast qi function will calculate 2) Generating Complete Verilog Code for CLA from Coq:
the carry qi generated by each pair of input signals, and pass Use the gv module function to automatically generate the
the carry signal from right to left to the next circuit structure, remaining portion of the Verilog code. n is the number of bits
which, together with the output generated by the GP generator, of the CLA, which corresponds to the bit-width of the signal
forms a new tuple that enters the Carry generator to participate parameter when generating the Verilog code.
in the operation. The gva ddern function in combination with the gvm odule
function can be used to generate complete Verilog code (no
F ixpoint f ast qi gpl c struct gpl : more than 128 bits) for a CLA of arbitrary size. This complete
Signal := match gpl with code can be run directly in Quartus.For example the complete
Verilog code to generate a CLA of size 4 bits is as follows:
(gi, pi) :: gpl′ ⇒ gi || (pi && (f ast qi gpl′ c))
module CLA (cout, sum, a, b, cin);
| nil ⇒ c end.
output [4 : 0]sum; output cout; input [4 : 0] a, b;
2) Calculate the Final Output Carry Signal: input cin; wire [5 : 0] g, p, c;
The f astc arry function takes two arguments: the chain gpl
assign c[0] = cin; assign p = a ˆ b; assign g = a & b;
and the initial rounding signal c. First,it calls the previously
defined f ast q function to compute the sequence of output assign c[0] = c[0]; assign c[1] = (g[0]) | ((p[0]) & (c[0]));
signals of the rounding chain, which is stored in the variable assign c[2] = (g[1]) | ((p[1]) & ((g[0]) | ((p[0]) & (c[0]))));
q.Here,rev gpl is used to reverse the chain to obtain the correct assign c[3] = (g[2]) | ((p[2]) & ((g[1]) | ((p[1])
sequence of carry signal outputs.If q is the empty list,the initial
& ((g[0]) | ((p[0]) & (c[0]))))));
carry signal c is returned.The final function returns a tuple
consisting of the initial carry signal and the newly generated assign cout = (g[3]) | ((p[3]) & ((g[2]) | ((p[2])
sequence of carry output signals from the CLA. & ((g[1]) | ((p[1])& ((g[0]) | ((p[0]) & (c[0]))))))));
Def inition f ast carry gpl c : assign sum = p ˆ c[4 : 0]; endmodule
(list Signal) ∗ Signal := 3) Verilog Code Running and Simulation in Quartus:
The following shows the running and simulation of the
let q := f ast q (rev gpl) c in match q with
Verilog code for the 32-bit CLA automatically generated
hd :: tl ⇒ (rev tl, hd) from Coq in Quartus, where Fig 4 shows the generated RTL
| nil ⇒ (nil, c) end. diagram.

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 Fig. 4. RTL diagram for 32-bit carry-lookahead adder

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