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CBA Processor

Unit III covers the design and organization of processors, including instruction fetch, decode, execute, and the concept of pipelining with its advantages and hazards. It discusses the architecture of microprocessors, instruction types, and the importance of data paths and ALU design in instruction execution. Additionally, it addresses pipeline hazards, including resource, data, and control hazards, as well as the role of interrupts and exceptions in processor operation.

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3 views21 pages

CBA Processor

Unit III covers the design and organization of processors, including instruction fetch, decode, execute, and the concept of pipelining with its advantages and hazards. It discusses the architecture of microprocessors, instruction types, and the importance of data paths and ALU design in instruction execution. Additionally, it addresses pipeline hazards, including resource, data, and control hazards, as well as the role of interrupts and exceptions in processor operation.

Uploaded by

shivamgdrive158
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Unit III

Processor
Unit-III: Processor:
• Design of a Processor, Instruction fetch,
decode, execute,
• Overview of Pipelining (purpose, advantages,
disadvantages-Hazards).
• Introduction to ISA, x86 with Assembly level
examples..
• Building a data path for instruction
execution. Implementation of a simple single
cycle CPU for a given instruction.
Microprocessor
• Central component of a computer
• Is an IC that functions as a central processing unit
in a digital computer like a brain or a heart of a
human
FIRST GENERATION (1971-73) SECOND GENERATION (1974-78)
Processor Characteristics

• Machine Instruction
– Opcode (binary), Operands (src, dst), next instruction
– Operands : Main or virtual memory, registers, Immediate, I/O device
– Format : Refer to sample below
– Symbolic representation of opcodes & operands
– Instruction types: Data processing, storage, movement, control
– Number of addresses: 3-, 2-, 1- , 0- instructions
– Addressing modes:
– Types of operand : Addresses, Numbers,Characters, Logical data
PROCESSOR ORGANIZATION

Requirements placed on the processor


• Fetch Instruction,
• Decode Instruction (or Interpret)
• Fetch operand(s)
• Execute Instruction
• Store data

ALU DESIGN
DATAPATH
PIPELINING
BUILDING
DATA
PATH
Introduction

• When the CPU is to execute an instruction, the


data involved in the operation has to pass
through various functional components, such as
ALU, registers, internal buses etc
• Datapath is the series of hardware components
that perform the required operations on the data
to complete the execution of the instruction.
• Control is the hardware that tells the datapath
what to do, in terms of switching, operation
selection, data movement between ALU
components, etc
DATAPATH SIMULATION
https://www.youtube.com/watch?v=-68uCTLXKiI for
slide 31

https://www.youtube.com/watch?v=BO9epbclqxU
PIPELINING
Instruction Pipelining
• It is clear that there is some scope for optimizing
the instruction cycle thereby reducing the
execution time.
• Instruction pipelining is a way to optimize the
instruction cycle by bringing in the parallelism
wherever possible
Instruction Pipelining – cont’d

FI – Fetch Instruction
DI – Decode Instruction
CO – Calculate Operand
FO – Fetch Operand(s)
EI – Execute Instruction
WO – Write Operand

Assumptions:
Every instruction goes through all the stages
All stages are performed in parallel (No
memory conflicts)
The given pipeline diagram illustrates the effect of a conditional branch on instruction pipeline execution.
A branch instruction introduces a delay in instruction execution, commonly known as a branch penalty.

2. Causes of the Branch Penalty


Branch penalties occur when the processor encounters a conditional branch instruction (e.g., an if statement or a loop jump). The processor must:

Evaluate the branch condition (taken or not taken).


Determine the correct instruction to fetch next.
If the branch is taken, flush the incorrectly fetched instructions and load the correct ones.
This results in a pipeline stall, wasting valuable cycles.
Instruction pipelining is a powerful
technique for enhancing
performance, but requires careful
design to achieve optimum results
with reasonable complexity.
Pipeline Hazards
• A pipeline hazard occurs when the pipeline, or some portion
of the pipeline, must stall because conditions do not permit
continued execution. Such a pipeline stall is also referred to as
a pipeline bubble.
• Types of hazards: resource, data, and control

RESOURCE HAZARDS
1. main memory has a single port
2. Single ALU
Solutions:
1. Increase resources
2. Reservation Table
Resource Hazards
Data Hazard
A data hazard occurs when there is a conflict in the access of
an operand location

Types of Data Hazards


• Read after write (RAW), or true dependency
• Write after read (WAR), or antidependency
• Write after write (WAW), or output dependency
• RAW or true dependency:
– An instruction modifies a register or memory location, and
a succeeding instruction reads the data in that memory or
register location. A hazard occurs if the read takes place
before the write operation is complete.
• WAR or antidependency:
– An instruction reads a register or memory location and a
succeeding instruction writes to the location. A hazard
occurs if the write operation completes before the read
operation takes place.
• WAW or output dependency:
– Two instructions both write to the same location. A hazard
occurs if the write operations take place in the reverse
order of the intended sequence.
Data Hazards
RAW WAW

WAR
Control or Branch Hazard
• A control hazard, also known as a branch
hazard, occurs when the pipeline makes the
wrong decision on a branch prediction and
therefore brings instructions into the pipeline
that must subsequently be discarded
100: I1
101: I2
102: I3
.
.
250: BI1
Expected Output
I1 → I2 → BI1
Interrupt & Exception
• Interrupt processing within a processor is a
facility provided to support the OS.
• It allows an application program to be suspended,
in order that a variety of interrupt conditions can
be serviced and later resumed.
• Interrupts and Exceptions.
• An interrupt is generated by a signal from
hardware, and it may occur at random times
during the execution of a program.
• An exception is generated from software, and it is
provoked by the execution of an instruction.

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