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Digital Logic Systems

This document outlines the examination structure for a Bachelor of Computer Applications course on Digital Logic Systems at Pokhara University for Fall 2024. It includes various questions covering topics such as digital systems, logic design, Boolean functions, shift registers, and De Morgan's theorem. Candidates are required to provide answers in their own words and attempt all questions within a 3-hour time frame.

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0% found this document useful (0 votes)
7 views2 pages

Digital Logic Systems

This document outlines the examination structure for a Bachelor of Computer Applications course on Digital Logic Systems at Pokhara University for Fall 2024. It includes various questions covering topics such as digital systems, logic design, Boolean functions, shift registers, and De Morgan's theorem. Candidates are required to provide answers in their own words and attempt all questions within a 3-hour time frame.

Uploaded by

lalitpal091091
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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P O K H A R A U N IV E R S IT Y

Level: Bachelor Semester: Fall Year : 2024


Programme: BCA Full Marks : 100
Course: Digital Logic Systems Pass Marks : 45
Time : 3 hrs.
Candidates are required to give their answers in their own words as far
as practicable.
The figures in the margin indicate full marks.
Attempt all the questions.
1. a) Describe the digital system with the example. Design a logic system 7
whose output is HIGH whenever A and B are both HIGH as long as C
and D are either both HIGH and both LOW. Explain all your Logic.
b) Explain about the self-complementing Code? Convert the Following: 8
i. (BCA)16 = (?)2
ii. (876)6 = (?)2421
iii. (1101111)gray =(?)2
iv. (18)10 -(25)10 Perform the operation using 2’s Compliment.
2. a) Implementing the 3 input X-or and X-nor gate with NAND gate and 7
NOR gate.
b) A logic circuit that implements the following Boolean logic function 8
F=A’C+AC’D, it is found that the circuit input combination A=C=1
can never occur. Using proper K-map and don’t care condition find the
simpler expression for F and implement it using NOR gate only
assuring that the complement form of variable is not available
3. a) Design combinational circuit that converts the excess-3-code to 8421 7
conversions.
b) Derive a PLA program table for the combinational circuit that square 8
3bit input number. Minimize the number of product term.
4. a) What is the race around condition in JK flip flop? How the race around 7
condition can be overcome using master slave flip with explain with
the circuit and timing diagram?
b) Design the given sequential machine with the given state diagram 8
using RS flip flop.

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5. a) What do you mean by shift register? Explain the working of 4-bit 7
Parallel in Serial Out (PISO) shift register using the truth table and
timing diagram.
b) Design 4-bit synchronous down counter using JK flip flop which count 8
all the possible even number.
6. a) State and prove De Morgan’s theorem of 3 variable. 7
b) Explain the working of 4-bit arithmetic circuit that perform the 8
following operation.
i. Addition (A+B)
ii. Addition with Carry (A+B+1)
iii. A plus 1’s Complement of B (A +B’)
iv. Subtraction (A+B’+1)
v. Transfer A, Using B=0.
vi. Increment A (A+1), B=0
vii. Decrement A (A-1), B=1
viii. Transfer A, Using B=1
7. Write short notes on: (Any two) 2×5
a) Processor bus organization
b) Priority encoder
c) State reduction and assignment

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