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Part one: Introduction to Microprocessors

Evolution of Microprocessors (‫)التطور التاريخي للمعالجات الماكروية‬

We can categorize the microprocessor according to the generations or according to
the size of the microprocessor:
First Generation (4 - bit Microprocessors)
The first-generation microprocessors were introduced in the year 1971-1972 by
Intel Corporation. It was named Intel 4004 since it was a 4-bit microprocessor. It
was a processor on a single chip. It could perform simple arithmetic and logical
operations such as addition, subtraction, Boolean OR and Boolean AND.
I had a control unit capable of performing control functions like fetching an
instruction from storage memory, decoding it, and then generating control pulses to
execute it.

Second Generation (8 - bit Microprocessor)

The second-generation microprocessors were introduced in 1973 again by Intel.
It was a first 8-bit microprocessor which could perform arithmetic and logic
operations on 8-bit words. It was Intel 8008, and another improved version was
Intel 8088.

Third Generation (16 - bit Microprocessor)

The third-generation microprocessors, introduced in 1978 were represented by
Intel's 8086, Zilog Z800 and 80286, which were 16 - bit processors with a
performance like minicomputers.
Fourth Generation (32 - bit Microprocessors)
Several different companies introduced the 32-bit microprocessors, but the most
popular one is the Intel 80386.
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Fifth Generation (64 - bit Microprocessors)
From 1995 to now we are in the fifth generation. After 80856, Intel came out with a
new processor namely Pentium processor followed by Pentium Pro CPU, which
allows multiple CPUs in a single system to achieve multiprocessing.
Note: Other improved 64-bit processors are Celeron, Dual, Quad, Octa Core
processors.

Q: What is an 8085 Microprocessor?

Answer: It is an 8-bit microprocessor that can process, accept and send 8-bit data
simultaneously. It operates on a 3MHz clock frequency and has 16 address lines so it
has 64-kilo bytes of memory

Q: What is the 8086 microprocessors?

Answer: It is a 16-bit microprocessor having 20 address lines and 16 data lines along
with 1MB of memory storage. The processing is faster than that of the 8085
microprocessor.

Electronic and Logic Circuits

Modern devices contain two types of circuits:
Electronic circuits
The basic components of electronic circuits are transistors, resistors, capacitors, etc.
Electronic circuits operate on a wide range of voltages such as (1V, 2.1V, 3.3V,
12V) positive or negative and deal with analog signals.
Logic Circuits
The basic component of digital circuits are logic gates such as AND, OR, NAND,
NOR, XOR, XNOR, NOT... which deal with digital signals.

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Integrated Circuits (IC)
Integrated circuits consist of logic and electronic circuits built on a single small
block or chip of semiconductor that all work together to perform a specific task.
The IC is easily breakable, so to be attached to a circuit board, it is often housed in
a plastic package with metal pins.

Figure 1: Integrated circuits of Microprocessor Microprocessor

Computer's Central Processing Unit (CPU) built on a single Integrated Circuit (IC)
is called a microprocessor. A digital computer with one microprocessor which acts
as a CPU is called microcomputer. It is a programmable, multipurpose, clock-
driven, register-based electronic device that reads binary instructions from a storage
device called memory, accepts binary data as input and processes data according to
those instructions and provides results as output.

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Figure 2: Main Component of Microprocessor Central processing
unit (CPU).
The CPU supervises and controls all other computer units, transfers data to
and from these units, and performs the arithmetic and logical operations necessary to
transform data into meaningful information. It called “Processor” or
“Microprocessor” in personal computer. It is divided into three parts:
1- Arithmetic and Logic unit (ALU).
2- Control unit (CU).
3- Register.

Arithmetic and Logic unit (ALU).

Perform the processing of data including arithmetic operations such as addition,
subtraction, multiplication, division and logic operations including comparison (ex.
A<B) and sorting.

Control Unit (CU).

The control unit coordinates the operation of the entire computer system
automatically, and acts as a central nervous system that sends control signals to
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other computer units. The operations it performs are:
1- Control of input and output devices.
2- Sending and retrieving information to and from memory’s (primary and
secondary memory).
3- Routing of information between the main memory (RAM) and the arithmetic
and logic unit (ALU).
4- Direct and coordinates all units of the computer to execute program steps.
Registers
Registers are a type of computer memory used to quickly accept, store, and transfer data
and instructions that are being used immediately by the CPU. The most important
registers are:
1- Instruction Register (IR): It contains the instruction being executed.
2- Program Counter Register (PC): It contains the address of the next instruction
to be executed.
3- Address Register (AR): holds the address of memory location.
4- Data Register (DR): Holds data that is being transferred to or from memory.
5- Accumulator Register (ACC): Where intermediate arithmetic and logic results
are stored.

The basic operations performed by microprocessor

A microprocessor does three basic things.
1- Using its ALU to perform arithmetic and logical operations. Modern
microprocessors contain complete floating-point processors that can perform
extremely sophisticated operations on large floating-point numbers.
2- A microprocessor can move data from one memory location to another.
3- A microprocessor can make decisions and jump to a new set of instructions
based on those decisions.

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Instructions Fetch-Execute Cycle
The microprocessor follows the following sequence to execute instructions. 1- Initially:
the microprocessor loads the program instructions into main
memory.
2- Fetch: The microprocessor fetches those instructions from the memory.
3- Decode: Separate the operation from the operands and replace the variables with
their real values stored in main memory in preparation for execution.
4- Execute: Executes these instructions until the end of the program (until all
instructions are performed).
5- Later: it sends the result in binary to the output device.

Between these processes the register stores the temporarily data and ALU performs the
computing functions.

Figure 3: Sequence of Execute Instructions Cycle

Q: How does the CPU Fetch and execute program instructions?

1- Fetch: Fetch the instruction from memory to IR.
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 2- Change the address of Program Counter PC to the next instruction.
3- Decode: Determine the type of the instruction to be execute.
- If the instruction uses data in memory, use the address in the AR register to
fetch the data.
- Fetch the data into DR register (Data Register).
4- Execute: Execute the instruction.
5- Store the result in the ACC register or in a proper place or send it to the output
device.
6- Go to step 1 to Fetch the next instruction whose address in PC register.

Part Two : 16 Bit – 8086 Microprocessor

8086 Microprocessor is an enhanced version of 8085 Microprocessor that was

designed by Intel in 1976. This 16 Bit Microprocessor have 20-bit address lines
and16-bit data lines that provides up to 1MB storage. It consists of powerful
instruction set, which provides operations like multiplication and division easily. It
supports two modes of operation Maximum mode and Minimum mode. Maximum
mode is suitable for system having multiple processors and Minimum mode is
suitable for system having a single processor.

Features of 8086
The most prominent features of an 8086 microprocessor are as follows −
• It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
• It was the first processor having 16-bit ALU, 16-bit registers, 16-bit internal
data bus, and 16-bit external data bus resulting in faster processing.
• It is available in 3 versions based on the frequency of operation

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o 8086 → 5MHz
o 8086-2 → 8MHz
o (c)8086-1 → 10 MHz
• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
• Fetch stage can prefetch up to 6 bytes of instructions and stores them in the
queue.
• Execute stage executes these instructions.
• It has 256 vectored interrupts.
• It consists of 29,000 transistors.

Comparison between 8085 & 8086 Microprocessor

• Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.
• Address Bus − 8085 has 16-bit address bus
• while 8086 has 20-bit address bus.
• Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb
of memory.
• Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an
instruction queue.
• Pipelining − 8085 doesn’t support a pipelined architecture while 8086
supports a pipelined architecture.
• I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 =
65,536 I/O's.
• Cost − The cost of 8085 is low whereas that of 8086 is high.

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 Microprocessor 8086 - Pin Configuration

8086 was the first 16-bit microprocessor available in 40-pin Dual Inline Package (DIP)
chip. Let us now discuss in detail the pin configuration of an 8086 Microprocessor.
8086 Pin Diagram
Here is the pin diagram of 8086 microprocessors

Microprocessor
Pin

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Differentiate between minimum and maximum mode of operation of 8086
microprocessor

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 What is Timing diagram, State, Machine cycle, and Instruction Cycle: 8086
Microprocessor

Timing diagram:
Timing Diagram shows the behavior of the object(s) in a given period of time. It is
a graphical method of showing the exact output behavior of a logic circuit for
every possible set of input conditions. It is often used in digital devices to describe
the operation. Its visual characteristics are easy to understand the operation.

T-state:
One sub-division of an operation performed in one clock cycle is called a T-state.
T1, T2, T3, T4 are called states.

Machine cycle:
A group of state come together to perform one operation is called machine
cycle. The basic operation of reading/writing a byte from/to a memory location/a
port is called a machine cycle. The time taken to complete a machine cycle is
represented as Tcy. A machine cycle is made up of many states.

Instruction cycle:
The total time for fetching and executing an instruction is called instruction cycle.
An instruction cycle consists of one or more machine cycle.
In 8086, the concept of a machine cycle is not so relevant. The Execution Unit
(EU) executes instruction in certain clock periods. These clock cycles do not
constitute any form of machine cycles. The Bus Interface Unit (BIU) fetches
instructions and operands from the memory. Any external access either to the
memory or I/O device requires four clock periods.

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Bus cycle:
This group of four clock cycles is called the bus cycle. There is memory or I/O
read bus cycle; memory or I/O write bus cycle. One bus cycle consists of four
clock periods.

Control Signals Generation

8086 microprocessors do not generate the basic four control signal (IO/R, IO/W,
MEMR and MEMW) directly, but it gained them by the following signal: (RD, WR
and M/IO), through the manner bellow: As shown in figure a bubbled NAND logic
gate are used to decode the three signal which outputted from microprocessor. By De
Morgan theorem, a bubbled NAND gates is equal to OR gate, so by this logic circuit
these bubbled NAND gates can also be replaced by OR gate to generate the control
signals.

Memory/IO (M/IO). The 8086 does not output separate memory and I/O read and
write signals. Instead, the M/IO signal is output early in the T1 state and identifies
the current bus cycle as a (memory M) (M/IO = 1) or (input/output I/O) (M/ IO =
0) operation.

Read (RD). This active-low output signal indicates that the direction of data flow
on the bus is from memory or I/O into the processor. It can be combined with
M/IO to form MEMR and IOR control signals. It is output during the T2 state and
removed during the T4 state. The memory or I/O device is assumed to have placed
the addressed byte or word onto the data lines by the time RD returns high.

Write (WR). This signal is the counterpart of RD and indicates that data is to flow
from the CPU to memory or to an I/O device. In either case, the data is output
during the T2 state. This gives the memory or I/O plenty of time to latch the data
byte or word before WR is removed during
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Consider the sequence of events that occur during a memory read bus cycle.

T1. The processor outputs the 20-bit memory address. The data lines are open
circuited and all control lines disabled.
T2. The MEMR control line is driven low. The memory unit recognizes this bus
cycle as a memory read and prepares to place the addressed byte or word onto the
data lines.
T3. The microprocessor configures its data bus lines for input but takes no further
action. This
state is provided primarily to give the memory time to “look up” the data byte or word.
T4. The microprocessor now expects the data to be on the data bus lines. Therefore
it latches the contents of these lines and releases the memory read control signal.
This marks the end of the bus cycle.

The most important point to note is that the microprocessor controls all the bus
timing. The memory must be able to supply the selected data byte or word by the
time MEMR goes high during the T4 state. If it cannot do so, the CPU will read
random information on the data bus lines. This will lead to unpredictable results.

Why are there T states?

➢ In the 8086/8088, the address and data lines are multiplexed. –

➢ The microprocessor needs time to change the signals during each bus cycle.

➢ Memory devices need time to decipher the address value and then read/write the

data

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 BUS CYCLE OPERATION

Memory read in minimum mode which shown in Figure () can describe as:
During period T1,
• The 8086 outputs the 20-bit address of the memory location to be
accessed on its multiplexed address/data bus. BHE is also output along with
the address during T1.

• At the same time a pulse is also produced at ALE. The trailing edge or the
high level of this pulse is used to latch the address in external circuitry.

• Signal M/IO is set to logic 1 and signal DT/R is set to the 0 logic level
and both are maintained throughout all four periods of the bus cycle.

Beginning with period T2,

• Status bits S3 through S6 are output on the upper four address bus lines.
This status information is maintained through periods T3 and T4.

o On the other hand, address/data bus lines AD0 through AD7 are put in

the high-Z state during T2.

o Late in period T2, RD is switched to logic 0. This indicates to the

memory subsystem that a read cycle is in progress. DEN is switched to

logic 0 to enable external circuitry to allow the data to move from
memory onto the microprocessor's data bus.
During period T3,
• The memory must provide valid data during T3 and maintain it until after -
the processor terminates the read operation. The data read by the 8086
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microprocessor can be carried over all 16 data bus lines
During T4,
• The 8086 switches RD to the inactive 1 logic level to terminate the read
operation. DEN returns to its inactive logic level late during T4 to disable
the external circuitry.

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memory write cycle in minimum mode which shown in Figure () can describe as:

During period T1,

• The address along with BHE are output and latched with the ALE pulse.
• M/IO is set to logic 1 to indicate a memory cycle.
• However, this time DT/R is switched to logic 1. This signals external circuits
that the 8086 is going to transmit data over the bus.
Beginning with period T2,

• WR is switched to logic 0 telling the memory subsystem that a write operation is

to follow.
• The 8086 puts the data on the bus late in T2 and maintains the data valid
through T4. Data will be carried over all 16 data bus lines.
• DEN enables the external circuitry to provide a path for data from the
processor to the memory.
During period T3,
• The memory must receive valid data during T3 and maintain it until after -
the processor terminates the write operation. The data write by the 8086
microprocessor can be carried over all 16 data bus lines
During T4,

• The 8086 switches WR to the inactive 1 logic level to terminate the write
operation. DEN returns to its inactive logic level late during T4 to disable
the external circuitry.

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Maximum-mode Memory-Read bus-cycle of 8086 system

To complete the minimum-mode memory-read bus-cycle, the required control

signals with appropriate active logic levels are:
• IO/M = ‘logic 0’, to select memory interface
• MN/MX = ‘logic 0’, to select maximum-mode of operation
• DT/R = ‘logic 0’, to activate the data-receive mode of ‘Data-bus-buffer’
• Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
• ALE-pulse, to latch the valid Physical-address. ( )
• Proper status code S0 to S2 (as shown in table of slide 8) is generated by
• CPU to initiate data reading (MRDC) from the desired memory bank
• DEN = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass
• Reset MRDC and DEN signals to END the read-bus-cycle.

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Maximum-mode Memory-Read cycle of 8086
The timing diagram for 8086 maximum mode memory read operation is shown
below using logic ‘0’ and ‘1’ wave forms. To complete the maximum-mode
memory-write buscycle, the required control signals with appropriate active logic
levels are:
• IO/M = ‘logic 0’, to select memory interface
• MN/MX = ‘logic 0’, to select maximum-mode of operation
• DT/R = ‘logic 1’, to activate the data-transmit mode of ‘Data-bus-buffer’
• Valid Physical-address (A0 to A19) and BHE signal is generated by CPU
• ALE-pulse, to latch the valid Physical-address.
• Proper status code S0 to S2 (as shown in table of slide 8) is generated by
• CPU to initiate data writing (MRTC) from the desired memory bank
• DEN = ‘1’, enables the ‘Data-Bus-transceiver-buffer’ to let data pass

• Reset MRTC and DEN signals to END the read-bus-cycle

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8086 Microprocessor

8086 requires one phase clock with a 33% duty cycle to provide optimized internal timing.

– Range of clock:

• 5 MHz for 8086 • 8Mhz for 8086-2 • 10Mhz for 8086-1

8086 Internal Architecture

Bus Interface Unit

Sends out addresses for memory locations

Fetches Instructions from memory
Reads/Writes data to memory
Sends out addresses for I/O ports
Reads/Writes data to Input/Output ports
Execution Unit

Tells BIU (addresses) where to fetch instructions or data

Decodes & Executes instructions
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Dividing the work between BIU & EU speeds up processing
Architecture Diagram of 8086

Execution Unit

Main components are

• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose Registers
• Flag Register
• Pointer & Index registers

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Instruction Decoder
Translates instructions fetched from memory into a series of actions which EU
carries out Control System
Generates timing and control signals to perform the internal operations of the
microprocessor
Arithmetic Logic Unit
EU has a 16-bit ALU which can ADD, SUBTRACT, AND, OR, increment,
decrement,
complement or shift binary numbers

General Purpose Registers

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Flag Register:8086 has a 16-bit flag register

Contains 9 active flags

There are two types of flags in 8086
• Conditional flags – six flags, set or reset by EU on the basis of results of some
arithmetic operations
• Control flags – three flags, used to control certain operations of the processor

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 Bus Interface Unit
Main Components are
• Instruction Queue
• Segment Registers
• Instruction Pointer
Instruction Queue
8086 employs parallel processing
When EU is busy decoding or executing current instruction, the buses of 8086
may not be in use.
At that time, BIU can use buses to fetch up to six instruction bytes for the
following instructions
BIU stores these pre-fetched bytes in a FIFO register called Instruction Queue
When EU is ready for its next instruction; it simply reads the instruction from
the queue in BIU
Pipelining:EU of 8086 does not have to wait in between for BIU to fetch next
instruction byte from memory

So the presence of a queue in 8086 speeds up the processing

Fetching the next instruction while the current instruction executes is called
pipelining
Memory Segmentation
8086 has a 20-bit address bus , So it can address a maximum of 1MB of memory
8086 can work with only four 64KB segments at a time within this 1MB range
These four memory segments are called
• Code segment • Stack segment • Data segment • Extra
segment
Code Segment
That part of memory from where BIU is currently fetching instruction code bytes
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Stack Segment A section of memory set aside to store addresses and data while a
subprogram executes
 Data & Extra Segments
Used for storing data values to be used in the program.
Segment Registers
hold the upper 16-bits of the starting address for each of the segments
The four segment registers are
• CS (Code Segment register)
• DS (Data Segment register)
• SS (Stack Segment register)
• ES (Extra Segment register)
Instruction Pointer (IP) Register

a 16-bit register
Holds 16-bit offset, of the next instruction byte in the code segment
BIU uses IP and CS registers to generate the 20-bit address of the instruction to
be fetched from memory

Stack Segment (SS) Register & Stack Pointer (SP) Register

1. Upper 16-bits of the starting address of stack segment is stored in SS register

2. It is located in BIU
3. SP register holds a 16-bit offset from the start of stack segment to the top of the
stack 32
4. It is located in EU
Other Pointer & Index Registers

1. Base Pointer (BP) register 2. Source Index (SI) register

1. Destination Index (DI) register
Can be used for temporary storage of data
Main use is to hold a 16-bit offset of a data word in one of the segments
ADDRESSING MODES OF 8086

Various Addressing Modes

1. Immediate Addressing Mode 2. Register Addressing Mode

3. Direct Addressing Mode 4. Register Indirect Addressing Mode

5. Index Addressing Mode 6. Based Addressing Mode

7. Based & Indexed Addressing Mode 8. Based & Indexed with displacement Addressing

Mode 9. Strings Addressing Mode

INSTRUCTION SET of 8086

Instruction set basics:

Instruction:- An instruction is a binary pattern designed inside a microprocessor to perform

a specific function.

• Opcode:- It stands for operational code. It specifies the type of operation to be performed
by CPU. It is the first field in the machine language instruction format.

• E.g. 08 is the opcode for instruction “MOV X,Y”.

• Operand:- We can also say it as data on which operation should act. Operands may be
register values or memory values. The CPU executes the instructions using information
present in this field. It may be 8-bit data or 16-bit
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data.
Assembler:- it converts the instruction into sequence of binary bits, so that this bits can be
read by the processor.

• Mnemonics:- these are the symbolic codes for either instructions or commands to perform
a particular function.

• E.g. MOV, ADD, SUB etc.

Types of instruction set of 8086 microprocessor

(1). Data Copy/Transfer instructions. (2). Arithmetic & Logical instructions.

(3). Branch instructions. (4). Loop instructions.

(5). Machine Control instructions. (6). Flag Manipulation instructions.

(7). Shift & Rotate instructions. (8). String instructions

(1). Data copy/transfer instructions.

(1). MOV Destination, Source

There will be transfer of data from source to destination.

Source can be register, memory location or immediate data.
Destination can be register or memory operand.
Both Source and Destination cannot be memory location or segment registers at the
same time.
E.g. (1). MOV CX, 037A H; (2). MOV AL, BL; (3). MOV BX, [0301
H];

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Stack Pointer

It is a 16-bit register, contains the address of the data item currently on top of the stack.

Stack operation includes pushing (providing) data on to the stack and popping (taking)data
from the stack.

Pushing operation decrements stack pointer and Popping operation increments stack pointer.
i.e. there is a last in first out (LIFO) operation

(2). Push Source

Source can be register, segment register or memory.

This instruction pushes the contents of specified source on to the stack.

In this stack pointer is decremented by 2.

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The higher byte data is pushed first (SP-1).
 Then lower byte data is pushed (SP-2).

E.g.: (1). PUSH AX; (2). PUSH DS; (3). PUSH [5000H];

(3) POP Destination

➢ Destination can be register, segment register or memory.

➢ This instruction pops (takes) the contents of specified destination.
➢ In this stack pointer is incremented by 2.
➢ The lower byte data is popped first (SP+1).
➢ Then higher byte data is popped (SP+2).
E.g. (1). POP AX; (2). POP DS; (3). POP [5000H];

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(4). XCHG Destination, source;

• This instruction exchanges contents of Source with destination.

• It cannot exchange two memory locations directly.

•The contents of AL are exchanged with BL.

•The contents of AH are exchanged with BH.

•E.g. (1). XCHG BX, AX; (2). XCHG [5000H],AX;

(2). Arithmetic Instructions

These instructions perform the

operations like: 1. Addition, 2. Subtraction, 3. Increment,4. Decrement.

(1). ADD destination, source;

➢ This instruction adds the contents of source operand with the contents of destination
operand.
➢ The source may be immediate data, memory location or register.
➢ The destination may be memory location or register.
➢ The result is stored in destination operand.
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➢ AX is the default destination register.
 E.g. (1). ADD AX,2020H; (2). ADD AX,BX;
SHL Instruction

The SHL (shift left) instruction performs a logical left shift on the destination operand,
filling the lowest bit with 0.

SHR Instruction

✓ The SHR (shift right) instruction performs a logical right shift on the destination
operand. The highest bit position is filled with a zero.

SAR Instruction

SAR (shift arithmetic right) performs a right arithmetic shift on the destination operand.

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Shifting left n bits multiplies the operand by 2n.

For example, 5 * 22 = 20

Shifting right n bits divides the operand by 2n

For example, 80 / 23 = 10

ROL Instruction

✓ ROL (rotate) shifts each bit to the left

✓ The highest bit is copied into both the Carry flag and into the lowest bit
✓ No bits are lost

ROR Instruction
✓ ROR (rotate right) shifts each bit to the right
✓ The lowest bit is copied into both the Carry flag and into the highest bit
✓ No bits are lost

RCL Instruction
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✓ RCL (rotate carry left) shifts each bit to the left
 ✓ Copies the Carry flag to the least significant bit
✓ Copies the most significant bit to the Carry flag

RCR Instruction

✓ RCR (rotate carry right) shifts each bit to the right

✓ Copies the Carry flag to the most significant bit
✓ Copies the least significant bit to the Carry flag

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