TERM PAPER LEADING TO THESIS REPORT

ON
“PROGRAMMABLE LOGIC DEVICE”

A Thesis Submitted to
Bhagalpur College of Engineering
For The Award of the Degree Of
MASTER OF TECHNOLOGY
in
MICROELECTRONICS & VLSI TECHNOLOGY

Under the Department of

Electronics & Communication Engineering
Submitted
By
BHAVANA KUMARI
Roll no.22MECE17
Registration no.-22141108016

Department of Electronics & Communication Engineering

Bhagalpur College of Engineering, Bhagalpur

Affiliated ToAryabhatta Knowledge University, Patna

JANUARY 2024
 CERTIFICATE

This is to certify that the thesis titled, “PROGRAMMABLE

LOGIC DEVICE” submitted in partial fulfillment of the
requirements for the award of degree of Master of Technology
in “Microelectronics and VLSI Technology” of Bhagalpur
College of Engineering, affiliated to Aryabhatta Knowledge
University, Patna, is an authentic record of the work carried out
by me at Bhagalpur College of Engineering, Bhagalpur.

The matter presented in this thesis has not been submitted to

any other University/Institute for the award of any degree.

Date:

BHAVANA KUMARI
Registration No.: 22141108016
 ABSTRACT
I have discussed about the development of programmable logic
devices, the programming techniques. Programmable logic
arrays (PLAs) are traditional digital electronic devices. A PLA
is a simple programmable logic device (SPLD) used to
implement combinational logic circuits. A PLA has a set of
programmable AND gates, which link to a set of programmable
OR gates to produce an output. The AND–OR layout of a PLA
allows for implementing logic functions that are in a sum-of-
products form. PLAs are available in the market in different
types. PLAs could be stand alone chips, or parts of bigger
processingsystem
 CONTENTS
1. INTRODUCTION................................................................................... 5
2. STRUCTURE OF PLD ............................................................................. 6

2.1 PROM…………………………………………………………………………………………….7
2.2 PAL………………………………………………………………………………………………..8
2.3 PLA………………………………………………………………………………………………..8
 1. INTRODUCTION
A programmable logic device is defined as an integrated circuit that
contains an array of logic elements and interconnections that can be
programmed by the user to implement a desired logic function. The logic
elements are usually simple combinational or sequential circuits, such as
AND, OR, NOT, and XOR gates, or registers. The interconnections are
usually programmable switches or multiplexers that can connect the
inputs and outputs of the logic elements in different. The programming
of a PLD can be done using a hardware description language (HDL),
such as Verilog or VHDL, or a graphical user interface (GUI) software
tool. The programming code or file is then downloaded to the PLD using
a special device programmer or a standard interface, such as JTAG or
USB. The programming code or file determines how the logic elements
and interconnections are configured to perform the desired logic
function.
 STRUCTURE OF PLD
 Inputs to the PLD are applied to a set of buffer/inverters. These devices
have both the true value of the input as well as the complemented value of
the input as its outputs.
 Outputs from these devices are the inputs to an array of and-gates. The
AND array generates a set of p product terms.
 The product terms are inputs to an array of or-gates to realize a set of m
sum-of-product expressions.
  There are three kinds of PLDs based on the type of arrays
, which has programmable feature.

1. Programmable Read Only Memory

2. Programmable Array Logic
3. Programmable Logic Array

Programmable Read Only Memory PROM

Read Only Memory ROM is a memory device, which stores the binary information permanently. That means,
we can’t change that stored information by any means later. If the ROM has programmable feature, then it is
called as Programmable ROM PROM. The user has the flexibility to program the binary information
electrically once by using PROM programmer. PROM is a programmable logic device that has fixed AND array
& Programmable OR array. The block diagram of PROM is shown in the following figure.

Example
Let us implement the following Boolean functions using PROM.
A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each
function is having three variables X, Y & Z. So, we require a 3 to 8
decoder and two programmable OR gates for producing these two
functions. The corresponding PROM is shown in the following figure.
 Programmable Array Logic PAL
PAL is a programmable logic device that has Programmable AND array & fixed OR
array. The advantage of PAL is that we can generate only the required product terms
of Boolean function instead of generating all the min terms by using programmable
AND gates. The block diagram of PAL is shown in the following figure.
Here, the inputs of AND gates are programmable. That means each AND gate has both
normal and complemented inputs of variables. So, based on the requirement, we can
program any of those inputs. So, we can generate only the required product terms by
using these AND gates.

Programmable Logic Array PLA

PLA is a programmable logic device that has both Programmable AND
array & Programmable OR array. Hence, it is the most flexible PLD. The
block diagram of PLA is shown in the following figure .
Here, the inputs of AND gates are programmable. That means each
AND gate has both normal and complemented inputs of variables. So,
based on the requirement, we can program any of those inputs. So, we
can generate only the required product terms by using these AND
gates. Here, the inputs of OR gates are also programmable. So, we can
program any number of required product terms, since all the outputs of
AND gates are applied as inputs to each OR gate. Therefore, the
outputs of PAL will be in the form of sum of products form.

A=XY+XZ′

B=XY′+YZ+XZ′
 CONCLUSION
Programmable logic devices are electronic components that can be
configured to perform specific logic functions by the user. They
offer flexibility, speed, cost-effectiveness, performance, and rapid
prototyping advantages over fixed logic devices. They are widely
used in digital systems design for various applications. They come
in different types depending on their complexity, architecture, and
programmability, such as SPLDs, CPLDs, and FPGAs. They are
programmed using hardware description languages or graphical
user interface software tools. They have revolutionized the field of
digital electronics and opened new possibilities for innovation and
creativity.
 REFERENCES
1. D. Chen, J. Cong, M. D. Ercegovac, and Z. Huang, Performance-driven
mapping for CPLD architectures. Proc. ACM/SIGDA Symposium on Field
Programmable Gate Arrays, 39–47, 2001.
2. F. Vahid et al., Embedded System Design: A Unified Hardware/Software
Introduction, New York: John Wiley & Sons, 2002.
3. R.W. Ward and T.C.A. Molteno, A CPLD coprocessor for embedded
cryptography, Proc. Electronics New Zealand Conf. 2003.
4. R. Garg, M. Sanchez, K. Gulati, N. Jayakumar, A. Gupta, and S. P. Khatri, A
design flow to optimize circuit delay by using standard cells and PLAs. Proc.
ACM Great Lakes Symposium on VLSI, 217–222, 2006
5. DOI:10.1002/9780470050118.ecse316 In book: Wiley Encyclopedia of
Computer Science and Engineering 2008.