GMR Institute of Technology

GMRIT/ADM/F-44
Rajam, AP REV.: 00
(An Autonomous Institution Affiliated to JNTUGV, AP)

Cohesive Teaching – Learning Practices (CTLP)

Class 4th Sem. – B. Tech Department: CSE/AIML/AIDS

Course Computer Organization and Architecture Course Code 21CS403
Prepared by Dr. K. Srividya, Ms. Santhoshini Sahu, Mrs. A Vineela, Mrs. A Bhavani, Mr. B. M.
Sreenivasa Rao
Lecture Topic Instructions codes, Computer register instructions, Memory & Register Reference
instructions, Input and output Reference instructions, Instruction’s cycle,
Addressing modes
Course Outcome (s) CO1, CO2 Program Outcome (s) PO1, PO12
Duration 50 Min Lecture 7-12 Unit I
Pre-requisite (s) Micro operations

1. Objective

❖ Understand Instruction codes.

❖ Understand the types of instructions.
❖ Understand the instruction cycle.
❖ Understand the addressing modes.

2. Intended Learning Outcomes (ILOs)

At the end of this session the students will be able to:

1. Summarize the format of instruction code.

2. Understand the types of instruction codes.
3. Understand the working of instruction cycle.
4. Summarize the usage and types of addressing modes.

3. 2D Mapping of ILOs with Knowledge Dimension and Cognitive Learning Levels of RBT

Cognitive Learning Levels

Knowledge
Remember Understand Apply Analyse Evaluate Create
Dimension
Factual
Conceptual A,B, C
Procedural
Meta Cognitive

4. Teaching Methodology

❖ Power Point Presentation, Chalk Talk, visual presentation

5. Evocation
6. Deliverables

Lecture -1: Instructions codes

The internal organization of a digital system is defined by the sequence of microoperations it performs
on data stored in its registers. The general-purpose digital computer is capable of executing various
microoperations and, in addition., can be instructed as to what specific sequence of operations it must
perform. The user of a computer can control the process by means of a program. A program is a set
of instructions that specify the operations, operands, and the sequence by which processing has to
occur. The data processing task may be altered by specifying a new program with different
instructions or specifying the same instructions with different data.

A computer instruction is a binary code that specifies a sequence of microoperations for the computer.
Instruction codes together with data are stored in memory. The computer reads each instruction from
memory and places it in a control register. The control then interprets the binary code of the
instruction and proceeds to execute it by issuing a sequence of microoperations. Every computer has
its own unique instruction set. The ability to store and execute instructions, the stored program
concept, is the most important property of a general-purpose computer.

An instruction code is a group of bits that instruct the computer to perform a specific operation. It is
usually divided into parts, each having its own particular interpretation. The most basic part of an
instruction code is its operation part. The operation code of an instruction is a group of bits that define
such operations as add, subtract, multiply, shift, and complement. The number of bits required for the
operation code of an instruction depends on the total number of operations available in the computer.
The operation code must consist of at least n bits for a given 2n (or less) distinct operations. As an
illustration, consider a computer with 64 distinct operations, one of them being an ADD operation.
The operation code consists of six bits, with a bit configuration 110010 assigned to the ADD
operation. When this operation code is decoded in the control unit, the computer issues control signals
to read an operand from memory and add the operand to a processor register. At this point we must
recognize the relationship between a computer operation and a microoperation.

An operation is part of an instruction stored in computer memory. It is a binary code that tells the
computer to perform a specific operation. The control unit receives the instruction from memory and
interprets the operation code bits. It then issues a sequence of control signals to initiate
microoperations in internal computer registers. For every operation code, the control issues a
sequence of microoperations needed for the hardware implementation of the specified operation. For
this reason, an operation code is sometimes called a macrooperation because it specifies a set of
microoperations. The operation part of an instruction code specifies the operation to be performed.
This operation must be performed on some data stored in processor registers or in memory. An
instruction code must therefore specify not only the operation but also the registers or the memory
words where the operands are to be found, as well as the register or memory word where the result is
to be stored. Memory words can be specified in instruction codes by their address. Processor registers
can be specified by assigning to the instruction another binary code of k bits that specifies one of 2n
registers. There are many variations for arranging the binary code of instructions, and each computer
has its own particular instruction code format. Instruction code formats are conceived by computer
designers who specify the architecture of the computer.

Stored Program Organization

The simplest way to organize a computer is to have one processor register and an instruction code
format with two parts. The first part specifies the operation to be performed and the second specifies
an address. The memory address tells the control where to find an operand in memory. This operand
is read from memory and used as the data to be operated on together with the data stored in the
processor register.

In the above figure, Instructions are stored in one section of memory and data in another. For a
memory unit with 4096 words we need 12 bits to specify an address since 212 = 4096. If we store each
instruction code in one 16-bit memory word, we have available four bits for the operation code
(abbreviated opcode) to specify one out of 16 possible operations, and 12 bits to specify the address
of an operand. The control reads a 16-bit instruction from the program portion of memory. It uses the
12-bit address part of the instruction to read a 16-bit operand from the data portion of memory. It then
executes the operation specified by the operation code.

Computers that have a single-processor register usually assign to it the name accumulator and label
it AC. The operation is performed with the memory operand and the content of AC. If an operation
in an instruction code does not need an operand from memory, the rest of the bits in the instruction
can be used for other purposes. For example, operations such as clear AC, complement AC, and
increment AC operate on data stored in the AC register. They do not need an operand from memory.
For these types of operations, the second part of the instruction code (bits 0 through 11) is not needed
for specifying a memory address and can be used to specify other operations for the computer.
Indirect Address

It is sometimes convenient to use the address bits of an instruction code not as an address but as the
actual operand. When the second part of an instruction code specifies an operand, the instruction is
said to have an immediate operand. When the second part specifies the address of an operand, the
instruction is said to have a direct address. This is in contrast to a third possibility called indirect
address, where the bits in the second part of the instruction designate an address of a memory word
in which the address of the operand is found. One bit of the instruction code can be used to distinguish
between a direct and an indirect address. As an illustration of this configuration, consider the
instruction code format shown in figure above. It consists of a 3-bit operation code, a 12-bit address,
and an indirect address mode bit designated by I. The mode bit is 0 for a direct address and 1 for an
indirect address. A direct address instruction is shown in Figure (b). It is placed in address 22 in
memory. The I bit is 0, so the instruction is recognized as a direct address instruction. The opcode
specifies an ADD instruction, and the address part is the binary equivalent of 457. The control finds
the operand in memory at address 457 and adds it to the content of AC. The instruction in address 35
shown in Figure(c) has a mode bit I = 1. Therefore, it is recognized as an indirect address instruction.
The address part is the binary equivalent of 300. The control goes to address 300 to find the address
of the operand. The address of the operand in this case is 1350. The operand found in address 1350
is then added to the content of AC. The indirect address instruction needs two references to memory
to fetch an operand. The first reference is needed to read the address of the operand; the second is for
the operand itself. We define the effective address to be the address of the operand in a computation-
type instruction or the target address in a branch-type instruction. Thus the effective address in the
instruction of Figure(b) is 457 and in the instruction of Figure(c) is 1350. The direct and indirect
addressing modes are used in the computer presented in this chapter. The memory word that holds
the address of the operand in an indirect address instruction is used as a pointer to an array of data.
The pointer could be placed in a processor register instead of memory as done in commercial
computers.

Lecture -8: Computer register instructions

Computer registers are high-speed memory storing units. It is an element of the computer processor.
It can carry any type of information including a bit sequence or single data. A register should be 32
bits in length for a 32-bit instruction computer. Registers can be numbered relies upon the processor
design and language rules. The instructions in a computer are saved in memory locations and
implemented one after another at a time. The function of the control unit is to fetch the instruction
from the memory and implement it. The control does the similar for all the instructions in the memory
in sequential order. A counter is needed to maintain a path of the next instruction to be implemented
and evaluate its address. The figure shows the registers with their memories. The memory addresses
are saved in multiple registers. These requirements certainly state the use for registers in a computer.

The following table shows the registers and their functions.

The description for each of the registers determined in the figure is as follows −

• The data register holds the operand read from the memory.
• The accumulator is a general-purpose register need for processing.
• The instruction register holds the read memory.
• The temporary data used while processing is stored in the temporary register.
• The address register holds the address of the instruction that is to be implemented next from
the memory.
• The Program Counter (PC) controls the sequence of instructions to be read. In case a branch
instruction is detected, the sequential execution does not arise. A branch execution calls for a
transfer to an instruction that is not in sequence with the instructions in the PC.
• The input register (INPR) and output register (OUTPR) are the registers used for the I/O
operations. The INPR receives an 8-bit character from the input device. It is similar to the
OUTPR.

Common Bus System

There are multiple registers and their functions which are as follows −

• Load (LD) − During the next clock pulse transition the information from the bus is
transmitted to the register whose load (LD) input is enabled.
• Memory Unit − When the write input of the memory is activated, it holds the content
of the bus. When the read input is activated, the memory places the 16-bit output onto
the bus with the selection variables being S2S1 S0 = 111.
• Increment (INR) and Clear (CLR) − When the INR signal is enabled, the contents
of the specified register are incremented. The contents are cleared when the CLR signal
is enabled.
• Address Registers (AR) − The address of the memory for the next read and write
operation is determined. It receives or sends an address from or to the bus when
selection inputs S2S1 S0=001 is used and the load is enabled. With inputs INR and CLR,
the address gets incremented or cleared.
• Program Counter (PC) − The address of the next instruction that is to be read from
the memory is saved. It receives or sends an address from or to the bus when selection
inputs S2S1 S0 = 010is applied and the load input is enabled. With inputs INR and CLR,
the address gets incremented or cleared.
• Data Register (DR) − The data register includes the data to be written into memory
or data that is to be read from the memory. It receives or sends an address from or to
the bus when selection inputs are S2S1 S0 = 011 applied and the load input is enabled.
With inputs INR and CLR, the address gets incremented or cleared.
• Accumulator (AC) − Accumulators are beneficial in executing the register micro-
operations including complement, shift, etc. The results acquired are again sent to the
accumulator. An accumulator stores the intermediate arithmetic and logic results.
• Instruction Registers (IR) − The IR stores the copy of the instruction that the
processor has to implement. The instruction that is read from the memory is stored in
 the IR. It receives or sends instruction code from or to the bus when selection inputs
S2S1 S0 = 111 are applied and the load input is enabled.
• Temporary Register (TR) − The temporary storage for variables or results is
supported by the temporary register. It receives or sends the temporary data from or to
the bus when selection inputs S2S1 S0 = 011 are applied and the load input is enabled.
With inputs INR and CLR, the address gets incremented or cleared.
• Input Registers (INPR) − It includes 8 bits to hold the alphanumeric input
information. Input device shifts its serial data into the 8-bit register. The data is moved
to AC via the adder/logic circuit with load enabled.
• Output Registers (OUTPR) − The data is received from AC and moved to the output
device.

The basic computer has eight registers, a memory unit, and a control unit. Paths must be provided to
transfer information from one register to another and between memory and registers. The number of
wires will be excessive if connections are made between the outputs of each register and the inputs
of the other registers. A more efficient scheme for transferring information in a system with many
registers is to use a common bus. The connection of the registers and memory of the basic computer
to a common bus system is shown in the above figure. The outputs of seven registers and memory
are connected to the common bus. The specific output that is selected for the bus lines at any given
time is determined from the binary value of the selection variables S2, S1, and S0. The number along
each output shows the decimal equivalent of the required binary selection. For example, the number
along the output of DR is 3. The 16-bit outputs of DR are placed on the bus lines when S2S1S0 = 011
since this is the binary value of decimal 3. The lines from the common bus are connected to the inputs
of each register and the data inputs of the memory. The particular register whose LD (load) input is
enabled receives the data from the bus during the next clock pulse transition. The memory receives
the contents of the bus when its write input is activated. The memory places its 16-bit output onto the
bus when the read input is activated and S2S1S0 = 111. Four registers, D R , AC, IR, and TR, have 16
bits each. Two registers, AR and PC, have 1 2 bits each since they hold a memory address. When the
contents of AR or PC are applied to the 16-bit common bus, the four most significant bits are set to
O's. When AR or PC receive information from the bus, only the 12 least significant bits are transferred
into the register. The input register INPR and the output register OUTR have 8 bits each and
communicate with the eight least significant bits in the bus. INPR is connected to provide information
to the bus but OUTR can only receive information from the bus. This is because INPR receives a
character from an input device which is then transferred to AC . OUTR receives a character from AC
and delivers it to an output device. There is no transfer from OUTR to any of the other registers.

The 16 lines of the common bus receive information from six registers and the memory unit. The bus
lines are connected to the inputs of six registers and the memory. Five registers have three control
inputs: LD (load), INR (increment), and CLR (clear). This type of register is equivalent to a binary
counter with parallel load and synchronous clear. The increment operation is achieved by enabling
the count input of the counter. Two registers have only a LD input. The input data and output data of
the memory are connected to the common bus, but the memory address is connected to AR.
Therefore, AR must always be used to specify a memory address. By using a single register for the
address, we eliminate the need for an address bus that would have been needed otherwise. The content
of any register can be specified for the memory data input during a write operation. Similarly, any
register can receive the data from memory after a read operation except AC. The 16 inputs of AC
come from an adder and logic circuit. This circuit has three sets of inputs. One set of 16-bit inputs
come from the outputs of AC. They are used to implement register microoperations such as
complement AC and shift AC. Another set of 16-bit inputs come from the data register DR. The
inputs from DR and AC are used for arithmetic and logic microoperations, such as add DR to AC or
AND DR to AC. The result of an addition is transferred to AC and the end carry-out of the addition
is transferred to flip-flop E (extended AC bit). A third set of 8-bit inputs come from the input register
INPR. Note that the content of any register can be applied onto the bus and an operation can be
performed in the adder and logic circuit during the same clock cycle. The clock transition at the end
of the cycle transfers the content of the bus into the designated destination register and the output of
the adder and logic circuit into AC. For example, the two microoperations

DR →AC and AC →DR

can be executed at the same time. This can be done by placing the content of AC on the bus (with
525150 = 100), enabling the LD (load) input of DR, transferring the content of DR through the adder
and logic circuit into AC, and enabling the LD (load) input of AC, all during the same clock cycle.
The two transfers occur upon the arrival of the clock pulse transition at the end of the clock cycle.

Lecture -9: Memory & Register Reference instructions

The basic computer has 16-bit instruction register (IR) which can denote either memory reference or
register reference or input-output instruction.
 • Memory Reference – These instructions refer to memory address as an operand. The other
operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than 111) and 1-
bit addressing mode for direct and indirect addressing.

Example –

IR register contains = 0001XXXXXXXXXXXX, i.e. ADD after fetching and decoding of instruction
we find out that it is a memory reference instruction for ADD operation.

Hence, DR ← M[AR]

AC ← AC + DR, SC ← 0

• Register Reference – These instructions perform operations on registers rather than memory
addresses. The IR(14 – 12) is 111 (differentiates it from memory reference) and IR(15) is 0
(differentiates it from input/output instructions). The rest 12 bits specify register operation.

Example –

IR register contains = 0111001000000000, i.e. CMA after fetch and decode cycle we find out that it
is a register reference instruction for complement accumulator.

Hence, AC ← ~AC

• Input/Output – These instructions are for communication between computer and outside
environment. The IR(14 – 12) is 111 (differentiates it from memory reference) and IR(15) is
1 (differentiates it from register reference instructions). The rest 12 bits specify I/O operation.

Memory Reference instructions:

Memory reference instructions are those commands or instructions which are in the custom to
generate a reference to the memory and approval to a program to have an approach to the commanded
information and that states as to from where the data is cache continually. These instructions are
known as Memory Reference Instructions.

There are seven memory reference instructions which are as follows &
AND

The AND instruction implements the AND logic operation on the bit collection from the register and
the memory word that is determined by the effective address. The result of this operation is moved
back to the register.

ADD

The ADD instruction adds the content of the memory word that is denoted by the effective address
to the value of the register.

LDA

The LDA instruction shares the memory word denoted by the effective address to the register.

STA

STA saves the content of the register into the memory word that is defined by the effective address.
The output is next used to the common bus and the data input is linked to the bus. It needed only one
micro-operation.

BUN

The Branch Unconditionally (BUN) instruction can send the instruction that is determined by the
effective address. They understand that the address of the next instruction to be performed is held by
the PC and it should be incremented by one to receive the address of the next instruction in the
sequence. If the control needs to implement multiple instructions that are not next in the sequence, it
can execute the BUN instruction.
BSA

BSA stands for Branch and Save return Address. These instructions can branch a part of the program
(known as subroutine or procedure). When this instruction is performed, BSA will store the address
of the next instruction from the PC into a memory location that is determined by the effective address.

ISZ

The Increment if Zero (ISZ) instruction increments the word determined by effective address. If the
incremented cost is zero, thus PC is incremented by 1. A negative value is saved in the memory word
through the programmer. It can influence the zero value after getting incremented repeatedly. Thus,
the PC is incremented and the next instruction is skipped.

Register Reference Instructions:

Register-reference instructions are recognized by the control when 07 = 1 and I = 0. These instructions
use bits 0 through 11 of the instruction code to specify one of 12 instructions. These 12 bits are
available in IR(0-11). They were also transferred to AR during time T2. These instructions are
executed with the clock transition associated with timing variable T3. Each control function needs
the Boolean relation D7I'T3, which we designate for convenience by the symbol r. The control
function is distinguished by one of the bits in IR(0-11). By assigning the symbol B, to bit i of IR, all
control functions can be simply denoted by rB. For example, the instruction CLA has the hexadecimal
code 7800, which gives the binary equivalent 011I 1000 0000 0000. The first bit is a zero and is
equivalent to I'. The next three bits constitute the operation code and are recognized from decoder
output D7. Bit 11 in IR is I and is recognized from 811. The control function that initiates the
rnicrooperation for this instruction is D7I'T3B11 = rB11. The execution of a register-reference
instruction is completed at time T3. The sequence counter SC is cleared to 0 and the control goes
back to fetch the next instruction with timing signal T0.

The first seven register-reference instructions perform clear, complement, circular shift, and
increment rnicrooperations on the AC or E registers. The next four instructions cause a skip of the
next instruction in sequence when a stated condition is satisfied. The skipping of the instruction is
achieved by incrementing PC once again (in addition, it is being incremented during the fetch phase
at time T1). The condition control statements must be recognized as part of the control conditions.
The AC is positive when the sign bit in AC(IS) = 0; it is negative when AC(IS) = I. The content of
AC is zero (AC = 0) if all the flip-flops of the register are zero. The HLT instruction clears a start-
stop flip-flop S and stops the sequence counter from counting. To restore the operation of the
computer, the start-stop flip-flop must be set manually.

Lecture -10: Input-Output Reference Instructions:

Just like the Register-reference instruction, an Input-Output instruction does not need a reference to
memory and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction.
The remaining 12 bits are used to specify the type of the input-output operation or test performed.
Note
The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise, the
instruction is a memory-reference type, and the bit in position 15 is taken as the addressing mode I.
When the three operation code bits are equal to 111, control unit inspects the bit in position 15. If the
bit is 0, the instruction is a register-reference type. Otherwise, the instruction is an input-output type
having bit 1 at position 15.

Lecture -11: Instructions cycle:

Registers Involved In Each Instruction Cycle:
Memory address registers(MAR) : It is connected to the address lines of the system bus. It specifies
the address in memory for a read or write operation.
Memory Buffer Register(MBR) : It is connected to the data lines of the system bus. It contains the
value to be stored in memory or the last value read from the memory.
Program Counter(PC) : Holds the address of the next instruction to be fetched.
Instruction Register(IR) : Holds the last instruction fetched.
The Instruction Cycle –
Each phase of Instruction Cycle can be decomposed into a sequence of elementary micro-operations.
In the above examples, there is one sequence each for the Fetch, Indirect, Execute and Interrupt
Cycles.

Each instruction cycle in turn is subdivided into a sequence of subcycles or phases. In the basic
computer each instruction cycle consists of the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next
instruction. This process continues indefinitely unless a HALT instruction is encountered.
Fetch and Decode
Initially, the program counter PC is loaded with the address of the first instruction in the program.
The sequence counter SC is cleared to 0, providing a decoded timing signal To. After each clock
pulse, SC is incremented by one, so that the timing signals go through a sequence T0, T1, T2, and so
on. The microoperations for the fetch and decode phases can be specified by the following register
transfer statements.
Since only AR is connected to the address inputs of memory, it is necessary to transfer the address
from PC to AR during the clock transition associated with timing signal T0. The instruction read from
memory is then placed in the instruction register IR with the clock transition associated with timing
signal T1. At the same time, PC is incremented by one to prepare it for the address of the next
instruction in the program. At time T2, the operation code in IR is decoded, the indirect bit is
transferred to flip-flop I, and the address part of the instruction is transferred to AR. Note that SC is
incremented after each clock pulse to produce the sequence To, T1, and T2.
To provide the data path for the transfer of PC to AR we must apply timing signal T0 to achieve the
following connection:
1. Place the content of PC onto the bus by making the bus selection inputs S2S1 S0 equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR. The next clock transition
initiates the transfer from PC to AR since T0 = 1.
In order to implement the second statement
T1: IR M[AR], PC  PC + 1
it is necessary to use timing signal T1 to provide the following connections in the bus system.
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making S2S1 S0 = 111.
3. Transfer the content of the bus to IR by enabling the LD input of IR .
4. Increment PC by enabling the INR input of PC. The next clock transition initiates the read and
increment operations since T1 = 1.
Lecture -12: Addressing Modes

The operation field of an instruction specifies the operation to be performed. This operation will be
executed on some data which is stored in computer registers or the main memory. The way any
operand is selected during the program execution is dependent on the addressing mode of the
instruction. The purpose of using addressing modes is as follows:
To give the programming versatility to the user.
To reduce the number of bits in addressing field of instruction.
➢ Types of Addressing Modes
Below we have discussed different types of addressing modes one by one:
➢ Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction has an
operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.
➢ Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The instruction
has the address of the Register where the operand is stored.

➢ Register Indirect Mode

In this mode, the instruction specifies the register whose contents give us the address of operand
which is in memory. Thus, the register contains the address of operand rather than the operand itself.
➢ Direct Addressing Mode
 ➢ Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.
In this mode, effective address of operand is present in instruction itself.
Single memory reference to access data.
No additional calculations to find the effective address of the operand.

For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
➢ Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored in
memory. This slows down the execution, as this includes multiple memory lookups to find the
operand.

➢ Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to obtain
the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and R(that
holds the displacement), or vice versa.
 ➢ Relative Addressing Mode

It is a version of Displacement addressing mode.

In this the contents of PC(Program Counter) is added to address part of instruction to obtain the
effective address.
EA = A + (PC), where EA is effective address and PC is program counter.
The operand is A cells away from the current cell(the one pointed to by PC)
➢ Base Register Addressing Mode

It is again a version of Displacement addressing mode. This can be defined as EA = A + (R),

where A is displacement and R holds pointer to base address.
➢ Stack Addressing Mode

In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top two
items from the stack, add them, and will then PUSH the result to the top of the stack.
The two-word instruction at address 200 and 201 is a "load to AC" instruction with an address field
equal to 500. The first word of the instruction specifies the operation code and mode, and the second
word specifies the address part. PC has the value 200 for fetching this instruction. The content of
processor register R 1 is 400, and the content of an index register XR is 100. AC receives the operand
after the instruction is executed. The figure lists a few pertinent addresses and shows the memory
content at each of these addresses. The mode field of the instruction can specify any one of a number
of modes. For each possible mode we calculate the effective address and the operand that must be
loaded into AC . In the direct address mode the effective address is the address part of the instruction
500 and the operand to be loaded into AC is 800. In the immediate mode the second word of the
instruction is taken as the operand rather than an address, so 500 is loaded into AC . (The effective
address in this case is 201 . ) In the indirect mode the effective address is stored in memory at address
500. Therefore, the effective address is 800 and the operand is 300. In the relative mode the effective
address is 500 + 202 = 702 and the operand is 325. (Note that the value in PC after the fetch phase
and during the execute phase is 202.) In the index mode the effective address is XR + 500 = 100 +
500 = 600 and the operand is 900. In the register mode the operand is in R 1 and 400 is loaded into
AC . (There is no effective address in this case. ) In the register indirect mode the effective address is
400, equal to the content of R 1 and the operand loaded into AC is 700. The autoincrement mode is
the same as the register indirect mode except that R 1 is incremented to 401 after the execution of the
instruction. The autodecrement mode decrements R1 to 399 prior to the execution of the instruction.
The operand loaded into AC is now 450. The table below lists the values of the effective address and
the operand loaded into AC for the nine addressing modes.
7. Keywords

❖ Instruction cycle.
❖ Memory reference instructions
❖ Register reference instruction
❖ Input-output reference instructions
❖ Addressing modes

8. Sample Questions

Remember:

1. Define instruction code.

2. List the memory reference instructions.
3. What is instruction?
4. Draw the instruction cycle.
5. List the addressing modes.

Understand

1. Explain the different instruction codes.

2. Explain the reference instructions with example.
3. Explain the instruction cycle in detail.
4. Explain the different addressing modes.

9. Stimulating Question (s)

1. -

10. Mind Map

11. Student Summary

 At the end of this session, the facilitator (Teacher) shall randomly pick-up few students to
summarize the deliverables.

12. Reading Materials

13. Scope for Mini Project

NIL ---------------