GMR Institute of Technology

GMRIT/ADM/F-44
Rajam, AP REV.: 00
(An Autonomous Institution Affiliated to JNTUGV, AP)

Cohesive Teaching – Learning Practices (CTLP)

Class 4th Sem. – B. Tech Department: CSE/AIML/AIDS

Course Computer Organization and Architecture Course Code 21CS403
Prepared by Dr. K. Srividya, Ms. Santhoshini Sahu, Mrs. A Vineela, Mrs. A Bhavani, Mr. B. M.
Sreenivasa Rao
Lecture Topic ALU, addition and subtraction with signed magnitude data, Hardware
implementation, Multiplication, Hardware implementation, Division, Hardware
implementation, Divide overflow
Course Outcome (s) CO3 Program Outcome (s) PO1, PO12
Duration 50 Min Lecture 13-19 Unit II
Pre-requisite (s) Micro operations

1. Objective

❖ Understand fixed point arithmetic operations.

2. Intended Learning Outcomes (ILOs)

At the end of this session the students will be able to:

1. Summarize the arithmetic operations for fixed point representation.

3. 2D Mapping of ILOs with Knowledge Dimension and Cognitive Learning Levels of RBT

Cognitive Learning Levels

Knowledge
Remember Understand Apply Analyse Evaluate Create
Dimension
Factual
Conceptual A,B, C
Procedural
Meta Cognitive

4. Teaching Methodology

❖ Power Point Presentation, Chalk Talk, visual presentation

5. Evocation

6. Deliverables

Lecture -13: ALU, addition and subtraction with signed magnitude data
The The Arithmetic Logic Unit (ALU) is a component in the central processing unit (CPU) of a
computer that performs arithmetic and logical operations on binary data. It includes circuits for
addition, subtraction, multiplication, division, and other mathematical operations.

When it comes to addition and subtraction with signed magnitude data, the following steps are taken:

Addition:

• Determine the sign of the operands by looking at the most significant bit (MSB).
• If the signs of the operands are the same, perform binary addition on the magnitudes and use
the common sign for the result.
• If the signs are different, perform binary subtraction on the magnitudes of the larger number
minus the smaller number, and use the sign of the larger number for the result.

As display in the table, the addition algorithm states that −

• When the signs of P and Q are equal, add the two magnitudes and connect the sign of P to the
output.
• When the signs of P and Q are different, compare the magnitudes and subtract the smaller
number from the greater number.
• The signs of the output have to be equal as P in case P > Q or the complement of the sign of
P in case P < Q.
• When the two magnitudes are equal, subtract Q from P and modify the sign of the output to
positive.

For example, to add -7 and 3 in signed magnitude representation:

• The sign bit of -7 is 1, and the magnitude is 0111.

• The sign bit of 3 is 0, and the magnitude is 0011.
• Since the signs are different, we perform binary subtraction: 0111 - 0011 = 0100.
• The sign of the result is the sign of the larger number, which is -7.
• Therefore, the result is -4 in signed magnitude representation.

Subtraction:
 • Determine the sign of the operands by looking at the MSB.
• If the signs of the operands are different, perform binary addition on the magnitudes of the
larger number plus the magnitude of the negative of the smaller number, and use the sign of
the larger number for the result.
• If the signs are the same, perform binary subtraction on the magnitudes of the larger number
minus the magnitude of the smaller number, and use the sign of the first operand for the result.

The subtraction algorithm states that −

• When the signs of P and Q are different, add the two magnitudes and connect the signs of P
to the output.
• When the signs of P and Q are the same, compare the magnitudes and subtract the smaller
number from the greater number.
• The signs of the output have to be equal as P in case P > Q or the complement of the sign of
P in case P < Q.
• When the two magnitudes are equal, subtract Q from P and modify the sign of the output to
positive.

For example, to subtract -7 from 3 in signed magnitude representation:

• The sign bit of 3 is 0, and the magnitude is 0011.

• The sign bit of -7 is 1, and the magnitude is 0111.
• Since the signs are different, we perform binary addition: 0111 + 0011 = 1010.
• The sign of the result is the sign of the larger number, which is -7.
• Therefore, the result is -10 in signed magnitude representation.

Lecture -14: Hardware implementation

The two signs As and Bs are compared by an exclusive-OR gate For an add operation, identical signs
dictate that the magnitudes be added, for subtract operation different signs dictate that the magnitudes
be added. The magnitudes are added with a micro operation EAA+B.. Where E A is a register that
combines E and A . For A 0 indicates that A<B, for this case it is necessary to take the 2’s compliment
of the value in A .this operation can be done with one micro operation A Ā+1.
However , we assume that A register as circuits for micro operation compliment and increment, so
the 2’s compliment is obtain from these two micro operation. The value in AVF provides an overflow
indication. The final value of E is immaterial.

The left most bit of binary number represents the sign bit; 0 for positive and 1 for negative. If the sign
bit is 1, the entire the entire number is represented in 2’s compliment form. The addition of two
numbers in signed-2’s complement form consists of adding the number with the sign bits treated the
same as the other bits of the number. A carry out of the sign bit position is discarded. The subtraction
consists of first taking the 2’s compliment of the subtrahend and then adding it to the minuend When
two numbers of n digits each are added and the sum occupies n+1 Digits, we say that an overflow
occurred. When the two carries are applied to an exclusive-OR gate, the overflow is detected when
the output of the gate is equal to 1.
Step 1: The sign bits of A and B that are As and Bs respectively are compared with XOR gate. If
output is 0 then signs are identical and if 1 the signs are different.
Step 2: For add operation identical signs means magnitude will get add and different signs means
magnitude will get subtract.
For subtraction operation identical signs means magnitude will get subtract and different signs means
magnitude will get add
Step 3: For addition operation the addition of A and B is stored at register A and carry in E. The
carry in E after the addition is transferred to add overflow flip flop AVF.
EA ← A+B
AVF ← E
For subtraction operation the 2’s complement of A is taken and then addition of A and B is stored at
register EA.
EA ← A+B+1
AVF=0
Step 4: If E=0 then indicates that B ≤ A and for correct result 1’s complement of A is required. If
result obtaining after 1’s complement of A is all 0 then sign bit As should be positive to avoid
negative 0.
If E=1 then indicates that B>A then complement of result in A and complement of sign As is required
for correct result

Lecture -15: Multiplication

• Multiplication of two fixed point binary numbers in signed magnitude representation is done
with process of successive shift and add operation.
• In the multiplication process we are
considering successive bits of the
multiplier, least significant bit first.
• If the multiplier bit is 1, the multiplicand
is copied down else 0’s is copied down.
• The numbers copied down in successive
lines are shifted one position to the left
from the previous number.
• Finally, numbers are added and their sum
form the product.
• The sign of the product is determined
from the sign of the multiplicand and
multiplier. If they are alike, sign of the
product is positive else negative.
Lecture -16: Hardware implementation:

• Registers: Two Registers B and Q are used to store multiplicand and multiplier respectively.
Register A is used to store partial product during multiplication.
Sequence Counter register (SC) is used to store number of bits in the multiplier.
• Flip Flop: To store sign bit of registers we require three flip flops (A sign, B sign and Q sign).
Flip flop E is used to store carry bit generated during partial product addition.
• Complement and Parallel adder: This hardware unit is used in calculating partial product
i.e., perform addition required.

Initially, the multiplicand is in B and the multiplier in Q. Their corresponding signs are in B, and
Q., respectively. The signs are compared, and both A and Q are set to correspond to the sign of the
product since a double-length product will be stored in registers A and Q. Registers A and E are
cleared and the sequence counter SC is set to a number equal to the number of bits of the multiplier.
We are assuming here that operands are transferred to registers from a memory unit that has words
 of n bits. Since an operand must be stored with its sign, one bit of the word will be occupied by the
sign and the magnitude will consist of n - 1 bits.
After the initialization, the low-order bit of the multiplier in Q, is tested. If it is a 1, the multiplicand
in B is added to the present partial product in A. If it is a 0, nothing is done. Register EAQ is then
shifted once to the right to form the new partial product The sequence counter is decremented by 1
and its new value checked. If it is not equal to zero, the process is repeated and a new partial product
is formed. The process stops when SC = 0. Note that the partial product formed in A is shifted into
Q one bit at a time and eventually replaces the multiplier. The final product is available in both A
and Q, with A holding the most significant bits and Q holding the least significant bits.

Booth Multiplication Algorithm:

Booth's multiplication algorithm is a technique used for multiplying two binary numbers together. It
is a bit manipulation algorithm that is particularly useful for large numbers. The algorithm works by
converting the two binary numbers to a signed representation using two's complement notation. This
signed representation allows for the use of negative numbers, which simplifies the multiplication
process.
Once the numbers are converted, the algorithm performs a series of steps to calculate the product.
These steps involve shifting the numbers and adding or subtracting them based on the values of
adjacent bits.
Here are the steps of the Booth's multiplication algorithm:
1. Convert the two binary numbers to their signed representation using two's complement
notation.
2. Create a new binary number that is twice the length of the original numbers, with an extra bit
set to 0 at the beginning. This will be the product.
3. Starting from the rightmost bit of the product, scan left to right, comparing adjacent pairs of
bits in the multiplier. If the pair is "01", add the multiplicand to the product. If the pair is "10",
subtract the multiplicand from the product. If the pair is "00" or "11", no operation is necessary.
4. Shift the multiplier one bit to the right, and shift the product one bit to the left.
5. Repeat steps 3 and 4 until the multiplier is zero.
6. The final product is the result of the multiplication.

Booth's multiplication algorithm is particularly useful for large numbers because it reduces the
number of operations needed to calculate the product. This can lead to faster calculation times
compared to other multiplication algorithms.
Lecture -17: Division:

Division of two fixed-point binary numbers in signed-magnitude representation is done with paper
and pencil by a process of successive compare, shift, and subtract operations. Binary division is
simpler than decimal division because the quotient digits are either 0 or 1 and there is no need to
estimate how many times the dividend or partial remainder fits into the divisor. The divisor B consists
of five bits and the dividend A, of ten bits. The five most significant bits of the dividend are compared
with the divisor. Since the 5-bit number is smaller than B, we try again by taking the six most
significant bits of A and compare this number with B. The 6-bit number is greater than B, so we place
a 1 for the quotient bit in the sixth position above the dividend. The divisor is then shifted once to the
right and subtracted from the dividend.
The difference is called a partial remainder because the division could have stopped here to obtain a
quotient of 1 and a remainder equal to the partial remainder. The process is continued by comparing
a partial remainder with the divisor. If the partial remainder is greater than or equal to the divisor, the
quotient bit is equal to 1 . The divisor is then shifted right and subtracted from the partial remainder.
If the partial remainder is smaller than the divisor, the quotient bit is 0 and no subtraction is needed.
The divisor is shifted once to the right in any case. Note that the result gives both a quotient and a
remainder.

Lecture -18: Hardware implementation of division algorithm

Register EAQ is now shifted to the left with 0 inserted into Q, and the previous value of E lost. The
divisor is stored in the B register and the double-length dividend is stored in registers A and Q. The
dividend is shifted to the left and the divisor is subtracted by adding its 2' s complement value. The
information about the relative magnitude is available in E. If E = 1, it signifies that A>=B. A quotient
bit 1 is inserted into Q, and the partial remainder is shifted to the left to repeat the process. If E = 0,
it signifies that A < B so the quotient in Q, remains a 0 (inserted during the shift). The value of B is
then added to restore the partial remainder in A to its previous value. The partial remainder is shifted
to the left and the process is repeated again until all five quotient bits are formed. Note that while the
partial remainder is shifted left, the quotient bits are shifted also and after five shifts, the quotient is
in Q and the final remainder is in A.

The dividend is in A and Q and the divisor in B. The sign of the result is transferred into Q, to be part
of the quotient. A constant is set into the sequence counter SC to specify the number of bits in the
quotient. As in multiplication, we assume that operands are transferred to registers from a memory
unit that has words o f n bits. Since a n operand must be stored with its sign, one bit of the word will
be occupied by the sign and the magnitude will consist of n - 1 bits.
A divide-overflow condition is tested by subtracting the divisor in B from half of the bits of the
dividend stored in A. If A >= B, the divide-overflow flip-flop DVF is set and the operation is
terminated prematurely. If A < B, no divide overflow occurs so the value of the dividend is restored
by adding B to A.
The division of the magnitudes starts by shifting the dividend in A Q to the left with the high-order
bit shifted into E. If the bit shifted into E is 1, we know that EA > B because EA consists of a 1
followed by n - 1 bits while B consists of only n -1 bits. In this case, B must be subtracted from EA
and 1 inserted into Q, for the quotient bit. Since register A is missing the high-order bit of the dividend
(which is in E), its value is EA – 2n-1. Adding to this value the 2' s complement of B results. The
carry from this addition is not transferred to E if we want E to remain a l.
If the shift-left operation inserts a 0 into E, the divisor is subtracted by adding its 2's complement
value and the carry is transferred into E. If E = 1, it signifies that A>=B; therefore, Q, is set to 1. If E
= 0, it signifies that A < B and the original number is restored by adding B to A. In the latter case we
leave a 0 in Q, (0 was inserted during the shift). This process is repeated again with register A holding
the partial remainder.
After n - 1 times, the quotient magnitude is formed in register Q and the remainder is found in register
A. The quotient sign is in Q, and the sign of the remainder in A, is the same as the original sign of the
dividend.

Lecture -19: Divide overflow:

The division operation may result in a quotient with an overflow. This is not a problem when working
with paper and pencil but is critical when the operation is implemented with hardware. This is because
the length of registers is finite and will not hold a number that exceeds the standard length. To see
this, consider a system that has 5-bit registers. We use one register to hold the divisor and two registers
to hold the dividend. From the example, we note that the quotient will consist of six bits if the five
most significant bits of the dividend constitute a number greater than the divisor. The quotient is to
be stored in a standard 5-bit register, so the overflow bit will require one more flip-flop for storing
the sixth bit. This divide-overflow condition must be avoided in normal computer operations because
the entire quotient will be too long for transfer into a memory unit that has words of standard length,
that is, the same as the length of registers. Provisions to ensure that this condition is detected must be
included in either the hardware or the software of the computer, or in a combination of the two. When
the dividend is twice as long as the divisor, the condition for overflow can be stated as follows: A
divide-overflow condition occurs if the high-order half bits of the dividend constitute a number
greater than or equal to the divisor. Another problem associated with division is the fact that a division
by zero must be avoided. The divide-overflow condition takes care of this condition as well. This
occurs because any dividend will be greater than or equal to a divisor which is equal to zero. Overflow
condition is usually detected when a special flip-flop is set. We will call it a divide-overflow flip-flop
and label it DVF.
The occurrence of a divide overflow can be handled in a variety of ways. In some computers it is the
responsibility of the programmers to check if DVF is set after each divide instruction. They then can
branch to a subroutine that takes a corrective measure such as rescaling the data to avoid overflow.
In some older computers, the occurrence of a divide overflow stopped the computer and this condition
was referred to as a divide stop. Stopping the operation of the computer is not recommended because
it is time consuming. The procedure in most computers is to provide an interrupt request when DVF
is set.
The interrupt causes the computer to suspend the current program and branch to a service routine to
take a corrective measure. The most common corrective measure is to remove the program and type
an error message explaining the reason why the program could not be completed. It is then the
responsibility of the user who wrote the program to rescale the data or take any other corrective
measure.
Keywords

❖ Fixed point representation.

❖ Floating point representation

7. Sample Questions

Remember:

1. Define overflow.
2. Draw flowchart of floating point division.
3. Draw flowchart of booth multiplication algorithm.
 Understand

1. Explain Booth’s algorithm for multiplication of signed 2’complement numbers.

2. Explain in detail about the hardware implementation of addition and subtraction
algorithm with neat diagram
3. Perform floating-point addition using the numbers 0.5 and 0.4375 use the floating
point addition algorithm.

8. Stimulating Question (s)

1. -

9. Mind Map

11. Student Summary

At the end of this session, the facilitator (Teacher) shall randomly pick-up few students to
summarize the deliverables.

12. Reading Materials

13. Scope for Mini Project

NIL ---------------