Chinese Journal of Electronics

Vol.31, No.1, Jan. 2022

A 2 Kbits Low Power EEPROM for

Passive RFID Tag IC
HU Jianguo1, WANG Deming2, and WU Jing3
(1. School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai 519082, China)
(2. School of Physics and Telecommunication Engineering, South China Normal University, Guangzhou 510006, China)
(3. Development Research Institute of Guangzhou Smart City, Guangzhou 510800, China)

Abstract — This paper presents a low power con- However, the increasing number of hardware circuits
sumption and low cost electrically erasable program-
brings great challenges to the power supply capability
mable read-only memory (EEPROM) for radio frequency
of passive tag chip. In order to effectively reduce the
identification (RFID) tag chip. A read-write circuit with
parallel input and serial output is proposed. Only one power consumption of tag chip, it is necessary to carry
sensitive amplifier is used to read the data in memory, out low-power research.
which can effectively reduce the power consumption of RFID tag chip is composed of RF analog circuit,
the read operation. Because the tag may be read or writ- baseband protocol processing circuit and nonvolatile
ten while moving, the internal voltage may change in a
memory, among which RF analog circuit and baseband
wide range. Therefore, this paper designs a charge pump
and its control circuit with wide voltage working range.
protocol processing circuit have been reported in many
The proposed EEPROM is integrated into an RFID tag literatures. Therefore, this paper will focus on the low-
chip and fabricated using a 180 nm complementary met- power research of nonvolatile memory. Nonvolatile
al-oxide semiconductor (CMOS) process. Experimental memory mainly includes electrically erasable program-
results show that the circuit can work in the input mable read-only memory (EEPROM)[8], flash, FeRAM,
voltage range of 1 V to 1.8 V, and the minimum current
RRAM, PRAM and MRAM. Flash memory is widely
of read operation and write operation is 0.68 μA and 30 μA
respectively, which has the characteristic of low power used in ultra large capacity storage because of its high-
consumption. speed block erasure and efficient programming features,
Key words — EEPROM, RFID, Low power, Very but rarely used in byte erasure or bit erasure occasion.
large scale integration (VLSI).
For small capacity and applications that need to write
by bit or byte, especially in the field of payment, EEP-
ROM memory with high reliability and stability is
mainly used. Other memories have problems of compat-
I. Introduction ibility and reliability, and few processes can be realized,
Due to the characteristics of contactless and multi- so it is difficult to use them in tag IC.
target identification, radio frequency identification EEPROM is programmed and erased by Fowler
(RFID) tag chip has been widely used in the fields of Nordheim tunneling effect. Programming refers to in-
identity authentication, mobile payment, supply chain, jecting electrons into the floating gate and erasing refers
inventory management, production control and asset to discharging the stored electrons in the floating gate.
management. With the development of very large scale Compared with other memories, EEPROM can select-
integration (VLSI), Internet of things and information ively erase or program, which has greater flexibility, less
security technology, the integration of RFID techno- energy consumption, high reliability and durability, so
logy with implantable biomedical[1,2], electrochemical it is widely used in passive RFID tag chip. In order to
sensor[3−5] and on-chip security[6,7] has emerged. ensure the long-term reliability of the storage cell and

Manuscript Received Jan. 24, 2021; Accepted Feb. 7, 2021. This work was supported by the Key-Area Research and Development
Program of Guangdong Province (2019B010142002, 2019B010153001), Guangdong Basic and Applied Basic Research Foundation (2019B
1515120025), and the 2016 Guangzhou Innovation and Entrepreneurship Leader Team (CXLJTD-201608).
© 2022 Chinese Institute of Electronics. DOI:10.1049/cje.2021.00.044
 A 2 Kbits Low Power EEPROM for Passive RFID Tag IC 19

prevent the tunnel oxide from being broken down by EEPROM, the existing method uses at least 8-bit paral-
high voltage, the peak electric field on the tunnel oxide lel output, so the internal circuit has at least 8 parallel
should be limited. Therefore, the programming voltage sensitive amplifiers, which consumes a lot of power. In
should rise slowly and keep it for a long time. The com- order to reduce the reading power consumption, the
mon method is to use the low-frequency clock to drive parallel output is changed to serial output, only one bit
the charge pump to convert the low-voltage into the is read at a time, and only one sensitive amplifier is
high-voltage required by the programming step by step, needed, which can greatly reduce the power consump-
which makes it difficult to reduce the power consump- tion when reading EEPROM. In addition, the tradition-
tion of this part of the circuit. In order to solve this al EEPROM is generally integrated with a bandgap ref-
problem, Ref.[9] proposed a 768 bits EEPROM memory erence, which consumes a lot of power. In order to re-
for RFID tags. By designing an energy-efficient charge duce the power consumption, we can use the existing
pump and its control circuit, the programming voltage bandgap reference in the RF analog circuit to further
can be effectively controlled below 12 V to achieve low reduce the power consumption.
erasing power consumption. Ref.[10] has realized a Fig.1 shows the circuit architecture of the pro-
1 Kbits EEPROM memory. In order to further reduce posed EEPROM for passive RFID tag IC. RFID tag
the power consumption, the read operation voltage is chip is composed of RF analog circuit, digital control
reduced to 1 V, and the write operation still maintains circuit and EEPROM memory. The RF analog circuit
a high voltage. By designing a time-sharing drive charge includes rectifier, limiter, ask demodulator, load modu-
pump, the power consumption is effectively controlled lation, LDO power generation, clock and reset circuit,
at about 1 μ A, which is better applied to UHF RFID which provides clock, reset, demodulation signal, power
tag chip. In the aspect of large capacity storage, Ref.[11] supply and other signals for digital circuit and EEP-
proposed an EEPROM memory with a capacity of 200 ROM memory. The digital circuit includes encoder, de-
Kbytes, which adopts a more advanced 90 nm process coder, CRC, anti-collision and state machine control
and realizes ultra-high speed during reading operation, circuit, which provides a series of interface signals for
and effectively controls the power consumption and EEPROM, including: 11-bit address bus (EEAD), 8-bit
area of the circuit. In addition, in order to obtain large- input data bus (EEDBI), programming mode enable
scale application, Refs.[12−14] continue to explore the signal (EEMOD), program enable (PROGRAM), erase
reliability and durability of EEPROM memory, and put enable signal (WRITE), the clock signal (EECLK), read
forward a series of design and test methods to improve enable signal (EEREAD), data input or output syn-
the yield. chronization signal (DATASYN) and output data bus
In conclusion, the research on EEPROM has made (EEDBO).
good progress. However, with the rapid development of As shown in Fig.1 , the EEPROM memory pro-
semiconductor technology, storage capacity has shown a posed in this paper consists of memory array, decoder
growing trend in recent years. The larger the storage and driver circuit, read-write control, charge pump, buf-
capacity is, the larger the area and power consumption fer and sensitive amplifier. The memory is 2048 bits in
are, which increases the power supply pressure of the total, which is divided into 64 blocks with 4 bytes in
chip to a certain extent. In order to effectively reduce each block. The decoder and driver circuit can convert
the power consumption of tag chip, it is necessary to the input address signal into row selection signal and
carry out low-power research. column selection signal, which can be used to select the
The rest of this paper is organized as follows. Sec- byte or bit storage unit corresponding to the address.
tion II describes the architecture of the proposed EEP- The read control circuit will generate enable signal and
ROM for RFID tag IC. Section III presents the de- synchronization signal during read operation, such as
tailed design of low power circuit for read and write. EEREAD enable signal and DATASYN synchroniza-
Section IV shows a series of measure results with fur- tion signal. The write operation control circuit is used
ther analyzation and discussion, followed by a conclu- to generate programming and erasing control signals,
sion in Section V. such as EEMOD, EECLK, PROGRAM, ERASE and
WRITE signals. Because EEPROM needs to complete
II. Circuit Architecture the programming and erasing operation under high
After the RFID tag chip completes the operation of voltage, a charge pump and its control circuit are
writing EEPROM memory, most of the remaining oper- needed to generate a stable voltage of about 15.5 V.
ations are to obtain the information stored in the tag. The sense amplifier is used for read operation to distin-
Therefore, we pay more attention to the power con- guish whether the information in the storage unit is lo-
sumption of read operation. In the process of reading gic 1 or logic 0.
20 Chinese Journal of Electronics 2022

EEPROM
VDD
Rectifier LDO EEDBO
Charge Buffer Sense
Vref
PAD VHD Decod ERASE EECLK pump amplifier
WRITE PROGRAM EEREAD
Reset encodee
Rst Read/Write control
Limiter EEDBI [7:0]
State machine DATASYN
Antenna

Clock control
Clk Byte 0 Byte 1 Byte 2 Byte 3 Block 0

Decoder & driver

ASK Anticollision VDD Byte 0 Byte 1 Byte 2 Byte 3 Block 1
DEMOD Data CRC

…
Memory array
PAD Ant1 Ant2 EEAD[10:0]

…
Byte 0 Byte 1 Byte 2 Byte 3 Block 62
Load Dout
Digital control Byte 0 Byte 1 Byte 2 Byte 3 Block 63
MOD

Fig. 1. Circuit architecture of the proposed EEPROM for passive RFID tag IC

III. Proposed EEPROM Circuit reference source is not less than 10 μ A, and this cur-
rent is always present during the whole reading opera-
1. Read circuit
tion, so it cannot be used in low-power read circuit. In
In order to read out the logic information stored in order to control the reading power at about 1 μA, this
bit cell accurately, a read circuit based on current de- paper uses a reading circuit based on threshold voltage
tection mechanism can be used. This method requires a detection mechanism. This method does not need to use
stable bandgap reference circuit and a high gain sensit- reference source and operational amplifier, which effect-
ive amplifier. In order to obtain excellent anti-noise per- ively reduces the area and power consumption of the
formance, it is necessary to design a high-precision read circuit.
bandgap reference circuit, so that the output voltage is As shown in Fig.2, the bit cell of EEPROM is com-
not affected by temperature, process and power supply posed of NSG and NCG. NCG has two storage states,
voltage. The reference source is mainly composed of ref- which are defined as NCGPA and NCGEA respectively.
erence current, mirror circuit and regulating circuit. The threshold voltage of NCGPA is relatively low, only
Due to the existence of several current paths from the −0.63 V. When NCG is in NCGPA state, the informa-
power supply to the ground, the power consumption is tion stored in the bit cell can be defined as logical “0”.
generally large, and it is difficult to balance the area, The threshold voltage of NCGEA is relatively high,
power consumption and stability. In order to ensure which is 4.84 V. When NCG is in NCGEA state, the in-
sufficient anti-interference capability, the current of the formation stored in the bit cell can be defined as logic “1”.

VDD
NDSI
PM1 PM3
EERD
EEDBO

PM2 NM1 EERAD

CG SG
BL Path 2 DSI
BL
NCG NSG EERAD DATASYN
NM2 DSI
NDSI
NM3 Bit cell Path 1 I
EERAD ...
...

CG SG
Layout of the bit cell
BL Area: 2.88 μm2
NCG NSG Layout: one block, 4 bytes, 32 bits
Bit cell

Fig. 2. Low power read circuit based on threshold voltage detection mechanism

In the read circuit, PM1 and PM2 are two PMOS gate of PM1 is controlled by an enable signal (EERD).
transistors in series with the bit cell of EEPROM. The The enabling signal is generated by EEREAD and
 A 2 Kbits Low Power EEPROM for Passive RFID Tag IC 21

DATASYN, which determines whether the path is on consumption of path 1. In addition, the inverter com-
or not. The main function of PM2 is to increase the im- posed of PM3 and NM1 (path 2) has large transient
pedance of the path and reduce the static power con- power consumption. A bias voltage can be applied to
sumption when reading EEPROM. When a bit cell is the substrate of the inverter, that is, adding an NM2
selected by address, EEREAD is high level (VDD: 1– transistor to change the threshold voltage of PMOS and
1.8 V), PM1 and NM3 transistors are on. At the same NMOS transistors, so as to reduce the short-circuit cur-
time, SG and CG will be set to high level (VDD), and rent of the inverter and reduce the power consumption
NSG will be on. At this time, whether the current of path 2.
branch shown by the dotted line is on or not depends 2. Charge pump
on the state of NCG. When NCG is in NCGPA state, The input voltage of most charge pump circuits is
the path is on. Since the impedance of PM2 is much fixed, so there is no need to add complex control cir-
greater than that of other transistors in the path, the cuit. RFID tag chip can complete reading and writing
voltage of BL is close to 0. When NCG is in NCGEA in the process of movement, which will lead to signific-
state, NCG is not conducting, and the voltage of BL ant changes in field strength and coupling coefficient,
will be pulled to high level (VDD). After the BL signal and the induced voltage will also change in a wide
is processed by inverter, driving circuit and shaping cir- range. The output voltage of LDO in the chip can be
cuit, the logic information stored in the bit cell will be stable at 1.8 V at high field strength. With the in-
output. crease of distance, the coupling energy decays rapidly,
Fig.3 shows the timing of the read circuit and the and the output voltage of LDO can be as low as 1 V.
power consumption during EEPROM read operation. It Because the input voltage of the charge pump fluctu-
can be seen that only when EEREAD and DATASYN ates in a large range, if it is not controlled, the output
signals are at high level at the same time, the circuit voltage will be too small to reach the high voltage value
will start to work. The read circuit only operates the bit required for erasing EEPROM, which will lead to wrong
cell corresponding to the address signal EEAD and erasure. If the output voltage of the charge pump is too
reads only 1 bit information each time. If logic 1 is high, the long-term reliability of the device will also be
stored, BL signal will be pulled low, and logic 1 will be affected.
output in EEDBO after subsequent circuit processing. Fig.4 shows the charge pump and its control cir-
55 μ 60 μ 65 μ 70 μ cuit. The Dickson charge pump structure is used to
7.1 n 1m
800 μ
generate the high voltage signal for erasure. After the
600 μ Current
400 μ filter capacitor is used to stabilize the voltage, the VHH
200 μ

1 1.0 is divided. The traditional method uses diodes com-

0.8
0.6
0.4
EEREAD posed of MOS transistors to divide the voltage, which
0.2
0 can effectively improve the response speed of the
1 1.0
0.8
0.6
voltage divider circuit, accelerate the charging and dis-
0.4 DATASYN charging of the capacitor, and reduce the voltage jitter.
0.2
0
1 1.0
0.8
But this method consumes a lot of power and is not
0.6
0.4
REN suitable for RIFD tag chip. Because the voltage needed
0.2

431 μ
0
1.2 for EEPROM erasure is not too accurate, and can toler-
1.0
0.8 BL ate large ripple, this paper proposes to use capacitive
0.6
0.4
0.2
0 voltage divider, although the response speed is low, but
1.0
1 0.8 it can effectively reduce the power consumption of
0.6
0.4
0.2 charge pump. VP as shown in Fig.4 is used as one of
0
55 μ 60 μ 65 μ 70.3 μ the inputs of the comparator to compare with the refer-
ence voltage Vref. If the output voltage of the charge
Fig. 3. Timing of read circuit and power consumption of pump exceeds VHH, the clock signal CLK required for
EEPROM
charging and discharging is turned off, and the pump-
During the operation of the read circuit, only one ing voltage is stopped; if the voltage is lower than
branch has a large static current (path 1). In order to VHH, the clock is turned on and charging is started, so
reduce the power consumption during the read opera- that the voltage is dynamically stabilized at VHH. Be-
tion, we can increase the on impedance of path 1. When cause the designed EEPROM will eventually be ap-
path 1 is on, BL should be at low level. Therefore, the plied to the RFID tag chip, and the RF analog circuit
channel length L of PM1 and PM2 should be increased of the tag has bandgap and LDO, the use of the voltage
to increase the branch impedance and reduce the power reference can be reduced in the EEPROM, and the area
22 Chinese Journal of Electronics 2022

and power consumption can be further reduced through half a cycle to raise the voltage, the other half of the
circuit reused. cycle will fall back, which will cause jitter and intro-
duce additional noise. In order to eliminate the influ-
ence of the noise, this paper uses two mutually reverse
K
Charge VHH clocks (CLK and CLK_ INV) to charge and discharge
Comparator
CLK
pump the two branches at the same time. In the last stage,
CP2 VP
CP1 + two branches are connected together to solve the jitter
CP3 − problem. The final output voltage of the circuit is de-
Vref termined by VIN and series. When the series is fixed,
Fig. 4. Charge pump and its control circuit the change of VIN will change the output value VHH.
Because VIN is not fixed in some applications, it will
Fig.5 shows the charge pump circuit proposed in
change in a wide voltage range. For example, the LDO
this paper, in which the discharge signal can force the
output of RFID tag can be from 1 V to 1.8 V. At this
lower plate (Uc+) of the capacitor to be connected to
point, if you want to get the performance that the VHH
the VDD, so that the charge pump does not work. The
value remains unchanged no matter how VIN changes,
boost process of charge pump can be completed in two
you need to add a charge pump control circuit.
stages. In the first stage, CLK is at low level, MN1 is
turned on, MP1 is turned off, and the input signal IV. Simulation and Measured Results
(VIN) will charge the capacitor C1:
The proposed 2 Kbits EEPROM memory is integ-
Uc+ − Uc− = UC1 = V IN (1) rated into a high frequency passive RFID tag chip (the
tag supports ISO/IEC 15693 protocol). The chip is fab-
1st stage 2nd stage nth stage ricated and verified in a 180 nm 2P6M EEPROM pro-
−
Cn −
Uc− CLK
Uc+ C1 C2 + +
cess. Fig.6 shows the layout of EEPROM, RFID tag
chip and test platform. It can be seen that the whole
VIN ……
MN1 MP1
VDD MN2 MP2 VDD MNn MPn
VDD EEPROM occupies a chip area of 470 × 432 μm2.
Discharge Discharge Discharge VHH
C1 C2 CLK_INV
Cn

VIN ……
MN1V MP1V MN2V MP2V MNnV MPnV RFID tag
VDD VDD VDD 470 μm
Discharge Discharge Discharge Reader
Fig. 5. Charge pump circuit
432 μm

Half a clock cycle later is the second stage of boost. EEPROM

At this time, CLK is at high level (the voltage value is
equal to VIN), MN1 is off, and MP1 is on. The upper
plate of C1 is connected to the high level, and the
voltage value is VIN. Because the voltage difference of Fig. 6. The layout of the EEPROM and its test environment
the capacitor cannot be changed suddenly, the prin- In order to test the function and performance of
ciple can be used to improve the voltage. In this case: EEPROM, and verify the application of EEPROM in
Uc+ = 2V IN (2) RFID tag, we design additional RF analog circuit and
digital circuit. The general command of RFID can be
When several groups of such structures are cas- used to read and write EEPROM. For example, when
caded together, a charge pump circuit is formed, which writing EEPROM, we can consider using pulse position
is used to generate the high voltage signal VHH for coding and 100% ASK modulation to send commands
erasure. Only under the action of CLK, the charge and data to tags through readers. As shown in Fig.7,
pump can work. If CLK is turned off, the output we send a command to write a single block (22 21 C8
voltage will always be equal to VIN. In an ideal state, B6 A2 26 00 01 04 10 00 AA BB CC DD B0 65), that
VIN can be added to each level, after N level, there are: is, to write the EEPROM of block “00” to “AA BB CC
DD”, whether the tag is written successfully can be
V HH = (1 + N ) × V IN (3)
judged by observing the reply of the tag. The tag ad-
The proposed charge pump consists of two parallel opts single subcarrier and Manchester coding, and re-
branches. Considering that the charge pump has only turns “00” through load modulation, which means the
 A 2 Kbits Low Power EEPROM for Passive RFID Tag IC 23

operation is successful. During the read operation, we “AA BB CC DD”, which is consistent with what we
send a command to read a single block (22 20 C8 B6 just wrote. In order to verify the correctness of the
A2 26 00 01 04 10 00 90 55), that is, to read the EEP- whole EEPROM, we repeatedly erase and read any
ROM of the “00” block. According to the data re- block. After millions of tests, the circuit can still oper-
turned by the tag, we can find that what we read is ate reliably and achieve the design goal.

1/4 coding

Reader sends 100%ASK modulation Manchester encode

Write single block command one subcarrier
Flags+command+UID+block num+data+CRC16:
22 21 C8 B6 A2 26 00 01 04 10 00 AA BB CC DD B0 65

Tag responses load modulation

Tag responses (Flag+CRC16) : 00 78 F0

Tag responses load modulation

Tag responses (Flag+Data+CRC16):
Reader sends 100%ASK modulation
00 AA BB CC DD 62 7C
Read single block command
Flags+command+UID+ block num+CRC16:
22 20 C8 B6 A2 26 00 01 04 10 00 90 55

Fig. 7. Measured results

The main performance parameters of EEPROM are the power consumption of reading EEPROM. Com-
listed in Table 1 and compared with the existing literat- pared with the existing literature, the 0.68 μ A read
ure[10,15,16]. It can be seen that the input voltage of EE- power consumption of this paper has great advantages.
PROM designed in this paper can adapt to a wide
range of changes. The area of single cell is 2.88 μm2, the V. Conclusions
total storage capacity is 2 Kbits, and the access time is In this paper, a low-cost and low-power 2Kbit EE-
1.7 μs. For RFID tag chip, the most important thing is PROM memory is proposed and applied to high-fre-
quency RFID tag chip. In order to reduce the power
Table 1. Comparison with prior references consumption, a read-write circuit structure of parallel
Proposed Ref.[15] Ref.[10] Ref.[16] input and serial output is adopted. Only one sensitive
Process (nm) 180 180 180 90 amplifier is needed to read the stored data, which can
Cell type EEPROM 2T OTP EEPROM EEPROM
effectively reduce the power consumption of read opera-
Supply voltage (V) 1–1.8 1.8 1 1.5
tion. The proposed EEPROM is fabricated in 180 nm 2P
Cell size (μm2) 2.88 4.88 – –
Memory size 2 Kbit 2 Kbit 1 Kbit 200 KB 6M CMOS process, and its area is only 0.2 mm2. The
Access time (μs) 1.7 0.05 1.6 0.03 experimental results show that the circuit can work ef-
Area (mm2) 0.2 0.13 0.12 1.271 fectively in the environment of passive RFID tag chip,
Program current (μA) 30 58 33 600 and has the advantage of low power consumption, in
Read current (μA) 0.68 17 1.18 31.25 which the read operation can be as low as 680 nA.
24 Chinese Journal of Electronics 2022

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China, in 2010 and 2016, respectively. He
“Fast bit screening of automotive grade EEPROMs—Con-
tinuous improvement exercise,” IEEE Transactions on Very is currently a Researcher with the Devel-
Large Scale Integration (VLSI) Systems, vol.25, no.4, pp. opment Research Institute of Guangzhou Smart City. His re-
1250–1260, 2017. search interests include RFID tag and reader IC, analog front
[15] N. D. Phan, I. J. Chang, and J.-W. Lee, “A 2-Kb one-time end, ESD, LDO, demodulator and so on.
programmable memory for UHF Passive RFID tag IC in a (Email: [email protected])