Scribd
Upload
2 views18 pages

Assembler Directives

The document provides an overview of assembler directives, instruction fields, and the differences between the 8085 and 8086 microprocessors. It highlights the features and architecture of the 8086, including memory segmentation, addressing modes, and important pins. Additionally, it details the registers used in the 8086 and their functions in data and instruction processing.

Uploaded by

sonangmo27
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
2 views18 pages

Assembler Directives

The document provides an overview of assembler directives, instruction fields, and the differences between the 8085 and 8086 microprocessors. It highlights the features and architecture of the 8086, including memory segmentation, addressing modes, and important pins. Additionally, it details the registers used in the 8086 and their functions in data and instruction processing.

Uploaded by

sonangmo27
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 18

• Assembler directives:

 These are hints given to assembler by programmer


while writing an assembly language program.
 ORG—origin, start program/data @ a location.
 DB – define byte – 1byte memory space is allocated
for the variable .
 Ex: x db 12h,34h/ x db 10h dup( 00 )—16 bytes are
allocated for variable ‘x’ and duplicated with 00.
 DW- define word –2bytes space
 DQ –define quadword
 EQU – equate ; pi EQU 3.14
 End –end of program, ENDS—end of segment
• Fields of an instruction:
• LABEL: MNEMONIC OPERANDS; STATEMENT
Between operands , must be used
Ex:Rep: DCR C ;Decrement the content of Reg--C
Differences b/w 8085 & 8086
8085 8086
Type 8 bit µp 16 bit µp
Address lines 16 20
Data lines 8 16
Total memory 216 = 64KB 220 = 1 MB
Segmented M/M
Memory architecture Von-Neumann Von-Neumann
Operating frequrency 3 Mhz 5Mhz
Operating voltage + 5 V DC + 5V DC
Registers 8 bit & 16bit All are 16 bit
Flags 5—S,Z,AC,P,CY 9—O,D,I,T,S,Z,AC,P,CY
When reset , program 0000H FFFFO H
control transfers to
8085 8086
Modes of operation ------- Minimum & Maximum

Interrupts 5 hardware & 8 Maximum -256


software
Interrupt Interval 8 bytes 4B x 256=1024B/1KB
Interrupt vector table
IC 40 PIN 40 PIN
Max length of 3 bytes 6 Bytes
Instruction
Pipelining technique Not possible possible
Multiplication & Not possible Possible
division
Important features of 8086
It is a 16 bit processor, has 20 Address lines
Max memory that can be interfaced is 1MB
Follows Von-Neumann architecture
Operating voltage +5v DC supply
Frequency of operation5Mhz(5-8Mhz)
40 pin IC
MN/MX0- Maximum mode; 8086with others
1- Minimum mode; only 8086
All registers = 16bits
GDR’sGeneral Data reg’s--AX, BX, CX, DX
AX--Accumulator, default register in Mul..& Div..
BX -- Offset pointer
CX– Default counter
DX– Default register in multiplication and divisions
Special purpose Registers:
1. Segment Registers:
 CS-Code segment register
 DS- Data segment register
 SS-Stack segment register
 ES- Extra segment register
2. Pointer & Index registers:
IP – Instruction Pointer(Similar to PC in 8085)r
SP– Stack Pointer
BP—Base Pointer
SI- Source index register; used in string instructions
DI—Destination index register; used in string
instructions
3. Flag Register:
D15 D14 ------------------------D7 --------------------D1 D0
X X X X O D I T S Z X A X P X C
C Y
• T- Trap flag 1; Single step execution mode; Processor
stops after every instruction, such that results of the
registers can be verified.
• I- Interrupt1; Maskable interrupts are
recognised
0; Not recognised
Ex; INTR
• D- Direction : Used in string manipulation instructions
0; Auto increment mode; String is
processed from lower address to higher.
1;Auto decrement mode; Processed from
higher address to lower address.
• O- Overflow 1; if destination register is not able to hold
result of a signed operation.
 Maximum interrupts possible = 256
 If reset , the processor is initialised at FFFFOh
 ALE=1; All 20 lines  Address bus
=0; A19 – A16  status signals
AD15 -- AD0 Data bus
 Maximum length of Instruction---6Bytes
 Has 6bytes of Instruction byte queue in which
maximum length of instruction can be pre-fetched.

 Pipelining Technique:
More than one instruction can be at different
stages of execution at a single interval of time, so
speed increases.
Memory Segmentation
• 1 MB of memory is divided into 16 logical segments
of each 64KB.
• Base Address: It indicates the starting location of a
particular segment. It is present in Segment
registers.
• Offset Address : It is the distance of required
memory location from the beginning of the
segment. It is present in offset or index registers.
• Physical/Effective Address: It is the distance of
required memory location from the beginning of
memory.
• Physical address calculation:
1. Shift the Base/Segment address by 4 bit
locations left or 1 hexadecimal digit.
Shifting is equalent to multiplying CS by 10H.
2.Add the offset address to the shifted segment
value.
Ex: CS 9000H & IP 0FFF H
90000 H
+ 0FFF H
90FFF H
Effective Adrs Base Adrs 1MB
00000H 0000H 0000h
64KB

0FFFFH FFFFh
1000H
10000H 0000h
64KB

FFFFh
2000H
0000h
64KB

FFFFh

F000H
0000h
64KB
FFFFFH
FFFFh
Registers to point Segment and offset addresses
1. Code Segment: To store program or code
 Base Address : CS
 Offset Address: IP
2. Data Segment: To store Data
 Base Address : DS
 Offset Address: BP/BX
3. Stack Segment: To store temporary data
 Base Address : SS
 Offset Address :SP
4. Extra Segment: Alternate Data segment
 Base Address : ES
 Offset Address: SI/DI
Range of segment address- 0000H to F000H
Range of offset address  0000H to FFFFH
Addressing modes
• There are two types of instructions in 8086
1.Sequential flow ---8 modes
2. Control transfer--- 4 modes
Effective address: DS * 10H + offset address
1. Immediate --MOV AL, 80H; MOV AX,8000H
2. Direct ---MOV AL, [8000H]
3. Register---MOV AL, BL; MOV AX,BX
4. Register Indirect---MOV AL, [BX]
5. Register relative---MOV AL, 06H[BX]
6. Indexed---MOV AL, [SI]
7. Based Indexed--- MOV AL, [BX][SI]
8. Relative based indexed -- MOV AL, 07H[BX][SI]
Ex: Mathematically effective address can be
written as DS * 10H + offset address for data
segment.
Control transfer:
1. Intra segment – Program control is transferred
within the same segment
2. Inter segment – Program control is transferred
from one segment to another.
Important Pins in 8086
• ALE – Address latch enable
 1; All 20 line --- As address bus
 0; A19 – A 16  status signals
AD15 – AD0  Data bus
AD15 – AD8 : Higher byte of Data bus
AD7 – AD0 : Lower byte of Data bus
BHE- Bus high enable,
-- 0; If AD15 – AD8 are used for Data/Address .
BHE is used along with A0 line for selecting the even or odd bank of
memory
BHE A0
0 0 --- whole word (Two bytes)
0 1 --- odd bank byte
1 0 ---- even bank bye
1 1 --- Not used
• DT/R–> Data transmit or receive for bidirectional
buffers
-- 0: Receive ; 1: transmit
• DEN  To enable the data buffers when data is
transmitted through AD15 – AD0 lines
• LOCK –> o/p signal , which indicates that Mp is
executing some important instruction having lock
prefix and buses can not be used by other system.
• TEST  0: then only processor executes further
instruction, used with WAIT instruction.

You might also like