ECE4703

Lab 5
Michael Rothstein
Zhuolin Liu
Date:Nov/28/2023
Introduction:
In this lab, we used the MSP-EXP432P401R with an attachment that had a microphone
and speaker to perform the experiments. In order to look at the results and generate signals, a
Digilent Analog Discovery oscilloscope was used. This setup was used to explore a BPSK
Modulator. The root raised cosine design used in this lab was created in MATLAB and then
implemented in c. The results showed that the Modulator worked correctly.

Methods:
The lab consisted of 3 questions. In order to complete the lab we had to configure the
pins. We established a connection from the DAC pin to record the filtered signal. Pin J1.2 was
used to feed the signal, which was produced by the waveform generation software, into the
board. And 2 ground pins are connected.
The first question was completed in MATLAB. It was done by running the modulator.m
file found in the class Github. The unsampled symbol stream was claculated in upsampled. The
RRC filter output was in rcupsym. The unconverted RRC output was in modrcupsym, and the
coefficients were in rcp. The MATLAB file in GITHUB provided a method to calculate these
values, however the numsymbols was varied depending on the part of the questions between
32 and 512. Furthermore, the code did not have a method to visualize the data. In order to
visualize the data we utilized the plot function, pwelch function, and eyediagram function. These
were used to plot the data, find the periodogram, and create the eye diagram.
The second question involved grabbing the coefficients(multiplied by the pattern 1,0,-
1,0) from MATLAB, moving them into c and performing a multirate implementation. The
coefficients were moved into the coef line in the lab Github file. They were reformatted using a
MATLAB function that adds commas between each of the numbers, matching the required
formatting for c. The multirate (processsamplemultirate function) examples in the class Github
were implemented in the lab c file. The function was changed by making nextsample equal to
the rccphase (function in lab file) input symbol. The bpsksymbolgenerator function accounted for
the processsample function in the class example code, making the code function correctly.
Furthermore a debug pin was added in the process sample using an if else statement. These
changes ensured that the question requirements were met. The results were shown by looking
at the time response, frequency response, and persistence plot on the Waveforms.
To do the third question, we found the rrcphase function from assembly code by looking
for “.thumbfunc rrcphase”. This location is where the function starts. We searched for actions
with registers and values after “.thumbfunc rrcphase”, which indicates that the instruction we
counted is for “rrcphase” function. For instance, when counting instructions listed we focus on
the words MOV, STR etc. By counting those instructions, we can have a clear idea of how often
the programs access and move data. This is done with and without including the for loops.

Question 1:

Figures 1, 2, 3, 4, 5, and 6 show the results of the 6 sub questions in question 1. The
plots were made in MATLAB and show varying levels of symbols kept (number of first symbols)
in different ways and representations (upsampled, upconverted, eyediagram, and Pwelch). The
Power Spectrum of the RRC Filter Output with 512 Symbols began dropping at around
0.1*(fs/2) and the Power Spectrum of the Upconverted RRC Filter Output with 512 Symbols
had a passband between 0.35*(fs/2) and 0.65*(fs/2).

Figure 1: UpSampled Symbol Stream 32 Symbols Plot

Figure 2: RRC Filter Output First 32 Symbols

 Figure 3: Eye Diagram 512 Symbols

Figure 4: Power Spectrum of the RRC Filter Output 512 Symbols

 Figure 5: Upconverted RRC Filter Output 32 Symbols

Figure 6: Power Spectrum of the Upconverted RRC Filter Output 512 Symbols

Question 2:
 The results of this question are shown in Figures 7, 8, 9, 10, and 11. In Figure 7 and
Figure 8, the coefficients from MATLAB are not multiplied by the [1,0,-1,0] pattern, root raised
cosine filter. However, in Figure 9 and ten they are. The optimization 1 is completed by
transforming the original coefficients by multiplying by the pattern and optimization 2 is done by
using the multirate process. The blue line in the plots shows the the debugging pin.

Figure 7: Time and Frequency Response Without multiplying by the [1,0,-1,0] pattern

Figure 8. Time response and Persistence plot Without multiplying by the [1,0,-1,0] pattern
 Figure 9. Time and Frequency response With multiplying by the [1,0,-1,0] pattern

Figure 10. Persistence plot With multiplying by the [1,0,-1,0] pattern

Figure 11. Clock Cycles

Question 3:
This part of the lab provides answers to the third question, which seeks details about the assembly code
listing of the 'rrcphase' function and its instruction count. The section begins with the assembly code
listing for the 'rrcphase' function. Following this, we enumerate and explain each instruction, highlighting
which instructions are called and moved. Subsequently, we analyze the number of instructions executed
during each invocation of 'rrcphase,' including those within for loops.

In the “rrcphase” function, there are a total of 32 instructions listed. This count includes executable
instructions. The function contains two for-loops: the first executes 6 times and the second executes 7
times. Prior to the first for-loop, there are 14 instructions. Each loop has 9 instructions: the first loop
iterates 6 times, and the second iterates 7 times. Therefore, the total number of instructions executed per
invocation of “rrcphase” is calculated as follows: 14 + (9 * 6) + (9 * 7) = 131 instructions.

The Assembly code below is the code listing for function rrcphase:
.thumbfunc rrcphase
224 00000000 .thumb
225 .global rrcphase
226
227 $C$DW$19 .dwtag DW_TAG_subprogram
228 .dwattr $C$DW$19, DW_AT_name("rrcphase")
229 .dwattr $C$DW$19, DW_AT_low_pc(rrcphase)
230 .dwattr $C$DW$19, DW_AT_high_pc(0x00)
231 .dwattr $C$DW$19, DW_AT_TI_symbol_name("rrcphase")
232 .dwattr $C$DW$19, DW_AT_external
233 .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$172)
234 .dwattr $C$DW$19, DW_AT_TI_begin_file("../main.c")
235 .dwattr $C$DW$19, DW_AT_TI_begin_line(0x1e)
236 .dwattr $C$DW$19, DW_AT_TI_begin_column(0x0b)
237 .dwattr $C$DW$19, DW_AT_decl_file("../main.c")
238 .dwattr $C$DW$19, DW_AT_decl_line(0x1e)
239 .dwattr $C$DW$19, DW_AT_decl_column(0x0b)
240 .dwattr $C$DW$19, DW_AT_TI_max_frame_size(0x10)
241 .dwpsn file "../main.c",line 30,column 43,is_stmt,address rrcphase,isa 1
242
243 .dwfde $C$DW$CIE, rrcphase
244 $C$DW$20 .dwtag DW_TAG_formal_parameter
245 .dwattr $C$DW$20, DW_AT_name("phase")
246 .dwattr $C$DW$20, DW_AT_TI_symbol_name("phase")
247 .dwattr $C$DW$20, DW_AT_type(*$C$DW$T$10)
248 .dwattr $C$DW$20, DW_AT_location[DW_OP_reg0]
249
250 $C$DW$21 .dwtag DW_TAG_formal_parameter
251 .dwattr $C$DW$21, DW_AT_name("symbol")
252 .dwattr $C$DW$21, DW_AT_TI_symbol_name("symbol")
253 .dwattr $C$DW$21, DW_AT_type(*$C$DW$T$10)
254 .dwattr $C$DW$21, DW_AT_location[DW_OP_reg1]
255
256
257 ;*****************************************************************************
258 ;* FUNCTION NAME: rrcphase *
 259 ;* *
260 ;* Regs Modified : A1,A2,A3,A4,V3,V4,SP,SR,D0,D0_hi,D1 *
261 ;* Regs Used : A1,A2,A3,A4,V3,V4,SP,LR,SR,D0,D0_hi,D1 *
262 ;* Local Frame Size : 0 Args + 0 Auto + 12 Save = 12 byte *
263 ;*****************************************************************************
264 rrcphase:
265 ;* --------------------------------------------------------------------------*
266 ;* A1 assigned to $O$C16
267 ;* A2 assigned to $O$A17
268 ;* A1 assigned to $O$U16
269 ;* A2 assigned to $O$U39
270 ;* A3 assigned to $O$U29
271 ;* V4 assigned to $O$L2
272 ;* V4 assigned to i
273 $C$DW$22 .dwtag DW_TAG_variable
274 .dwattr $C$DW$22, DW_AT_name("i")
275 .dwattr $C$DW$22, DW_AT_TI_symbol_name("i")
TI ARM Assembler PC v20.2.6 Tue Nov 28 15:28:07 2023

Copyright (c) 1996-2018 Texas Instruments Incorporated

C:\Users\micha\AppData\Local\Temp\{069B388C-3B41-44ED-8A0B-D82A31DFD6F5} PAGE 6

276 .dwattr $C$DW$22, DW_AT_type(*$C$DW$T$10)

277 .dwattr $C$DW$22, DW_AT_location[DW_OP_reg7]
278
279 ;* V3 assigned to phase
280 $C$DW$23 .dwtag DW_TAG_variable
281 .dwattr $C$DW$23, DW_AT_name("phase")
282 .dwattr $C$DW$23, DW_AT_TI_symbol_name("phase")
283 .dwattr $C$DW$23, DW_AT_type(*$C$DW$T$483)
284 .dwattr $C$DW$23, DW_AT_location[DW_OP_reg6]
285
286 ;* A2 assigned to symbol
287 $C$DW$24 .dwtag DW_TAG_variable
288 .dwattr $C$DW$24, DW_AT_name("symbol")
289 .dwattr $C$DW$24, DW_AT_TI_symbol_name("symbol")
290 .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$483)
291 .dwattr $C$DW$24, DW_AT_location[DW_OP_reg1]
292
293 ;* D0 assigned to q
294 $C$DW$25 .dwtag DW_TAG_variable
295 .dwattr $C$DW$25, DW_AT_name("q")
296 .dwattr $C$DW$25, DW_AT_TI_symbol_name("q")
297 .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$172)
298 .dwattr $C$DW$25, DW_AT_location[DW_OP_regx 0x40]
299
300 ;* V4 assigned to limit
301 $C$DW$26 .dwtag DW_TAG_variable
302 .dwattr $C$DW$26, DW_AT_name("limit")
 303 .dwattr $C$DW$26, DW_AT_TI_symbol_name("limit")
304 .dwattr $C$DW$26, DW_AT_type(*$C$DW$T$10)
305 .dwattr $C$DW$26, DW_AT_location[DW_OP_reg7]
306
307 .dwcfi cfa_offset, 0
308 00000000 B5C8 PUSH {A4, V3, V4, LR} ; [DPU_V7M3_PIPE] ; [ORIG 16-BIT INS]
309 .dwcfi cfa_offset, 16
310 .dwcfi save_reg_to_mem, 14, -4
311 .dwcfi save_reg_to_mem, 7, -8
312 .dwcfi save_reg_to_mem, 6, -12
313 .dwcfi save_reg_to_mem, 3, -16
314 00000002 4606 MOV V3, A1 ; [DPU_V7M3_PIPE] |30| ; [ORIG 16-BIT INS]
315 .dwpsn file "../main.c",line 31,column 17,is_stmt,isa 1
316 00000004 483F LDR A1, $C$FL1 ; [DPU_V7M3_PIPE] |31| ; [ORIG 16-BIT
INS]
317 00000006 4A42 LDR A3, $C$CON1 ; [DPU_V7M3_PIPE] ; [ORIG 16-BIT INS]
318 00000008 0A10EE00 VMOV S0, A1 ; [DPU_MERLIN_PIPE] |31| ; [KEEP 32-
BIT INS]
319 0000000c B99E CBNZ V3, ||$C$L2|| ; [] ; [ORIG 16-BIT INS]
320 .dwpsn file "../main.c",line 37,column 5,is_stmt,isa 1
321 ; BRANCHCC OCCURS {||$C$L2||} ; [] |37|
322 ;* --------------------------------------------------------------------------*
323 .dwpsn file "../main.c",line 38,column 9,is_stmt,isa 1
324 0000000e 1A90EE00 VMOV S1, A2 ; [DPU_MERLIN_PIPE] |38| ; [KEEP 32-
BIT INS]
325 00000012 0AE0EEF8 VCVT.F32.S32 S1, S1 ; [DPU_MERLIN_PIPE] |38| ; [KEEP
32-BIT INS]
326 00000016 0AE0EEFD VCVT.S32.F32 S1, S1 ; [DPU_MERLIN_PIPE] |38| ; [KEEP
32-BIT INS]
327 0000001a 2706 MOVS V4, #6 ; [DPU_V7M3_PIPE] ; [ORIG 16-BIT INS]
328 0000001c 1A90EE10 VMOV A2, S1 ; [DPU_MERLIN_PIPE] |38| ; [KEEP 32-
BIT INS]
329 00000020 4610 MOV A1, A3 ; [DPU_V7M3_PIPE] |38| ; [ORIG 16-BIT INS]
330 00000022 6001 STR A2, [A1, #0] ; [DPU_V7M3_PIPE] |38| ; [ORIG 16-BIT INS]
TI ARM Assembler PC v20.2.6 Tue Nov 28 15:28:07 2023

Copyright (c) 1996-2018 Texas Instruments Incorporated

C:\Users\micha\AppData\Local\Temp\{069B388C-3B41-44ED-8A0B-D82A31DFD6F5} PAGE 7

331 00000024 3018 ADDS A1, A1, #24 ; [DPU_V7M3_PIPE] ; [ORIG 16-BIT INS]
332 ;* --------------------------------------------------------------------------*
333 ;* BEGIN LOOP ||$C$L1||
334 ;*
335 ;* Loop source line : 39
336 ;* Loop closing brace source line : 40
337 ;* Known Minimum Trip Count :6
338 ;* Known Maximum Trip Count :6
339 ;* Known Max Trip Count Factor : 6
340 ;* --------------------------------------------------------------------------*
 341 00000026 ||$C$L1||:
342 .dwpsn file "../main.c",line 40,column 13,is_stmt,isa 1
343 00000026 1C04F850 LDR A2, [A1, #-4] ; [DPU_V7M3_PIPE] |40| ; [KEEP 32-BIT
INS]
344 .dwpsn file "../main.c",line 39,column 30,is_stmt,isa 1
345 0000002a 1E7F SUBS V4, V4, #1 ; [DPU_V7M3_PIPE] |39| ; [ORIG 16-BIT
INS]
346 .dwpsn file "../main.c",line 40,column 13,is_stmt,isa 1
347 0000002c 1904F840 STR A2, [A1], #-4 ; [DPU_V7M3_PIPE] |40| ; [KEEP 32-BIT
INS]
348 .dwpsn file "../main.c",line 39,column 30,is_stmt,isa 1
349 00000030 D1F9 BNE ||$C$L1|| ; [DPU_V7M3_PIPE] |39| ; [ORIG 16-BIT INS]
350 ; BRANCHCC OCCURS {||$C$L1||} ; [] |39|
351 ;* --------------------------------------------------------------------------*
352 .dwpsn file "../main.c",line 43,column 20,is_stmt,isa 1
353 00000032 2707 MOVS V4, #7 ; [DPU_V7M3_PIPE] |43| ; [ORIG 16-BIT INS]
354 00000034 E000 B ||$C$L3|| ; [DPU_V7M3_PIPE] |43| ; [ORIG 16-BIT INS]
355 ; BRANCH OCCURS {||$C$L3||} ; [] |43|
356 ;* --------------------------------------------------------------------------*
357 00000036 ||$C$L2||:
358 00000036 2706 MOVS V4, #6 ; [DPU_V7M3_PIPE] |43| ; [ORIG 16-BIT INS]
359 ;* --------------------------------------------------------------------------*
360 00000038 ||$C$L3||:
361 00000038 4936 LDR A2, $C$CON2 ; [DPU_V7M3_PIPE] ; [ORIG 16-BIT INS]
362 0000003a 0186EB01 ADD A2, A2, V3, LSL #2 ; [DPU_V7M3_PIPE] ; [KEEP 32-BIT
INS]
363 ;* --------------------------------------------------------------------------*
364 ;* BEGIN LOOP ||$C$L4||
365 ;*
366 ;* Loop source line : 44
367 ;* Loop closing brace source line : 45
368 ;* Known Minimum Trip Count :6
369 ;* Known Maximum Trip Count :7
370 ;* Known Max Trip Count Factor : 1
371 ;* --------------------------------------------------------------------------*
372 0000003e ||$C$L4||:
373 .dwpsn file "../main.c",line 45,column 9,is_stmt,isa 1
374 0000003e 0B04F852 LDR A1, [A3], #4 ; [DPU_V7M3_PIPE] |45| ; [KEEP 32-BIT
INS]
375 00000042 0A90EE00 VMOV S1, A1 ; [DPU_MERLIN_PIPE] |45| ; [KEEP 32-
BIT INS]
376 00000046 6B20F851 LDR V3, [A2], #32 ; [DPU_V7M3_PIPE] |45| ; [KEEP 32-BIT
INS]
377 0000004a 6A10EE01 VMOV S2, V3 ; [DPU_MERLIN_PIPE] |45| ; [KEEP 32-
BIT INS]
378 0000004e 0AE0EEF8 VCVT.F32.S32 S1, S1 ; [DPU_MERLIN_PIPE] |45| ; [KEEP
32-BIT INS]
379 .dwpsn file "../main.c",line 44,column 24,is_stmt,isa 1
 380 00000052 1E7F SUBS V4, V4, #1 ; [DPU_V7M3_PIPE] |44| ; [ORIG 16-BIT
INS]
381 .dwpsn file "../main.c",line 45,column 9,is_stmt,isa 1
382 00000054 0A20EE01 VMLA.F32 S0, S2, S1 ; [DPU_MERLIN_PIPE] |45| ; [KEEP
32-BIT INS]
383 .dwpsn file "../main.c",line 44,column 24,is_stmt,isa 1
384 00000058 D1F1 BNE ||$C$L4|| ; [DPU_V7M3_PIPE] |44| ; [ORIG 16-BIT INS]
385 ; BRANCHCC OCCURS {||$C$L4||} ; [] |44|
TI ARM Assembler PC v20.2.6 Tue Nov 28 15:28:07 2023

Copyright (c) 1996-2018 Texas Instruments Incorporated

C:\Users\micha\AppData\Local\Temp\{069B388C-3B41-44ED-8A0B-D82A31DFD6F5} PAGE 8

386 ;* --------------------------------------------------------------------------*
387 $C$DW$27 .dwtag DW_TAG_TI_branch
388 .dwattr $C$DW$27, DW_AT_low_pc(0x00)
389 .dwattr $C$DW$27, DW_AT_TI_return
390
391 0000005a BDC8 POP {A4, V3, V4, PC} ; [DPU_V7M3_PIPE] ; [ORIG 16-BIT INS]
392 .dwcfi cfa_offset, 0
393 .dwcfi restore_reg, 7
394 .dwcfi restore_reg, 6
395 .dwcfi restore_reg, 3
396 ; BRANCH OCCURS ; []
397 .dwattr $C$DW$19, DW_AT_TI_end_file("../main.c")
398 .dwattr $C$DW$19, DW_AT_TI_end_line(0x30)
399 .dwattr $C$DW$19, DW_AT_TI_end_column(0x01)
400 .dwendentry
401 .dwendtag $C$DW$19
The rccphase function assembly code listing ends here

From above assembly code we can see that there is total 32 instructions in the listing:
Exactly line and movement explained below:
1. PUSH {A4, V3, V4, LR}: Pushes registers onto the stack.
2. MOV V3, A1: Moves the value from A1 to V3.
3. LDR A1, $C$FL1: Loads a value into A1.
4. LDR A3, $C$CON1: Loads a value into A3.
5. VMOV S0, A1: Moves the value from A1 to S0.
6. CBNZ V3, ||$C$L2||: Conditional branch.
7. VMOV S1, A2: Moves the value from A2 to S1.
8. VCVT.F32.S32 S1, S1: Convert S1 from a 32-bit integer to a floating-point value.
9. VCVT.S32.F32 S1, S1: Convert S1 from a floating-point value to a 32-bit integer.
10. MOVS V4, #6: Moves immediate value 6 to V4.
11. VMOV A2, S1: Moves the value from S1 to A2.
12. MOV A1, A3: Moves the value from A3 to A1.
 13. STR A2, [A1, #0]: Store the value of A2 into the memory location pointed to by A1.
14. ADDS A1, A1, #24: Add immediate value 24 to A1.
First For loop(looping 6 times) (Total 9 instruction counted in here)
15. LDR A2, [A1, #-4]: Load the value from memory into A2.
16. SUBS V4, V4, #1: Subtract immediate value 1 from V4.
17. STR A2, [A1], #-4: Store the value of A2 into memory and update A1.
18. BNE ||$C$L1||: Conditional branch.
19. MOVS V4, #7: Moves immediate value 7 to V4.
20. B ||$C$L3||: Unconditional branch.
21. MOVS V4, #6: Moves immediate value 6 to V4.
22. LDR A2, $C$CON2: Loads a value into A2.
23. ADD A2, A2, V3, LSL #2: Adds V3 shifted left by 2 to A2.
Second For loop(looping 7 times) (Total 9 instruction counted in here)
24. LDR A1, [A3], #4: Loads a value into A1 and post-increments A3.
25. VMOV S1, A1: Moves the value from A1 to S1.
26. LDR V3, [A2], #32: Loads a value into V3 and post-increments A2.
27. VMOV S2, V3: Moves the value from V3 to S2.
28. VCVT.F32.S32 S1, S1: Convert S1 from a 32-bit integer to a floating-point value.
29. SUBS V4, V4, #1: Subtract immediate value 1 from V4.
30. VMLA.F32 S0, S2, S1: Perform a multiply-accumulate operation.
31. BNE ||$C$L4||: Conditional branch.
32. POP {A4, V3, V4, PC}: Pops registers from the stack and branches to the return address.

Conclusion:
In this lab we created symbol streams, and a filter in MATLAB and visualized them. Next
we brought the coefficients into c, optimized them, created the filter, and observed the result
through the time response, persistence diagram, and frequency response. This lab taught us
how to visualize symbol streams in MATLAB, bring MATLAB coefficients into c, apply
optimization techniques, apply a multirate filter in c, and create a persistence plot in Waveforms.

References

https://schaumont.dyn.wpi.edu/ece4703b23/lab5.html

https://hub.wpi.edu/software/576/code-composer-studio

https://www.ti.com/tool/download/SIMPLELINK-MSP432-SDK
https://schaumont.dyn.wpi.edu/ece4703b23/techdoc.html#data-sheets-and-user-guides