NC State University Spring 2023

ECE Department ECE 546 W. Rhett Davis

Layout Tutorial 1
with the FreePDK3 and Synopsys Custom Compiler

In this tutorial you will go through creating an Inverter layout while performing design-rule checks
(DRC). This tutorial assumes that you have logged in to an EOS machine and are familiar with basic
UNIX commands.

Contents
1. Create a Script to Setup Your Environment....................................................................................................... 1
2. Start the Custom Compiler Framework ............................................................................................................. 1
3. Create Layout View of an Inverter .................................................................................................................... 3
3.1. Create New Library.................................................................................................................................... 3
3.2. Create New Layout View ........................................................................................................................... 4
4. Selecting and Moving Layout ............................................................................................................................ 9
5. DRC ..................................................................................................................................................................10
5.1. Viewing DRC Errors.................................................................................................................................11
6. Painting .............................................................................................................................................................14
6.1. Other Ways to Create Shapes....................................................................................................................15
6.2. Add Remaining Wires and Power Rails....................................................................................................15
7. Create Pins ........................................................................................................................................................16
8. Further Reading ................................................................................................................................................18

1. Create a Script to Setup Your Environment

Before you start this tutorial, log in to a Linux machine and create a file called setup.sh file that contains
the following lines:
module load synopsys/2022
source /mnt/designkits/ncsu/FreePDK3/syncust/scripts/setup/setup.sh

The second line will set up your current environment with variables and your current directory with files
that are needed to run the Synopsys tools with the FreePDK3 design-kit. At the moment, this includes
only lib.defs, though we may add .synopsys_custom.tcl later in the semester. Keep this file somewhere
handy. You will probably want to copy it into any directory where you plan to create files for ECE 546.

Note to users outside NCSU: The setup.sh scripts mentioned above is provided in
$PDK_DIR/syncust/scripts/setup/setup.sh.

2. Start the Custom Compiler Framework

1. Log in to a Linux machine. The setup for this tutorial is currently supported only on Linux machines.
2. Create a directory to run this tutorial, called something like "layout1". Change to this directory and copy
the setup.sh script into this directory.

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3. Type "source setup.sh" at the command prompt. This will set-up the environment and files and start a
new command shell with the Custom Compiler and HSPICE tools in the search path.
4. Start Custom Compiler by typing "custom_compiler &" at the command prompt.

$ mkdir layout1
$ cd layout1
$ source setup.sh
$ custom_compiler &

The main Custom Compiler home window will appear, as shown below:

One of the most useful windows is the Library Manager, which allows you to browse the available
libraries and create your own. To display this window, click on Library Manager in the home window.

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Another very useful window is the Console, which allows you to read error messages and enter various
text commands. To display this window, click on Console in the home window. Notice that you can
switch back to the home window by clicking on the home-tab in the upper right hand corner. Do that
now, and then display the console window. You should see the following:

3. Create Layout View of an Inverter

In this section of the tutorial, we’ll create the layout of an inverter.

3.1. Create New Library

Before we begin, we need to create a library to store our work. In the Library Manager, create new library
called “mylib”. Select File→New→Library. This will open new dialog window, in which you need to
enter the name and directory for your library. By default, the library will be created in the current
directory. You will need to specify the technology for this library. Do that by selecting “Tech Library”
and setting the drop-down box to “NCSU_TechLib_FreePDK3”. After you fill out the form, it should
look something like this:

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Click OK. You should see the library "mylib" appear in the Library Manager.

3.2. Create New Layout View

Next, select the library you just created in the Library Manager and select File→New→Cell View.... We
will create a layout view of an inverter cell. Simply type in "inv" for the Cell-Name and select "layout"
for the View-Name. Note that the "Editor" is automatically set to "Layout Editor". Click OK.

Alternatively, you can select the "Layout Editor" tool, instead of typing out the view name. This will
automatically set the view name to "layout".
Click Ok. After you hit "OK", the Layout Editor screen will appear as shown below.

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Now you are ready to draw objects in the Layout Editor window. In this section you learn to place copies of other
cells: pmos and nmos. These cells save your time by including many of the shapes you need without having to
draw them yourself.
In Layout Editor select Create→Instance, or simply hit "i". This will pull up the "Create Instance" dialog box as
shown below. Select the library "NCSU_TechLib_FreePDK3", cell "nmos", view "layout".

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Next, move the cursor into the layout editor window. You should see an instance at the tip of your cursor. If you
don’t see an instance, it might simply be too small to see, as in the case shown below.

In this case, you will want to zoom in before placing the instance. To do that, right-click and drag a box
around the origin, as shown below. When you release the button, you should see that the instance is much
larger.

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Next, place the NMOS transistor so that your layout looks like the window below. Make sure to place it
exactly on the origin as shown below, which will make things easier later-on. You can tell if it is on the
origin by looking at the X and Y values in the upper left of the window, which give the coordinates in
microns.

Next, in the create-instance dialog box, change the cell from "nmos" to "pmos". Place the pmos roughly as
shown below, also on the y-axis. Note that you can press Shift-Z at any time to zoom out, or press the F key
to Fit the entire view. Once you have placed the instance, press "Escape" to stop adding instances.

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Now, you will notice that you don't immediately see what is inside the either of the sub-cell instances you just
created. You can fix this by hitting Shift-F to display all levels of hierarchy. (You can also do this by choosing
Options→Design, selecting the General tab and changing the Stop Level from 0 to 32) To switch back, hit
CTRL-F, or set the Stop Level back to 0 from the Design Options dialog box.
You may want to adjust your view so that it looks nicer. Remember, to zoom in, right-click and drag a box around
the area you want to zoom in. Press F to fit the entire design in the window, or SHIFT-Z and CTRL-Z to zoom in
and out by factors of 2.
Use the commands above to show the layout as below.

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Now, look now at the "Layers" box on the right side of the layout window. This box
should look similar to the one shown on the right. If not, click the “LPPs” button to
show the “Layer-Purpose-Pairs”. This box shows you the names of the layers that
are "valid" (meaning that you can manipulate them). You can figure out which layers
are part of the NMOS cell by making them visible and in-visible. To toggle a layer’s
visibility, middle-click with the mouse over the layer's name. You can toggle the
visibility of all layers on and off by clicking the “Visible: All” box in the upper right.
You can type a few characters of a layer’s name in the text-box to quickly search for
a layer. You can also click the “Design” button (shown on the right with a red box)
to limit the number of layers listed to include only those layers that are used in the
current design. Click the “Valid” button (three items below the “Design” button) to
see the list of all Valid layers again.
Using this approach, you should be able to figure out that the NMOS uses the
following layers: ACT, NIM, GATE, DUMMY, and M0A. The PMOS is like it,
except that it uses layers PIM and NW and omits NIM. Note that there is nothing
magical about this instance. You could paint these shapes manually in the current
cell-view, and it would make no difference whatsoever to the tool. However, it’s
much less effort to use this instance, so that’s what we’ll do.
Note also the words "drawing", "net", or "pin" next to each entry in the layer list.
These are the purposes of a shape. The purpose is used to indicate special
functionality of a shape. We will discuss these more in later tutorials. For now,
remember that "drawing" is the purpose that indicates that a shape will appear in the
mask layout. You may sometimes see "drawing" abbreviated as "drw" or "dg".

4. Selecting and Moving Layout

By default, if you simply drag out a region while holding down the left mouse button (Button-1), whatever is
within the box will be selected and highlighted in yellow.

 Drag a box over the nmos you just instantiated. When you release the mouse button, whatever is "selected", in
this case the nmos cell will be highlighted.

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Once you have selected an object (that is, an instance or a shape) you can do lots of things with it.

 For example you can move it by typing the m hot-key and clicking on a reference point for the move. You can
move layout up/down/left/right one grid at a time by clicking at the selection and moving the mouse. Try it.
You can also select objects by clicking on them.

 Clicking the left mouse button once on an instance or shape selects it.
If you didn’t place your NMOS and PMOS cells exactly as illustrated above, try moving them now until they are.
This layout is a good start for an inverter, but it is wasting space. Compact it now by moving the PMOS down
until its PIM rectangle touches the NMOS NIM rectangle, as shown below.

5. DRC
To perform a Design Rule Check (DRC), choose Verification→DRC→Setup and Run…. The DRC form
appears, as shown below. All values should be filled in automatically as shown. Click "OK" to run the check with
the IC Validator tool. If you have not saved the design, you will be prompted to do so. DRC cannot be executed
unless the design is saved.

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5.1. Viewing DRC Errors

You should see a text-viewer window appear that shows IC Validator’s progress on the check. Once
complete, the results viewer (called VUE) will appear as shown below on the left. You can learn about
the errors by clicking on the “DRC Errors” tab as shown below on the right. Then click on the ACT.2
rule name in the Violation Brower panel and double-click on “Error” in the Error List panel. This will
highlight the error in the layout viewer and fit the view to the marker as shown below.

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In this particular case, DRC is showing us that we moved the NMOS and PMOS a bit too close together. There
will need to be at least 21.5 nm between the ACT shapes, as we can see from the “Violation Detail” panel in the
VUE Error Browser window. To fix this error, you'll need to move the instances further apart. It’s good practice
to space your cells by the smallest amount allowed in order to make the layout as dense as possible. You can draw
temporary rulers by hitting "k" and dragging a ruler. You can clear the rulers by hitting "Shift-K". These rulers can
help you to draw dense layout much faster than you would by constantly running DRC. You will notice that the
ruler can only be dragged orthogonally. If you would like to drag a ruler in any direction, then you can change the
snap-mode by selecting the button in the lower-right.
Move the PMOS up by the minimum amount needed and re-verify until the ACT.2 violation disappears. Use
Verification→DRC→Setup and Run… as many times as needed to re-run the checks and reload the new list of
violations. You can also use Verification→DRC→Run, but I find that this choice does not prompt me to save
the layout first. This is confusing, because it will run DRC again on the last version that I had saved. If you
simply want to remove the error markers, click the “Clear Highlights” button in VUE, whick looks like an
eraser.
Once you have removed the ACT.2 violation, you will notice that you still have seven other types of violations to
fix! We will fix them shortly. Before we do that, let’s add another PMOS instance to bring the total PMOS fins
up to 4 (remember that each ACT shape implies a stack of 2 fins). Do that by selecting adding a ruler to indicate a
21.5 nm space above the PMOS ACT shape. Then choose Edit→Copy→Copy fins (or click the copy button ,
or press the “C” key) and click on the PMOS to copy it. Move the cursor until the PMOS ACT shape lines up
with your ruler. The layout should look like the one below.
NOTE: For maximum logic density, it would be better to have only one PMOS ACT shape (i.e. only 2 fins). This
was our intention when creating the FreePDK3 design rules. However, our current SPICE models show that the
PMOS is significantly slower than the NMOS, which means that more fins may be necessary for higher speed.
We hope to find a way to make the PMOS faster in a future revision and enable higher density layout.

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NC State University Spring 2023
ECE Department ECE 546 W. Rhett Davis

Save and Re-run DRC, and you will see that you have added a new type of violation. Let us go through all of
these violations now:
• ACT.7 (6 errors) – The left and right edges of ACT must be underneath DUMMY gate metal. These
DUMMY shapes are not included in the nmos/pmos cells, so we will need to add them ourselves.
• NIM/PIM.1 (1 error) – The tiny space or “notch” between the PIM shapes is not allowed. We will fix
this by adding a PIM rectangle around both pmos cells.
• NIM/PIM.2 (3 errors) – There is a minimum vertical width requirement for NIM & PIM shapes. The
same PIM rectangle that fixes the NIM/PIM.1 error will fix this one, too. We will also need to add a NIM
rectangle around the NMOS to fix the remaining error.
• NIM/PIM.5 (3 errors) – NIM & PIM must extend 20 nm beyond ACT, but this is slightly confusing,
because this rule can be satisfied by a combination of NIM and PIM, not a single NIM or PIM shape.
Therefore, the NIM and PIM shapes that we already plan to add will fix all of these violations as long as
we ensure that they touch between the nmos and pmos instances.
• NIM/PIM.6 & .7 (3 errors each) – These will also go away after adding NIM & PIM rectangles.
• NW.1 & .3 (2 errors each) – These are similar to the NIM/PIM errors and can be solved by adding an NW
shape around the pmos instances.
To learn more about each design-rule, find the complete list of the current rules under the “Rules” tab of
the FreePDK3 Layer Reference. This Spread-Sheet page gives the name and value of every rule.
In the next section, we will fix these errors by paining the rectangles.

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6. Painting
We are now going to "paint" the necessary rectangles to fix our DRC errors.

 Select the NIM layer in the layer list by left-clicking on it.

 Press “R” to being drawing a rectangle. Left-click once to place one corner and a second time to place the
opposite corner.
 Left-click on the PMOS layer in the layer list to select it.
 Click again to add the PMOS rectangle.
 Press “Escape” to stop drawing rectangles.

If you didn’t place your rectangles exactly where you wanted, then you can always select it and delete it with the
delete key. Alternatively, you could press the “S” key to “stretch” an existing rectangle. After pressing the “S”
key, move the cursor over an edge of a rectangle, and you should see that it is highlighted. Click once to take hold
of the edge and a second time to place it in the new position. Do this now and save the design by
selecting Design→Save (or click the Save button, or press the F2 key). Then re-run DRC to make all of the
NIM/PIM errors go away. Remember to make the rectangles touch in the center. You could draw as many
rectangles as you wish, but it saves time and system memory to use as few rectangles as possible. You should be
able to make all NIM/PIM errors disappear with only one rectangle in each layer.

Once the NIM/PIM errors are resolved, fix the NW errors by adding a single NW rectangle in exactly the same
place as the PIM rectangle. Then add DUMMY rectangles to exactly over the left and right GATE shapes. These
should eliminate all remaining errors. Your layout should look like this:

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6.1. Other Ways to Create Shapes
Here are some other ways to create shapes that you may want to try:

 Path - You can draw a path by selecting the entry layer and then choosing Create→Interconnect (or press
"p"). Then click wherever you like in the layout. A minimum-width path will be drawn. This is mostly
convenient for higher levels of metal, which allow metal shapes to bend and don't usually have different width
rules for different routing directions.
 Copy - You can copy a shape or instance with the following steps:
1. Selecting the shape/instance
2. Choose Edit→Copy→Copy (or press "c")
3. Click on the shape/instance to set a reference point for the copy
4. Drag the mouse to the location of the copy
5. Click again to place the shape/instance
6. With the copied shape selected, you can change its layer by choosing Query→Property Editor (or
press the "Q" key), which will open a properties panel on the right. Click on the LPP (i.e. Layer-
Purpose Pair) field and change it to whatever you want. Then click the check-mark button at the
top of the property editor to accept the changes.

6.2. Add Remaining Wires and Power Rails

Now, let us add the remaining shapes for the inverter as follows. Start by adding BPR shapes for the VDD and
GND rails. Align these with the ACT shapes and make them as close as possible without creating any errors.

Then add via cells to connect BPR to M0A. Normally, you would the the O hot-key to place a via, but our vias
are not set up for this to work. Instead, press I as you would to create any instance and find the via cell named
BPR_M0A in the NCSU_TechLib_FreePDK3 library (where you found the pmos and nmos instances earlier).
Adding the via cell for the VDD power rail (above the PMOS) should be easy, but to add the via cell for the GND
rail (below the NMOS), you will need to flip it along the X axis. This can be done clicking the X-axis flip button
in the create-instance dialog-box, or by clicking on the orientation select box and changing it from R0 to MX.
If you place the BPR_M0A instance before rotating it, you can always select it and change its orientation by
pressing “Q” to open the Property Editor panel.

Next, add M0A rectangles or paths to connect the PMOS source nodes and the drain nodes of all devices. Finally,
add instances of the GATE_M0B and M0A_M0B via cells over the gate and drain nodes, respectively. Save and
re-run DRC to ensure that there are no errors. Your layout should look like the one below (with the NW, NIM,
and PIM layers invisible for clarity):

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7. Create Pins
Our last step is to create pins so that the nodes in our layout have names that are human-readable. Select the BPR
layer in the layers panel, and then create these pins in this layer by selecting Create→Pin→By Shape, or pressing
Ctrl-P. You should see bar labeled “Pin” appear near the top, as shown below.

It is possible that you may see a dialog box instead. Note that you can toggle between the dialog box and the bar
by clicking the button in the bar and the “Hide” button in the dialog box. Switch to the dialog-box view,
because we will need to set some options that are unavailable in the bar.
Type the names vdd!, gnd!, A, and Z in the “Names” text-box as shown below. Select the “Create Pin Label”
check-box and set “Type” to “Text”. Set the Height to 0.02 and Check “Auto Place”. Leave all other options as
they are.

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Next, click and drag a box on the layout where you want the vdd! pin to be placed. You should see the label drawn
in the center of your box. The shape of your rectangle doesn’t really matter, as long as it only covers area that is
already covered by BPR-drawing. Repeat this procedure for the gnd! pin. Before adding the A and Z pins, make
sure to change the entry layer to M0B-drawing. When you are done, your layout should look like the one below
(with one layout showing BPR and M0B only, and the other with NW, NIM, and PIM invisible for better clarity).
Important Note: It is absolutely essential that you select the Create Label box when you create each pin. The
label must be in the same layer as the metal shape and must overlap the shape. This is necessary to pass LVS. This
is not needed to finish Layout Tutorial #1; however, if you do not get into this habit now, then you will not be able
to finish Layout Tutorials #2 and #3.

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Congratulations! You have completed the tutorial. Save your design and take a screen-shot of your layout to turn
in with your assignment.
ECE 546Students: Hand-in this image of your layout. Make sure that your layout is as dense as
possible. Points will be deducted for layout that is larger than necessary.
8. Further Reading
If you would like to learn more about the layout editor, you can choose Help→Custom Compiler Help and
browse to the Custom Compiler Layout Editor User Guide, which is a good reference.

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