8051 INTERRUPTS

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 introduction

• interrupt: occurence of a condition (an event)

that causes a temporary suspension of a
program while the condition is serviced by
another program
• interrupt driven program: the interruption is
a response to an event that occurs
asynchronously with the main program
• it is not known when the program will be
interrupted

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 introduction (cont’d)

• Interrupt Service Routine (ISR) (interrupt

handler): a program that deals with an
interrupt
• main programs execute at base-level
(foreground)
• ISRs execute at interrupt-level (background)
• interrupt is asynchronous, not predictable

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introduction (cont’d)

without interrupts

with interrupts

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 8051 interrupt organization

• a total of 5 interrupt sources

• two external interrupts
• two timer interrupts
• a serial port interrupt
• all interrupts are disabled after a system
reset and are enabled individually by software

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enabling and disabling interrupts

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enabling and disabling interrupts (cont’d)

SETB ET1 ; enable Timer 1 interrupt

SETB EA ; set global enable bit

MOV IE, #10001000B

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enabling and disabling interrupts (cont’d)

SETB ET1 ; enable Timer 1 interrupt

SETB EA ; set global enable bit

MOV IE, #10001000B

initialization

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enabling and disabling interrupts (cont’d)

SETB ET1 ; enable Timer 1 interrupt

SETB EA ; set global enable bit

MOV IE, #10001000B

modifying on
the fly
initialization

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 interrupt priority
• ISR to be interrupted by another interrupt

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 polling sequence

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interrupt flag bits

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 processing interrupts

• interrupt accepted by CPU

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 processing interrupts

• interrupt accepted by CPU

• current instruction completes execution

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 processing interrupts

• interrupt accepted by CPU

• current instruction completes execution

• PC is saved on stack

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 processing interrupts

• interrupt accepted by CPU

• current instruction completes execution

• PC is saved on stack

• current interrupt status saved internally

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 processing interrupts

• interrupt accepted by CPU

• current instruction completes execution

• PC is saved on stack

• current interrupt status saved internally

• interrupts are blocked at the level of interrupt

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 processing interrupts

• interrupt accepted by CPU

• current instruction completes execution

• PC is saved on stack

• current interrupt status saved internally

• interrupts are blocked at the level of interrupt

• the PC is loaded with vector address of ISR

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 processing interrupts

• interrupt accepted by CPU

• current instruction completes execution

• PC is saved on stack

• current interrupt status saved internally

• interrupts are blocked at the level of interrupt

• the PC is loaded with vector address of ISR

• the ISR executes

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 processing interrupts (cont’d)

• ISR finises with RETI instruction

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 processing interrupts (cont’d)

• ISR finises with RETI instruction

• RETI retrieves old PC value from stack

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 processing interrupts (cont’d)

• ISR finises with RETI instruction

• RETI retrieves old PC value from stack

• RETI restores the old interrupt status

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 interrupt vectors

• interrupt accepted by CPU

• current instruction completes execution

• PC is saved on stack

• current interrupt status saved internally

• interrupts are block at the level of interrupt

• the PC is loaded with vector address of ISR

• the ISR executes

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 interrupt vectors

• the PC is loaded with vector address of ISR

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 interrupt vectors (cont’d)

• when vectoring to an interrupt, the flag that

caused the interrupt is cleared by hardware

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 interrupt vectors (cont’d)

• when vectoring to an interrupt, the flag that

caused the interrupt is cleared by hardware

• RI and TI for serial port interrupts has two

possible sources, so they must be tested and
cleared by software in ISR

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program design using interrupts

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program design using interrupts

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program design using interrupts

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program design using interrupts

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 small interrupt service routines

• 8 bytes within each

interrupt point

• do not overrun next ISR!

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 large interrupt service routines

• ISRs longer than 8 bytes

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 example: square wave

• use Timer 0 and interrupts for 10kHz square wave

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 example: square wave

• use Timer 0 and interrupts for 10kHz square wave

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 example: square wave

• use Timer 0 and interrupts for 10kHz square wave

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 example: two square waves
• use interrupts for simultaneos 7kHz and 500 Hz
square waves on P1.7 and P1.6

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 example: two square waves
• use interrupts for simultaneos 7kHz and 500 Hz
square waves on P1.7 and P1.6

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 example: two square waves
• use interrupts for simultaneos 7kHz and 500 Hz
square waves on P1.7 and P1.6

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 example: two square waves
• use interrupts for simultaneos 7kHz and 500 Hz
square waves on P1.7 and P1.6

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 serial port interrupts
• RI and TI for serial port interrupts has two
possible sources, so they must be tested and
cleared by software in ISR

• TI occurs when
transmission of character in
SBUF finishes

• RI occurs when a
character is completely
received in SBUF
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 example: character output
• continually transmit ASCII code set (excluding control
codes) via serial port using interrupts

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 example: character output
• continually transmit ASCII code set (excluding control
codes) via serial port using interrupts

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 example: character output
• continually transmit ASCII code set (excluding control
codes) via serial port using interrupts

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 example: character output
• continually transmit ASCII code set (excluding control
codes) via serial port using interrupts

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 example: character output
• continually transmit ASCII code set (excluding control
codes) via serial port using interrupts

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 example: character output
• continually transmit ASCII code set (excluding control
codes) via serial port using interrupts

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external interrupts

timer controls

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 example: furnace controller

P3.2

P3.3

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example: furnace controller (cont’d)

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example: furnace controller (cont’d)

on

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example: furnace controller (cont’d)

on

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example: intrusion warning system

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example: intrusion warning system (cont’d)

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example: intrusion warning system (cont’d)

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 interrupt timings

interrupts are
polled on the next
machine cycle

and latched

an interrupt is accepted if:

a) no equal or higher priority interrupt in progress
b) polling cycle is the last machine cycle of instruction
c) current instruction is not RETI or any access to IE or
IP
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interrupt timings (cont’d)

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 interrupt timings (cont’d)
interrupt latency assume
12 MHz crystal

best case = 3,25 sec

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 interrupt timings (cont’d)
interrupt latency assume
12 MHz crystal

best case = 3,25 sec

worst case = 9,25 sec

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 summary

• interrupt organization and vectors

• processing interrupts
• program design using interrupts

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references

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