Instructions for the Test

There are 50 questions in this question paper.

All questions carry 1 Mark each. There is no negative marking.

The time duration of the Test is 90 minutes.
There are 4 sections. All sections should be attempted.

Section Comments
Section 1 Aptitude
Section 2 Digital
Section 3 Analog/Backend
Section 4 Basics Electronics

Synopsys wishes you all the best

Aptitude

1. Two pipes M and N can fill a tank in 22 hours and 33 hours respectively. In how much time will the
tank be full if both the pipes are opened simultaneously?
(1) 18 hours
(2) 56/3 hours
(3) 12/11 hours
(4) 66/5 hours
1
2. If a packet containing three dozen glasses is dropped, which of the following CANNOT be the raio of
broken glasses to unbroken glasses?
(1) 4:3 (2) 5:1 (3) 1:2 (4) 11:7
1
3. Three numbers are in the ratio 3:4:5. The sum of the largest and the smallest equals the Sum of the
third and 52. The smallest number is
(1) 39 (2) 40 (3) 41 (4) 42
1
4. a/2 = b/3 = c/5, the value of (a+b+c)/c is
(1) 3 (2) 2 (3) 5 (4) 1/5
1
5. Two trains start from A & B and travel towards each other at speed of 50kmph and 60kmph resp. At
the time of the meeting the second train has traveled 120km more than the first. The distance between
them in km is
(1) 1322 (2) 1324 (3) 1220 (4) 1320
1
6. Sum of three even consecutive numbers is 48, and then least number is
(1) 20 (2) 18 (3) 16 (4) 14
1
7. A Cone and a sphere have equal radii and equal volumes. Find the ratio of the sphere of the diameter
of the sphere to the height of the cone
(1) 1.3 (2) 2.4 (3) 1.2 (4) 2.8
1
8. 13 sheeps and 9 pigs were bought for Rs. 1291.85.If the average price of a sheep be Rs. 74. What is
the average price of a pig.
(1) 32.65
(2) 36.65
(3) 36.85
(4) 38.65
1
9. In a certain office 1/3 of the workers are women ½ of the women are married and 1/3 of the married
women have children if ¾ of the men are married and 2/3 of the married men have children what part
of workers are without children?
(1) 12/18
 (2) 11/19
(3) 15/17
(4) 11/18
1
10. A man covers a distance on scooter. Had he moved 3 kmph faster he would have taken 40 min less. If
he had moved 2 kmph slower, he would have taken 40 min more. The distance is
(1) 50 km
(2) 40 km
(3) 36 km
(4) 45 km
1
Digital

11. A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle,
GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is turned on for
75 seconds. This traffic light must be implemented using a finite state machine (FSM). The only input
to this FSM is a clock of 5 second period) The minimum number of flip-flops required to implement this
FSM is _______
(1) 5 (2) 7 (3) 10 (4) 15
1
12. Consider the multiplexer-based logic circuit shown in the figure.

Which one of the following Boolean functions is realized by the circuit?

(1) WS1’S2’
(2) WS1 + WS2 + S1S2
(3) W’+S1+S2
(4) W^S1^S2
1
13. Figure shows a mod-M counter, Here M is equal to

(1) M =1
(2) M =2
(3) M =3
(4) M =4
1
14. A 0 to 6 counter consist of 3 flip-flops and a combination circuit of 2 input gate(s). The combination
circuit can be constructed using a minimum of
(1) one AND gate
(2) one OR gate
(3) one AND gate & one OR gate
(4) two AND gates
1
15.
Which of the following is the best method to connect unused input of a multi input AND gate.

(1) Connect Unused input to one of the used input.

(2) Connect unused input to Vcc.
(3) Left unused input floating
(4) All of the following
1
16.
What will be the maximum number of EPIs (Essential prime Implicants) for a 6 variable K-map?

(1) 32 (2) 31 (3) 64 (4) 63

1
17.
How many 2x1 multiplexers are required to build one 8 x 1 multiplexer?

(1) 5 (2) 6 (3) 7 (4) 8

1
18.
How are signed numbers commonly stored in memory?

(1) Using sign-magnitude notation

(2) Using 1’s complement
(3) Using 2’s complement
(4) Signed numbers cannot be stored
1
19.
How many flip flops are used in a ring counter with N states?

(1) N (2) 2N (3) log2(N) (4) 2N - 1

1
20. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A
changes after 10ns from 0 to 1 and it changes again from 1 to 0 at 20ns. At what time the value of
output B will be 1, if the transport delay model is used?
(1) 20 ns
(2) 30 ns
(3) 40 ns
(4) output will remain zero
1
21. A memory system of size 18 k bytes is to be designed using memory chips which have 12 address lines
and 4 data lines each. The number of such chips required to design the memory system is
(1) 12 (2) 9 (3) 8 (4) 18
1
22.
Net charge on a n-type semiconductor is:

(1) Positive
(2) Negative
(3) Neutral
(4) Cannot be determined
1
23. The minimum number of NAND gates required to implement the Boolean function ABCDE + ABCD +
ABC + AC + C is
(1) 0 (2) 1 (3) 4 (4) 7
1
24. In a DAC (Digital to Analog converter), the reference voltage is 25 volts. Find the analog output for the
 digital input 1011 (Base-2).
(1) 20.21 volts
(2) 19.25 volts
(3) 17.18 volts
(4) 21.25 volts
1
25. The Boolean expressions for Y when N is (i) even and (ii) odd are respectively

(1) (i)0 (ii)A

(2) (i)A (ii)0
(3) (i)A.B (ii)0
(4) (i)0 (ii)B
1
26. In the circuit shown, A and B are the inputs and F is the output. What is the functionality of the circuit?

(1) XOR (2) NOR (3) NAND (4) XNOR

1
27.
How does negative clock skew impact setup and hold timing?

(1) -ve clock skew tighten up hold requirements and relaxes setup requirements.
(2) -ve clock skew relaxes hold requirements and tighten up setup requirements.
(3) -ve clock skew relaxes both setup and hold time requirements.
(4) -ve clock skew tighten up both setup and hold time requirements.
1
28. The logic function f determined from the circuit shown below is______________
 (1) A
(2) A' + B'
(3) A'.B'
(4) (A + B) C'
1
29. For the FSM below, what is the state of the FSM after the input pattern ababbbabba is applied?

(1) 0 (2) 1 (3) 3 (4) 4

1
30.
Choose the correct option based on digital logic families.

(1) Fastest– CMOS , Least Power dissipation– Transistor-Transistor Logic(TTL).

(2) Fastest– Emitter Coupled Logic(ECL), Least Power dissipation– TransistorTransistor Logic(TTL)
(3) Fastest– Emitter Coupled LogicECL, Least Power dissipation- CMOS.
(4) Fastest– CMOS , Least Power dissipation– Emitter Coupled Logic(ECL).
1
Analog and Mixed Signal Design

31. Output voltage swing of a digital circuit shown in the figure comprising of MOSFETs (channel length
modulation accounted) along with required pull-up/pull-down resistors depends upon?

(1) Supply Voltage(Vdd), Transconductance of MOSFET(gm),

Value of pullup and pulldown resistors, Drain current(Id).
(2) Supply Voltage(Vdd), Overdrive Voltage of the MOSFETs(Vov), Transconductance of
 MOSFET(gm), Intrinsic Drain to Source resistance of the MOSFET(ro).
(3) Supply Voltage(Vdd), Overdrive Voltage of the MOSFETs(Vov),
Value of pullup and pulldown resistors, Drain Current(Id).
(4)
Supply Voltage(Vdd), Intrinsic Drain to Source resistance of the MOSFET(ro),
Value of pullup and pulldown resistors, parasitic capacitances.
1
32. In any CMOS circuit PVT (Process (P), supply Voltage (V) and operating Temperature(T)) can vary. For
Process 5 different corners are considered: SS (slow NMOS and slow PMOS), SF (slow NMOS, fast
PMOS), FS, FF and TT (Both typical PMOS and NMOS). Supply voltage varies between [Vmin,
Vmax, and temperature varies between [Tmin, Tmax]. If the circuit generally will pass for all other PVT
values, what value of PVT below must the circuit pass the hold check (hold violation free circuit)?
(1) SS,Vmin, Tmax
(2) SS, Vmin,Tmin
(3) FF, Vmax, Tmin
(4) FF,Vmin, Tmax
1
33.
The drawback of the BiCMOS circuit is?

(1) Sensitivity is less load capacitance

(2) Bipolar transistors are used for driving current to the load capacitance but not for the logic
operations
(3) Increased fabrication Complexity
(4) All the mentioned
1
34. In a power MOSFET, pinch-off occurs when (VDS is the drain to source voltage, VGS is the gate to
source voltage VT is the threshold voltage):
(1) VDS = VGS – VT
(2) VDS ≤ VGS - VT
(3) VDS ≥ VGS -VT
(4) VDS ≥ VGS -VT
1
35.
The CMRR of an ideal OP AMP is _____________

(1) Very Low

(2) Infinite
(3) Zero
(4) a & c are correct
1
36.
The time period of a monostable 555 multivibrator is?

(1) T = 0.33RC
(2) T = 1.1RC
(3) T = 3RC
(4) T = RC
1
37.
How to overcome mis-triggering on the positive pulse edges in the monostable circuit?

(1) Connect a RC network at the input

(2) Connect an integrator at the input
(3) Connect a differentiator at the input
(4) Connect a diode at the input
1
38. Each wire in a pair of 1 mm lines has capacitance of 0.08 fF/µm to ground and 0.12 fF/ µm to its
neighbor. Each line is driven by an inverter with a 1 kΩ effective resistance. Estimate the
contamination and propagation delays of the path. Neglect parasitic capacitance of the inverter and
resistance of the wires.
(1) 80ps, 320ps
 (2) 320ps, 80ps
(3) 80ps, 500ps
(4) 500ps, 320ps
1
39. What will be the output of the OPAMP if input=5 volts is applied while the supply voltages Vcc = 12 V,
Vdd = -12 volts & R2=2R1.

(1) 10 volts
(2) 15 volts
(3) 12 volts
(4) 5 volts
1
40. In the given figure an ideal current source is used for charge initially uncharged capacitor in series
with a resistor. Determine time constant of the circuit (in secs).

(1) 2.209
(2) 4.418
(3) 6.627
(4) None of the above
1
Basics of Electronics

41. For the given network assume R= 1K ohm. What is the value of Req

(1) (5+√2) Kohm

 (2) (2+√5)/3 Kohm
(3) (√5+1)/2 Kohm
(4) (√5-1)/3 Kohm
1
42. All the logic gates shown in the figure have propagation delay of 20 ns. Let A=C=0 and B=1 until time
t=0. At t=0, all the inputs flip (i.e. A=C=1 and B=0) and remain in that state. For t>0 , how much time
duration (in ns) will the output Z=1 ?

(1) 20 ns
(2) 40 ns
(3) 60 ns
(4) 80 ns
1
43. Find out the Boolean expression for Y in below circuit.

(1) A’B’+B’C’+A’D’+C
(2) AC+AB+BC+D’
(3) AC’+A’B’+B’C’+D
(4) A’C’+AB+BC+D’
1
44. What is the steady state value of Vout in the below circuit

(1) 5V (2) 1.66V (3) 2.5V (4) 3.3V

 1
45. In the circuit shown below

(1) LED turns ON when S2 & S3 both are closed

(2) LED turns ON when S2 & S3 both are open
(3) LED turns ON when one of S2 & S3 are closed
(4) LED doesn’t turn ON irrespective of Switch positions
1
46. Find the logical gate implemented by the following circuit

(1) XOR Gate

(2) AND Gate
(3) NAND Gate
(4) NOR Gate
1
47. In figure switch has been closed for long time and is opened at t=0. The Voltage (V) expression and
time constant for the circuit are

(1) (11-10e-0.3t) , 3/5 seconds

(2) (20-10e-0.6t) , 3/5 seconds
(3) (20-10e-0.6t ) , 5/3 seconds
(4) (11-10e-0.3t) , 5/3 seconds
1
48. For the below digital circuit, find the minimized (simplified/reduced) expression for Y

(1) A + B'
(2) A' + B'
 (3) A'+ B
(4) A + B
1
49. The resistance of a wire-A is 15Ω . Another wire-B of the same material & at the same temperature has
a diameter one-third as that of wire-A & a length twice as longer. What is the resistance of wire-B?
(1) 20 ohm
(2) 270 ohm
(3) 250 ohm
(4) 600 ohm
1
50. Using the small signal model of a MOSFET (neglecting body effect), find small signal output resistance
Rout from the adjoining figure. Vbiasis a DC voltage. Ibias is a DC current.

(1) gm1ro1ro2+ro2
(2)

(3)

(4) ro2||1/gm1
1
Answer Keys :
(1) 4 (2) 1 (3) 1 (4) 2 (5) 4 (6) 4 (7) 3 (8) 2 (9) 4 (10) 2 (11) 1 (12) 4 (13) 3 (14) 1 (15) 2 (16) 1 (17) 3 (18) 3
(19) 1 (20) 2 (21) 2 (22) 3 (23) 1 (24) 3 (25) 3 (26) 4 (27) 2 (28) 3 (29) 4 (30) 3 (31) 3 (32) 3 (33) 3 (34) 1
(35) 2 (36) 2 (37) 3 (38) 1 (39) 3 (40) 4 (41) 3 (42) 2 (43) 3 (44) 1 (45) 4 (46) 1 (47) 3 (48) 1 (49) 2 (50) 1
Solutions :
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)