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Script I Eee

The document outlines a series of commands for configuring power domains and floorplans for two groups, PDmac1 and PDmac2, in an electronic design automation context. It includes setting attributes, creating relative floorplans, adding halos and rings, and configuring power switches and stripes for various components. The commands are structured to manage the layout and connectivity of different modules within the design, ensuring proper power distribution and organization.

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hdhuy.tn
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
6 views6 pages

Script I Eee

The document outlines a series of commands for configuring power domains and floorplans for two groups, PDmac1 and PDmac2, in an electronic design automation context. It includes setting attributes, creating relative floorplans, adding halos and rings, and configuring power switches and stripes for various components. The commands are structured to manage the layout and connectivity of different modules within the design, ensuring proper power distribution and organization.

Uploaded by

hdhuy.tn
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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setObjFPlanBox Group PDmac1 200 1580 2160 2360

modifyPowerDomainAttr PDmac1 -minGaps 50 50 50 50


modifyPowerDomainAttr PDmac1 -rsExts 50 50 50 50
setObjFPlanBox Group PDmac2 200 200 2160 980
modifyPowerDomainAttr PDmac2 -minGaps 50 50 50 50
modifyPowerDomainAttr PDmac2 -rsExts 50 50 50 50

create_relative_floorplan -place
ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/ram2P1024x32 -
ref_type object -ref PDmac2 -horizontal_edge_separate {3 50 3}
vertical_edge_separate {0 50 0}

create_relative_floorplan -place
ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/ram2P1024x32 -
ref_type object -ref PDmac2 -horizontal_edge_separate {1 -50 1} -
vertical_edge_separate {0 50 0}

create_relative_floorplan -place
ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a -ref_type
object -ref PDmac2 -horizontal_edge_separate {3 50 3} -vertical_edge_separate {0
1000 0}

create_relative_floorplan -place
ethernet_mac_1/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/ram2P1024x32 -
ref_type object -ref PDmac1 -horizontal_edge_separate {3 50 3} -
vertical_edge_separate {0 50 0}

create_relative_floorplan -place
ethernet_mac_1/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/ram2P1024x32 -
ref_type object -ref PDmac1 -horizontal_edge_separate {1 -50 1} -
vertical_edge_separate {0 50 0}

create_relative_floorplan -place
ethernet_mac_1/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a -ref_type
object -ref PDmac1 -horizontal_edge_separate {3 50 3} -vertical_edge_separate {0
1000 0}

create_relative_floorplan -place dma_dut/dmamaster_dut/internal_memory/RAM4096x32 -


ref_type object -ref PDmac2 -horizontal_edge_separate {1 488.150 1} -
vertical_edge_separate {0 1000 0} -orient R90

addHaloToBlock 10 10 10 10
ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/ram2P1024x32

addHaloToBlock 10 10 10 10
ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/ram2P1024x32

addHaloToBlock 10 10 10 10
ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a

addHaloToBlock 10 10 10 10
ethernet_mac_1/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/ram2P1024x32

addHaloToBlock 10 10 10 10
ethernet_mac_1/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/ram2P1024x32
addHaloToBlock 10 10 10 10
ethernet_mac_1/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a

addHaloToBlock 10 10 10 10 dma_dut/dmamaster_dut/internal_memory/RAM4096x32

addPowerSwitch -column \-powerDomain PDmac1 \-enableNetOut


ethernet_mac_1/switch_enable_out_PDmac1 \-leftOffset 30 -bottomOffset 0 \-
horizontalPitch 72 \-checkerBoard \-loopBackAtEnd \-switchModuleInstance
ethernet_mac_1
addPowerSwitch -column \-powerDomain PDmac2 \-enableNetOut
ethernet_mac_2/switch_enable_out_PDmac2 \-leftOffset 30 -bottomOffset 0 \-
horizontalPitch 72 \-checkerBoard \-loopBackAtEnd \-switchModuleInstance
ethernet_mac_2

addRing -center 1 -stacked_via_top_layer Metal11 -type core_rings -jog_distance


0.24 -threshold 0.24 -nets {VDD VSS VDDm} -stacked_via_bottom_layer Metal1 -layer
{bottom Metal7 top Metal7 right Metal8 left Metal8} -width 10 -spacing 8 -offset
0.24

deselectAll
selectObject Group PDmac1
addRing -stacked_via_top_layer Metal11 -around power_domain -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets {VDDau VDDm VSS VDD} -
stacked_via_bottom_layer Metal1 \-layer {bottom Metal7 top Metal7 right Metal8 left
Metal8} -width 5 -spacing 5 -offset 7.5

deselectAll
selectObject Group PDmac2
addRing -stacked_via_top_layer Metal11 -around power_domain -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets {VDDlu VDDm VSS VDD} -
stacked_via_bottom_layer Metal1 \-layer {bottom Metal7 top Metal7 right Metal8 left
Metal8} -width 5 -spacing 5 -offset 7.5

deselectAll
selectInst dma_dut/dmamaster_dut/internal_memory/RAM4096x32
setAddStripeMode -ignore_nondefault_domains 1
addStripe -block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.44 \-
padcore_ring_bottom_layer_limit Metal7 -set_to_set_distance 144 \-
break_at_selected_blocks 1 -stacked_via_top_layer Metal11 \-
padcore_ring_top_layer_limit Metal9 -spacing 2 -xleft_offset 22 \-
merge_stripes_value 0.24 -layer Metal8 -block_ring_bottom_layer_limit Metal7 \-
width 5 -nets {VDD VSS} -stacked_via_bottom_layer Metal1
setAddStripeMode -ignore_nondefault_domains 0

deselectAll
selectInst ethernet_mac_1/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/
ram2P1024x32
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets VDDm -stacked_via_bottom_layer Metal1 \-
layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 3 -spacing 3.5

deselectAll
selectInst ethernet_mac_1/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets VDDm -stacked_via_bottom_layer Metal1 \-
layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 3 -spacing 3.5

deselectAll
selectInst ethernet_mac_1/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets VDDm -stacked_via_bottom_layer Metal1 \-
layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 3 -spacing 3.5

deselectAll
selectInst ethernet_mac_1/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_1/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
selectObject Group PDmac1

addStripe -block_ring_top_layer_limit Metal3 -max_same_layer_jog_length 0.44 \-


over_power_domain 1 -padcore_ring_bottom_layer_limit Metal1 -set_to_set_distance
144 \-break_at_selected_blocks 1 -stacked_via_top_layer Metal11 -
padcore_ring_top_layer_limit Metal3 \-spacing 2 -xleft_offset 138 -
merge_stripes_value 0.24 -layer Metal8 \-block_ring_bottom_layer_limit Metal1 -
width 3 -nets {VDDm VSS VDDau} -stacked_via_bottom_layer Metal1

deselectAll
selectInst ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/
ram2P1024x32
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets VDDm -stacked_via_bottom_layer Metal1 \-
layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 3 -spacing 3.5

deselectAll
selectInst ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets VDDm -stacked_via_bottom_layer Metal1 \-
layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 3 -spacing 3.5

deselectAll
selectInst ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets VDDm -stacked_via_bottom_layer Metal1 \-
layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 3 -spacing 3.5

deselectAll
selectInst ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
selectObject Group PDmac2

addStripe -block_ring_top_layer_limit Metal3 -max_same_layer_jog_length 0.44 \-


over_power_domain 1 -padcore_ring_bottom_layer_limit Metal1 -set_to_set_distance
144 \-break_at_selected_blocks 1 -stacked_via_top_layer Metal11 -
padcore_ring_top_layer_limit Metal3 \-spacing 2 -xleft_offset 138 -
merge_stripes_value 0.24 -layer Metal8 \-block_ring_bottom_layer_limit Metal1 -
width 3 -nets {VDDm VSS VDDlu} -stacked_via_bottom_layer Metal1

deselectAll
selectInst ethernet_mac_1/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_1/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_1/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
selectObject Group PDmac1

addStripe -max_same_layer_jog_length 0.8 -over_power_domain 1 \-pin_layer TOP -


over_pins 1 -skip_via_on_pin {} -break_at_selected_blocks 1 \-master HSWX1 -
max_pin_width 5.0 -pin_offset -2.80 \-stacked_via_top_layer Metal9 -
merge_stripes_value 0.1 \-layer Metal8 -width 3 -nets {VDDm} -
stacked_via_bottom_layer Metal1 -spacing 2.5

deselectAll selectInst
ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/ram2P1024x32
selectInst ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
selectObject Group PDmac2

addStripe -max_same_layer_jog_length 0.8 -over_power_domain 1 \-pin_layer TOP -


over_pins 1 -skip_via_on_pin {} -break_at_selected_blocks 1 \-master HSWX1 -
max_pin_width 5.0 -pin_offset -2.80 \-stacked_via_top_layer Metal9 -
merge_stripes_value 0.1 \-layer Metal8 -width 3 -nets {VDDm} -
stacked_via_bottom_layer Metal1 -spacing 2.5

deselectAll
selectInst ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
selectObject Group PDmac2

addStripe -block_ring_top_layer_limit Metal3 -max_same_layer_jog_length 0.44 \-


over_power_domain 1 -padcore_ring_bottom_layer_limit Metal1 -set_to_set_distance
144 \-break_at_selected_blocks 1 -stacked_via_top_layer Metal11 -
padcore_ring_top_layer_limit Metal3 \-spacing 2 -xleft_offset 138 -
merge_stripes_value 0.24 -layer Metal8 \-block_ring_bottom_layer_limit Metal1 -
width 3 -nets {VDDm VSS VDDlu} -stacked_via_bottom_layer Metal1

deselectAll
selectInst ethernet_mac_2/rx_fifo_module_to_dma/data/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/tx_fifo_module_from_dma/fifo1/dual_port_ram_4_tx_fifo/
ram2P1024x32
selectInst ethernet_mac_2/rx_fifo_module_to_dma/pkt_cntr/dual_port_ram_4_tx_fifo/a
selectObject Group PDmac2

addStripe -max_same_layer_jog_length 0.8 -over_power_domain 1 \-pin_layer TOP -


over_pins 1 -skip_via_on_pin {} -break_at_selected_blocks 1 \-master HSWX1 -
max_pin_width 5.0 -pin_offset -2.80 \-stacked_via_top_layer Metal9 -
merge_stripes_value 0.1 \-layer Metal8 -width 3 -nets {VDDm} -
stacked_via_bottom_layer Metal1 -spacing 2.5

addStripe -block_ring_top_layer_limit Metal9 -max_same_layer_jog_length 0.44 \-


padcore_ring_bottom_layer_limit Metal7 -set_to_set_distance 250 -
stacked_via_top_layer Metal11 \-padcore_ring_top_layer_limit Metal9 -spacing 0.2 -
xleft_offset 150 -merge_stripes_value 0.24 \-layer Metal8 -
block_ring_bottom_layer_limit Metal7 -width 5 -area {33.1565 27.065 1195.1805
2532.965} \-nets VDDm -stacked_via_bottom_layer Metal1

sroute -connect { blockPin corePin } -layerChangeRange { Metal1 Metal11 } \-


blockPinTarget { nearestRingStripe nearestTarget } -padPinPortConnect { allPort
oneGeom } \-checkAlignedSecondaryPin 1 -powerDomains { PDmac1 } -blockPin useLef -
allowJogging 1 \-crossoverViaBottomLayer Metal1 -allowLayerChange 1 -
targetViaTopLayer Metal11 \-crossoverViaTopLayer Metal11 -targetViaBottomLayer
Metal1 -nets { VDDau VSS }

sroute -connect { blockPin corePin } -layerChangeRange { Metal1 Metal11 } \-


blockPinTarget { nearestRingStripe nearestTarget } -checkAlignedSecondaryPin 1 \-
powerDomains { PDmac2 } -blockPin useLef -allowJogging 1 -crossoverViaBottomLayer
Metal1 \-allowLayerChange 1 -targetViaTopLayer Metal11 -crossoverViaTopLayer
Metal11 \-targetViaBottomLayer Metal1 -nets { VDDlu VSS }

deselectAll
selectInst dma_dut/dmamaster_dut/internal_memory/RAM4096x32
addRing -stacked_via_top_layer Metal11 -around selected -jog_distance 0.24 -
threshold 0.24 \-type block_rings -nets {VDD VSS} -stacked_via_bottom_layer
Metal1 \-layer {bottom Metal7 top Metal7 right Metal8 left Metal8} -width 2 -
spacing 2

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