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6.004 - First Day Package

The document outlines the MCT 505 course on Microcomputers and Microprocessor Systems at the Air Force Institute of Technology for the 2024/2025 academic session. It includes details about the lecturer, prerequisites, grading breakdown, course objectives, learning outcomes, and a schedule of topics to be covered over 12 weeks. Students are expected to complete group assignments, a design project, and attend lectures to qualify for examinations.

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4 views3 pages

6.004 - First Day Package

The document outlines the MCT 505 course on Microcomputers and Microprocessor Systems at the Air Force Institute of Technology for the 2024/2025 academic session. It includes details about the lecturer, prerequisites, grading breakdown, course objectives, learning outcomes, and a schedule of topics to be covered over 12 weeks. Students are expected to complete group assignments, a design project, and attend lectures to qualify for examinations.

Uploaded by

tijaniabdqudus001
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Mechatronic Engineering Department

Air Force Institute of Technology, Kaduna


First Semester, 2024/2025 Academic Session
MCT 505: Microcomputers and Microprocessor Systems
1. Staff:
Lecturer(s):
SN NAME Phone No. Email
1. Dr. Ameer Mohammed 07031278949 [email protected];
[email protected]
Office Hours: Thursday (0800 – 1000 hrs)

Pre-requisite: MCT 310 (Computer Hardware Engineering); MCT 409 (Digital Systems and
PLCs).
Programming prerequisites: Some experience programming with MATLAB is recommended
(we will use MATLAB in this course.) MATLAB will require the use of a 64-bit computer.
Lectures: 12 Weeks [L].
Required Reading Material: MCT 505 Lecture Notes/Slides (to be provided).
Reference Book(s):
Computer Organization and Design: The Hardware/Software Interface" by David A. Patterson
and John L. Hennessy. 1

2. Grading and Course Mechanics


The course grade will be established according to the following breakdown:
Group Assignment (Presentation) 10%
Mid-Term Test 10%
Design Project 10%
Examination (or Test) 70%
Mid-Term Test: To be scheduled after week five.
Final Examination: To be scheduled at the end of the semester.
Attendance: We expect students to attend the lectures (and tutorials); 75% attendance qualifies
students to sit for the test and final examination.

1
A number of other books and online materials were consulted in the process of preparing the lecture material.

1
Group Assignment/Presentation: Give a 15 minutes presentation on the following topics. The
topics for the various groups are as follows:

Groups Topic
Group A Virtual Memory
Group B Devices and Interrupts
Group C System Level Communication and Interfaces
Group D Parallel processing
Design Project: details to be decided.
Course Objectives:
On completion of this course, students will be able to
• Understand the role of abstraction in the design of large digital systems, and explain the
major software and hardware abstractions in contemporary computer systems.
• Analyze the performance of digital systems using measures such as latency and throughput.
• Design simple hardware systems based on a variety of digital abstractions such as ROMs
and logic arrays, logic trees, state machines, pipelining, and buses. synthesize digital
systems from a library of representative components and test the designs under simulation.
• Understand the operation of a moderately complex digital system – a simple RISC-based
computer – down to the gate level, and be able to synthesize, implement, and debug its
components.
• Appreciate the technical skills necessary to be a capable digital systems engineer.
Learning Outcomes:
Upon completion of this course, students will be able to
• Identify flaws and limitations in simple systems implemented using the static discipline
(noise assumptions, etc).
• Identify flaws and limitations in simple systems implemented using clocked registers with
asynchronous inputs (metastability issues).
• Identify flaws and limitations in simple systems implemented using pipelined processors
(pipeline hazards).
• Identify flaws and limitations in simple systems implemented using semaphores for
process synchronization (deadlocks).
• Identify flaws and limitations in simple systems implemented using shared-memory
multiprocessors (sequential inconsistency).
• Characterize the logic function of combinational devices using CMOS, ROM, or PLA
technologies.
• Explain synthesis issues for combinational devices using CMOS, ROM, or PLA
technologies from their functional specification.
• Explain synthesis of acyclic circuits from combinational components.
• Calculate performance characteristics of acyclic circuits with combinational components.

2
• Explain and calculate performance characteristics of single-clock sequential circuits.
• Design, debug, and test combinational circuits of the complexity of an arithmetic logic unit.
• Design, debug, and test a controller for a finite-state machine.
• Pipeline a combinational circuit for improved throughput.
• Understand issues affecting microprocessor instruction set design.
• Complete and debug the design of a simple CPU with a given RISC-based intruction set.
• Measure the memory access performance of a processor, and tune cache design parameters
to improve performance.
• Analyze the operation of page-based virtual memory systems.
• Translate simple programs from C to machine language.
• Deduce processor state from a memory snapshot during execution.
Course Content, Schedule and Calendar:
Week Mon. (13:00- 15:00) Wed. (12:00 – 13:00)
1 Basics of Information Digital Abstraction
2 CMOS Technology Combinational Logic
3 Combinational Logic
4 Sequential Logic Finite State Machines
5 Performance Measures Design Trade-Offs
6 Programmable Machines Mid-Term Test
7 Assembly Language Assembly Language
8 Compilers Compilers
9 Procedures and Stacks
10 Caches and The Memory Hierarchy Pipelining the Beta
11 GROUP PRESENTATION
12
EXAMINATION
13

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