DIGITAL LOGIC DESIGN

( CE_118 )

Hardware Description Language

Verilog
 Objective
• Describe what is the lexical convention
• Describe the data types allowed in Verilog
• Describe the module port rule allowed in Verilog
• Describe what is the dataflow modeling
• Describe how to use continuous assignments
• Describe how to use procedural assignments
• Describe the operation of the operators used in Verilog
• Describe the operands may be used associated with a specified
operator
 Content
• Lexical convention

• Data Types

• Module Port Rule

• Dataflow modeling

• Expression, operator, operand

• Continuous assignment

• Procedural assignment
 How to represent Hardware?
• Classical design method
- Schematic
- Hand-draw or machine-draw
• Computer-based language method
- Hardware Description Language (HDL): Verilog, VHDL
- Fast, popularly used to design complex circuit with large and very
large scale

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 Module
• Module is the basic building block in Verilog
- Can be an element or a collection of lower-level design blocks

- Provide functionality for higher-level block through its port

interface

- Hide internal implementation

- Is used at many places in the design

- Allows designers modify module internals without effecting the

rest of design

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Module
Example: 4-bit Ripple Carry Counter

Ripple Carry Counter Module T-flipflop

Module

Module

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Design Hierarchy
Module
 Module description
module module name ( port name, port name,…);
module_port declaration
module
data type declaration
logic description part
A part of a chip, or
endmodule the whole chip

A module definition

The file name for RTL source must be

“module name.v”

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 Lexical convention
• Operator

• White space

• Comment

• Number

• String

• Identifier

• Keyword
 Lexical convention
• Verilog is a case-sensitive language.
• Whitespace: \b blank, \t tab, \n new line
• Comment: /*..*/ or //……..
• Operator: unary, binary, ternary
a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

• Keywords: module, end module, input, output, inout,

wire, reg, …

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 Lexical convention
• Number
- Two forms to express numbers:
* 37 : 32 bit decimal 37, or
* <size>’<base_format><number>
Ex:
10’hFA 10 bits hexadecimal number FA (00_1111_1010)
1’b0 1 bit binary number 0 (0)
6’d30 6 bits decimal number (011110), decimal 30
15’o10752 15 bits octal number (001,000,111,101,010),
decimal 4586
4’b0 is equal to 4’b0000
4’b1 is equal to 4’b0001
4’bz is equal to 4’bzzzz
4’bx is equal to 4’bxxxx
-8 ’d 6 The two’s complement of 6, held in 8 bits

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 Lexical convention
• Strings are stored as a sequence of 8 bit ASCII values
• Strings are variables of reg type

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 Lexical convention
• Identifier:
– specified by a letter or underscore followed by more letter or
digits, or signs ($, _).
– The first character must NOT be a digit or $; it can be a letter or
an underscore
– Identifiers are case sensitive.
– Identifier can up to 1024 characters
– Example:
• shiftreg_a
• busa_index
• error_condition
• merge_ab
• _bus3
• n$657
 Data Types
• Value set:
– 0 - represents a logic zero, or false condition
– 1 - represents a logic one, or true condition
– x - represents an unknown logic value
– z - represents a high-impedance state
• Net
• Variable
• Vector
• Array
• Memory
• Parameter
 Data types
2 main groups: Net and Variable
• Net represents physical connections between structural entities,
such as gates.
- Net does not store a value, except “trireg” net
- Default value is z (trireg default value is x)
- Net types:

(Ref. Verilog IEEE book for detail of net types)

Ex:
- wire w1, w2; //declare 2 wires
- wand w;
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 Data types
• Variable: hold a value until another value assigned to it
- Used in behavioral description (procedural assignment)
reg : unsigned integer variables of varying bit width
integer : 32-bit signed integer
time : 64-bit unsigned integer
real : signed floating-point
realtime: store time as a real value
- reg, time, integer (default value is x),
real , realtime (default value is 0)

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 Data Types
• Registers
– an abstraction of a data storage element
– keyword for the register data type is reg.
– A register stores a value from one assignment to the next.
– The default initialization value for a reg data type is the unknown
value, x.
– Example:
reg reset;
initial begin
reset = 1’b1;
#100 reset = 1’b0;
end
 Data types

• Vector: Multiple net or reg data types are declared by

specifying a range, is known as a vector

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 Data types
• Array declaration for a net or variable that is either scalar or
vector

• Memory: is one-dimension array with element of type reg.

These memories can be used to model ROM, RAM, or reg files
Example:
reg mem1bit [0:1023];
reg [16:0] membyte [0:1023];
assign rdata = membyte[969];
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 Data Types

• Parameters
– Verilog parameters do not belong to either the net or variable
group, they are constants
– Syntax:
• <parameter_declaration> = parameter <list_of_assignments>;
– Example:
parameter msb = 7; // defines msb as a constant value 7
parameter e = 25, f = 9;// defines two constant numbers
parameter average_delay = (r + f) / 2;
parameter byte_size = 8, byte_mask = byte_size - 1;
parameter r = 5.7; //declares r as a ’ real’ parameter
 Expression, operator, operand
• expression = operators + operands
– Operators
– Operands
 Expression: Operands

▪ Constant number or string Constant

▪ Parameter
▪ Net
▪ Variable (reg, integer, time, real, realtime)
Data types
▪ Array element
▪ Bit-select or part-select (not for real, realtime)
▪ Function call that returns any of the above

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 Expression: Operators

Arithmetic + - * / % **
Logical ! && ||
Logical equality == !=
Case equality === !===
Bitwise ~ & | ^ ^~ (or ~^)
Relational < > >= <=
Unary reduction & ~& | ~| ^ ^~ (or ~^)
Shift << >> <<< >>>
Concatenation {}
Replication {{}}
Condition ?: Ref. book for detail of
each operator!
Unary + - 22
 Level of modeling

 There are different ways of modeling a hardware design. Choose an

appropriate model to design Combinational or Sequential Circuit.
 Some books do not classify Dataflow modeling as a separate modeling
type.
 Structural model

• Structural
- Explicit structure of the circuit
- How a module is composed as an interconnection of more primitive
modules or components
- E.g. Each logic gate initially instantiated and connected to others

• In Verilog, a structural model consists of:

- List of connected components
- Like schematics, but using text: netlist
- Boring when write, and hard to decode
- Essential without integrated design tools

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 Structural model
• Structural Models are built from gate primitives,
switches, and other modules
• Describe the logic circuit using logic gates

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 Structural model
• Primitive gates:
 12 primitive logic gates predefined in the Verilog HDL

 Advantanges:
✓ Gates provide a much closer one-to-one mapping
between the actual circuit and the model.
✓There is no continuous assignment equivalent to the
bidirectional transfer gate. 26
 Structural model

Example:
t1
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
t2
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;
t3 // Instantiate logic gate primitives
xor (s1, a, b);
Full adder 1-bit and (c1, a, b);
xor (sum, s1, c_in);
and (c2, s1, c_in);
xor (c_out, c2, c1);
endmodule
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 Behavioral model
• What is Behavioral model ?
– More like a procedure in a programming language, but NOT.

– Program describes input/output behavior of circuit, tell what you

want to have happen, NOT what gates to connect to make it happen.

– Describe what a component does, not how it does

– Many structural models could have the same behavior

(different implementations of one expression)

– Synthesized into a circuit that has this behavior

– Result is only as good as the tools

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 Behavioral model
• Why behavioral model?
– Good for more abstract models of circuits
– Easier to write
– More flexible
– Provide sequencing
– A much easier way to write testbenches
– Allow both model and the testbench to be described together

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 Assignments
• The continuous assignment
– assigns values to nets
• The procedural assignment
– assigns values to registers
 Continuous assignment

• Drive a value onto a net

assign out = i1 & i2; //out is net; i1 and i2 are nets
Left-hand side Right-hand side
Net (vector or scalar) Net, register, function call
Bit-select or part-select of a vetor net (any expression that gives
Concatenation of any of the above a value)

• Always active
• Delay value: control time when the net is assigned value
assign #10 out = in1 & in2; //delay of performing computation,
//only used by simulator, not synthesis
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 Continuous assignment
Examples:
wire out = in1 & in2; //scalar net
//implicit continuous assignment, declared only once
assign addr[15:0] = addr1_bits[15:0] ^ addr2_bits[15:0]; //vector net
assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in; //concatenation

module adder (sum, carry_out, carry_in, ina, inb);

output [3:0] sum;
output carry_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum, ina, inb;
assign {carry_out, sum} = ina + inb + carry_in;
endmodule
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 Continuous assignment

 Because the assignment is done always, exchanging the

written order of the lines of continuous assignments has no
influence on the logic
 Common error

- Not assigning a wire a value

- Assigning a wire a value more than one
 Target (LHS) is NEVER a reg variable
(LHS: Left-Hand Side)

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 Procedural Assignment
• Assign value to variable data types
Left-hand side Right-hand side
- reg, integer, time, real, realtime Net, variable, function
- Bit-select, part-select of reg, integer, time call (Any expression that
- Memory word evaluates a value)
- Concatenation of any of the above

 Occur in procedures: initial, always, task, and function

 Being thought of as “triggered” assignment
 Variable hold value until the next assignment
Examples:
reg[3:0] a = 4'h4;
//This is equivalent to writing
reg[3:0] a;
initial a = 4'h4;
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 Procedural assignment
 Difference between Continuous and Procedural assignment:

- Continuous assignments drive nets, nets are evaluated

and updated whenever an input operand changes value.
- Procedural assignments update the value of variables
under the control of the procedural flow constructs that
surround them

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 Procedural assignment
• 2 types of procedural assignment:
blocking and non-blocking procedural assignment
-> specify different flow in a sequential block

Blocking procedural assignment

a_sig = b_sig;
Procedural Execution of the next line is blocked
assignment until this assignment is done.

Nonblocking procedural assignment

Assignment is done a_sig <= b_sig;
depending on Execution of the next line is not
procedure. blocked by this line

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 Procedural assignment
• Example

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 Initial & Always
• Two basic components of behavioral
modeling: initial, always construct.

• Each initial and always construct starts a

separate activity flow in Verilog.

• initial and always can not be nested.

• In the code: initial and always start together at

simulation time 0, initial executes once, always
executes repetitively.

• They contain behavioral statements like:

procedural assignment, if…else, case, loop
statements.

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 Initial
• Variable and Net can be initialized when they are declared
module adder (sum, co, a, b, ci);

output reg [7:0] sum = 0; //Initialize 8 bit output sum

output reg co = 0; //Initialize 1 bit output co
input [7:0] a, b;
input ci;
…..
endmodule

module adder (output reg [7:0] sum = 0,

output reg co = 0,
input [7:0] a, b,
input ci );
//it is illegal to redeclare any ports of the module
//in the body of the module
…
endmodule
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 Always
• always may be followed by timing control expression
(@, #, wait -> see later)
• Statement following always is executed repeatedly until
simulation stops. $stop or $finish to halt the simulation
module clock_gen (output reg clock);
//Initialize clock at time zero
initial
clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always
#10 clock = ~clock;
initial
#1000 $finish;
endmodule

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 Procedural timing control

• How does the behavioral model advance time?

– Delay control #: delay a specific amount of time
– Event control @: delay until an event occurs
(“posedge”, “negedge”, or any change)
- edge-sensitive timing control
– Statement wait: delay until an event occur
- level-sensitive timing control
• In Verilog, if there are no timing control statements, the
simulation time does not advance.

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 Procedural timing control
• Examples:
//delay-based timing control
#10 rega = a+b;
reg a = #10 a+b; //intra-assignment delay

//event-based timing control

• @(clock) q = d; //q = d is executed whenever signal clock changes value
• @(posedge clk) q=d;
• q = @(posedge clock) d;
• @(a, b, c) y = (a & b) | (b & c) | (a & c); //equivalent @(a or b or c)
• @(*) // or @*, equivalent to @ (a or b or c or d or f)
y = (a & b) | (c & d) | myfunction(f);

//wait control
wait (!enable) #10 a = b;

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 Procedural timing control

waiting for signal in the

• Using with always statement: sensitivity list change.
always @ (………..)
always begin
begin

sensitive list

end end
always creates By adding “@ ( )” to always statement: means
an infinite loop “wait for change of signals listed in the sensitivity
list” and when the change takes place, sequential
block ( from begin to end ) is executed.
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 Procedural timing control

• Using with always statement:

negedge: transition from 1 to x, z, or 0,
always @ (………..) and from x or z to 0
posedge: transition from 0 to x, z, or 1,
begin sensitive list and from x or z to 1

description timing
always @ ( posedge clk ) when signal clk rises

always @ ( negedge rst_n ) when signal rst_n falls

always @ ( a or b ) when signal a or b change

end
Do not mix single-edge
(posedge / negedge) and
double-edge event in an always @ ( a or posedge clk )
event control.
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 Examples
• 4-bit counter
module counter(Q , clock, clear);
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;

always @( posedge clear or negedge clock)

begin
if (clear)
Q <= 4'd0; //Nonblocking assignments are recommended
//for creating sequential logic such as flipflops
else
Q <= Q + 1; // Modulo 16 is not necessary because Q is a
// 4-bit value and wraps around.
end
endmodule

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