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C++SystemC CoSimulation Assignment

The assignment focuses on understanding hardware/software co-simulation using SystemC with Verilog and SystemVerilog. It includes tasks such as running co-simulation examples, simplifying code, documenting findings, and comparing different approaches. Deliverables include a modified project folder, a slide presentation, and a README summarizing the project setup and results, with a submission deadline of May 23, 2025.

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rohitadwani365
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14 views3 pages

C++SystemC CoSimulation Assignment

The assignment focuses on understanding hardware/software co-simulation using SystemC with Verilog and SystemVerilog. It includes tasks such as running co-simulation examples, simplifying code, documenting findings, and comparing different approaches. Deliverables include a modified project folder, a slide presentation, and a README summarizing the project setup and results, with a submission deadline of May 23, 2025.

Uploaded by

rohitadwani365
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment: SystemC Co-Simulation Project

SystemC Co-Simulation Assignment

Objective:

This assignment will help you understand real-world hardware/software co-simulation using SystemC with

both Verilog (via VPI) and SystemVerilog (via UVM-ML). You will:

- Run and analyze two different SystemC co-simulation examples.

- Simplify and document one of them.

- Present your insights through a well-structured slide deck.

Part A - SystemC + Verilog via VPI (Kenji-Ishimaru/sysc_iv_sample)

Tasks:

1. Setup and Execution

- Clone the repo: https://github.com/Kenji-Ishimaru/sysc_iv_sample

- Run the co-simulation using run_iv.sh

- Open and interpret the waveform using GTKWave

- Document the run and its output

2. Simplify the Code

- Merge testbench and module into a single main.cpp

- Replace DUT with a simple Verilog adder (or similar logic)

- Remove unused files and interfaces (minimal VPI)

- Keep signal communication clear and annotated

3. Document in Slides

- Architecture overview

- Signal flow between SystemC and Verilog

- Purpose of each file/module


Assignment: SystemC Co-Simulation Project

- What you simplified and why

- Waveform and output examples

Part B - SystemC + SystemVerilog with UVM-ML (prod_cons/sc_sv)

Repository:

https://github.com/doswellf/combinator-uvm/tree/master/uvm_ml/1.3/UVM_ML-1.3/ml/examples/demos/prod_

cons/sc_sv

Tasks:

1. Explore the Producer-Consumer Demo

- Understand the structure and role of SystemC vs. SV

- Identify communication points between languages

- Build and run the example (basic simulation)

2. Explain Its Architecture

- What is being simulated and verified?

- What role does UVM-ML play?

- Diagram the communication and flow of control

3. Compare Approaches (A vs. B)

- Language interface: VPI vs. UVM-ML TLM

- Complexity and setup effort

- Practical use cases for each approach

Deliverables:

1. Modified project folder (sysc_iv_sample)

2. Slide presentation (10-14 slides) - PDF or PowerPoint

3. A README.txt in your simplified project directory summarizing:


Assignment: SystemC Co-Simulation Project

- How to run your simplified version

- Key simplifications and their motivation

- Output and results

Evaluation Criteria:

Execution and correctness (Part A + B): 25 marks

Code simplification and clarity (Part A): 25 marks

Technical understanding (Part B explanation): 20 marks

Slide quality and explanation: 20 marks

Comparison and critical thinking: 10 marks

Submission Deadline: 23rd May 2025 (Friday), 11:59 PM

Submit all files in a compressed .zip or .tar.gz archive via the course LMS or email.

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