UNIT-III (Part 5)

A) Instruction Formats

A computer will usually have a variety of instruction code formats. It is the

function of the control unit within the CPU to interpret each instruction code and
provide the necessary control functions needed to process the instruction.

The format of an instruction is usually depicted in a rectangular box symbolizing

the bits of the instruction as they appear in memory words or in a control register.
The bits of the instruction are divided into groups called fields.

The most common fields found in instruction formats are:

1. An operation code field that specifies the operation to be performed. 2. An

address field that designates a memory address or a processor register.

3. A mode field that specifies the way the operand or the effective address is
determined.

Operation code field

The operation code field of an instruction is a group of bits that define various
processor operations, such as add, subtract, complement, and shift.

Mode field

The bits that define the mode field of an instruction code specify a variety of
alternatives for choosing the operands from the given address. The various
addressing modes that have been formulated for digital computers are presented in
next part.

Address Field

Operations specified by computer instructions are executed on some data stored in

memory or processor registers. Operands residing in memory are specified by their
memory address. Operands residing in processor registers are specified with a
register address.

Address field of an instruction format provides the address from where operands
are to be fetched. Some instruction may have multiple address fields. Here we are
showing the effect of including multiple address fields in an instruction.

Computers may have instructions of several different lengths containing varying

number of addresses. The number of address fields in the instruction format of a
computer depends on the internal organization of its registers. Most computers fall
into one of three types of CPU organizations:

1. Single accumulator organization.

2. General register organization.

3. Stack organization.

Single accumulator organization

In This format all operations are performed with an implied accumulator register.
The instruction format in this type of computer uses one address field.

For example, the instruction that specifies an arithmetic addition is defined by an

assembly language instruction as

ADD X

Where X is the address of the operand. The ADD instruction in this case results in
the operation

AC  AC + M [X].

AC is the accumulator register and M [X] symbolizes the memory word located at
address X.
General register organization

The instruction format in this type of computer needs three register address fields.
Thus the instruction for an arithmetic addition may be written in an assembly
language as

ADD R 1 , R 2 , R3

To denote the operation

R 1  R2 + R3

The number of address fields in the instruction can be reduced from three to two if
the destination register is the same as one of the source registers. Thus the
instruction

ADD R 1 , R2

Would denote the operation

R 1  R 1 + R2

Only register addresses for R 1 and R2 need be specified in this instruction.

General register-type computers employ two or three address fields in their
instruction format. Each address field may specify a processor register or a
memory word. An instruction symbolized by

ADD R 1 , X

Would specify the operation

Rl  Rl + M[X]

It has two address fields, one for register R 1 and the other for the memory address
X.

Stack organization

Computers with stack organization would have PUSH and POP instructions which
require an address field. Thus the instruction PUSH X will push the word at
address X to the top of the stack. The stack pointer is updated automatically.
Operation-type instructions do not need an address field in stack-organized
computers. This is because the operation is performed on the two items that are on
top of the stack.

The instruction ADD in a stack computer consists of an operation code only with
no address field. This operation has the effect of popping the two top numbers
from the stack, adding the numbers, and pushing the sum into the stack. There is
no need to specify operands with an address field since all operands are implied to
be in the stack.

Example 1: Evaluate the arithmetic statement X = (A + B) • (C + D) using zero,

one, two, or three address instructions. Use the symbols ADD, SUH, MUL, and
DIV for the four arithmetic operations; MOV for the transfer-type operation; and
LOAD and STORE for transfers to and from memory and AC register.

Sol: Assume that the operands are in memory addresses A, B, C, and D, and the
result must be stored in memory at address X.

Three-Address Instructions

Computers with three-address instruction formats can use each address field to
specify either a processor register or a memory operand. The program in assembly
language that evaluates X = (A + B) • (C + D) is shown below, together with
comments that explain the register transfer operation of each instruction.

ADD R1, A, B R 1  M[A] + M[B]

ADD R2, C, D R 2  M[C] + M[D]

MUL X, R1, R2 M[X]  R 1 • R 2

It is assumed that the computer has two processor registers, R 1 and R2. The
symbol M [A] denotes the operand at memory address symbolized by A.

The advantage of the three-address format is that it results in short programs when
evaluating arithmetic expressions. The disadvantage is that the binary-coded
instructions require too many bits to specify three addresses.
Two-Address Instructions

Two-address instructions are the most common in commercial computers. Here

again each address field can specify either a processor register or a memory word.
The program to evaluate X = (A + B) • (C + D) is as follows:

MOV R1, A R 1  M[A]

ADD R1, B R 1  R1 + M[B]

MOV R2, C R 2  M[C]

ADD R2, D R 2  R2 + M[D]

MUL R1, R2 R1  R 1 • R 2

MOV X, R1 M[X]  R 1

The MOV instruction moves or transfers the operands to and from memory and
processor registers. The first symbol listed in an instruction is assumed to be both a
source and the destination where the result of the operation is transferred.

One-Address Instructions

One-address instructions use an implied accumulator (AC) register for all data
manipulation. For multiplication and division there is a need for a second register.
However, here we will neglect the second register and assume that the AC contains
the result of all operations. The program to evaluate X = (A + B) • (C + D) is

Load A A C  M[A]

ADD B AC  AC + M[B]

Store T M[T]  AC

Load C A C  M[C]

ADD D A C  AC + M[D]

MUL T A C  AC • M[ T]

Store X M[X]  AC
All operations are done between the AC register and a memory operand. T is the
address of a temporary memory location required for storing the intermediate
result.

Zero-Address Instructions

A stack-organized computer does not use an address field for the instructions ADD
and MUL. The PUSH and POP instructions, however, need an address field to
specify the operand that communicates with the stack. The following program
shows how X = (A + B) • (C + D) will be written for a stack organized computer.
(TOS stands for top of stack.)

PUSH A TOS A
PUSH B TOS B
ADD TOS (A + B)
PUSH C TOS  C
PUSH D TOS  D
ADD TO S (C + D)
MUL TOS (C + D)•( A+B )
POP X M[X]  TOS

To evaluate arithmetic expressions in a stack computer, it is necessary to convert

the expression into reverse Polish notation. The name "zero-address" is given to
this type of computer because of the absence of an address field in the
computational instructions
 B)RISC & CISC Computers

An important aspect of computer architecture is the design of the instruction set for
the processor. The instruction set chosen for a particular computer determines the
way that machine language programs are constructed. Early computers had small
and simple instruction sets, forced mainly by the need to minimize the hardware
used to implement them.

Many computers have instruction sets that include more than 100 and sometimes
even more than 200 instructions. These computers also employ a variety of data
types and a large number of addressing modes. The trend into computer hardware
complexity was influenced by various factors, such as upgrading existing models
to provide more customer applications, adding instructions that facilitate the
translation from high-level language into machine language programs, and striving
to develop machines that move functions from software implementation into
hardware implementation. A computer with a large number of instructions is
classified as a complex instruction set computer, abbreviated CISC.

In the early 1980s, a number of computer designers recommended that computers

use fewer instructions with simple constructs so they can be executed much faster
within the CPU without having to use memory as often. This type of computer is
classified as a reduced instruction set computer or RISC. In this section we
introduce the major characteristics of CISC and RISC architectures and then
present the instruction set and instruction format of a RISC processor.
RISC Characteristics

The concept of RISC architecture involves an attempt to reduce execution time by

simplifying the instruction set of the computer. The major characteristics of a RISC
processor are:

1. Relatively few instructions

2. Relatively few addressing modes

3. Memory access limited to load and store instructions

4. All operations done within the registers of the CPU

5. Fixed-length, easily decoded instruction format

6. Single-cycle instruction execution

7. Hardwired rather than micro programmed control

The small set of instructions of a typical RISC processor consists mostly of

register-to-register operations, with only simple load and store operations for
memory access. Thus each operand is brought into a processor register with a load
instruction. All computations are done among the data stored in processor registers.
Results are transferred to memory by means of store instructions. This architectural
feature simplifies the instruction set and encourages the optimization of register
manipulation.

The use of only a few addressing modes results from the fact that almost all
instructions have simple register addressing. Other addressing modes may be
included, such as immediate operands and relative mode. By using a relatively
simple instruction format, the instruction length can be fixed and aligned on word
boundaries. An important aspect of RISC instruction format is that it is easy to
decode. Thus the operation code and register fields of the instruction code can be
accessed simultaneously by the control. By simplifying the instructions and their
format, it is possible to simplify the control logic. For faster operations, a
hardwired control is preferable over a micro programmed control.

CISC Characteristics

The design of an instruction set for a computer must take into consideration not
only machine language constructs, but also the requirements imposed on the use of
high-level programming languages. The translation from high-level to machine
language programs is done by means of a compiler program. One reason for the
trend to provide a complex instruction set is the desire to simplify the compilation
and improve the overall computer performance. The task of a compiler is to
generate a sequence of machine instructions for each hlgh-level language
statement. The task is simplified if there are machine instructions that implement
the statements directly.

The essential goal of a CISC architecture is to attempt to provide a single machine

instruction for each statement that is written in a high-level language. Another
characteristic of CISC architecture is the incorporation of variable-length
instruction formats. Instructions that require register operands may be only two
bytes in length, but instructions that need two memory addresses may need five
bytes to include the entire instruction code. If the computer has 32-bit words (four
bytes), the first instruction occupies half a word, while the second instruction needs
one word in addition to one byte in the next word. Packing variable instruction
formats in a fixed-length memory word requires special decoding circuits that
count bytes within words and frame the instructions according to their byte length.
The instructions in a typical CISC processor provide direct manipulation of
operands residing in memory. For example, an ADD instruction may specify one
operand in memory through index addressing and a second operand in memory
through a direct addressing. Another memory location may be included in the
instruction to store the sum. This requires three memory references during
execution of the instruction. Although CISC processors have instructions that use
only processor registers, the availability of other modes of operations tend to
simplify high-level language compilation. However, as more instructions and
addressing modes are incorporated into a computer, the more hardware logic is
needed to implement and support them, and this may cause the computations to
slow down.

In summary, the major characteristics of CISC architecture are:

1. A large number of instructions-typically from 100 to 250 instructions

2. Some instructions that perform specialized tasks and are used infrequently

3. A large variety of addressing modes-typically from 5 to 20 different modes

4. Variable-length instruction formats

5. Instructions that manipulate operands in memory.