LESSON NO.

07
1.1. REGISTER + OFFSET ADDRESSING
Direct addressing and indirect addressing using a single register are two basic
forms of memory access. Another possibility is to use different combinations of direct
and indirect references. In the above example we used BX to access different array
elements which were placed consecutively in memory like an array. We can also
place in BX only the array index and not the exact address and form the exact
address when we are going to access the actual memory. This way the same register
can be used for accessing different arrays and also the register can be used for index
comparison like the following example does.

Example 2.8
001 ; a program to add ten numbers using register + offset addressing
002 [org 0x0100]
003 mov bx, 0 ; initialize array index to zero
004 mov cx, 10 ; load count of numbers in cx
005 mov ax, 0 ; initialize sum to zero
006
007 l1: add ax, [num1+bx] ; add number to ax
008 add bx, 2 ; advance bx to next index
009 sub cx, 1 ; numbers to be added reduced
010 jnz l1 ; if numbers remain add next
011
012 mov [total], ax ; write back sum in memory
013
014 mov ax, 0x4c00 ; terminate program
015 int 0x21
016
017 num1: dw 10, 20, 30, 40, 50, 10, 20, 30, 40, 50
018 total: dw 0

003 This time BX is initialized to zero instead of array base

007 The format of memory access has changed. The array base is
added to BX containing array index at the time of memory access.
008 As the array is of words, BX jumps in steps of two, i.e. 0, 2, 4.
Higher level languages do appropriate incrementing themselves
and we always use sequential array indexes. However in assembly
language we always calculate in bytes and therefore we need to
take care of the size of one array element which in this case is two.

Inside the debugger we observe that the memory access instruction is shown as
“mov ax, [011F+bx]” and the actual memory accessed is the one whose address is
the sum of 011F and the value contained in the BX register. This form of access is of
the register indirect family and is called base + offset or index + offset depending on
whether BX or BP is used or SI or DI is used.

1.2. SEGMENT ASSOCIATION

All the addressing mechanisms in iAPX88 return a number called effective address.
For example in base + offset addressing, neither the base nor the offset alone tells
the desired cell in memory to be accessed. It is only after the addition is done that
the processor knows which cell to be accessed. This number which came as the result
of addition is called the effective address. But the effective address is just an offset
and is meaningless without a segment. Only after the segment is known, we can form
the physical address that is needed to access a memory cell.
We discussed the segmented memory model of iAPX88 in reasonable detail at the
end of previous chapter. However during the discussion of addressing modes we
have not seen the effect of segments. Segmentation is there and it’s all happening
relative to a segment base. We saw DS, CS, SS, and ES inside the debugger.
Everything is relative to its segment base, even though we have not explicitly
explained its functionality. An offset alone is not complete without a segment. As
previously discussed there is a default segment associated to every register which
accesses memory. For example CS is associated to IP by default; rather it is tied with
it. It cannot access memory in any other segment.
In case of data, there is a bit relaxation and nothing is tied. Rather there is a
default association which can be overridden. In the case of register indirect memory
access, if the register used is one of SI, DI, or BX the default segment is DS. If
however the register used in BP the default segment used is SS. The stack segment
has a very critical and fine use and there is a reason why BP is attached to SS by
default. However these will be discussed in detail in the chapter on stack. IP is tied to
CS while SP is tied to SS. The association of these registers cannot be changed; they
are locked with no option. Others are not locked and can be changed.
To override the association for one instruction of one of the registers BX, BP, SI or
DI, we use the segment override prefix. For example “mov ax, [cs:bx]” associates BX
with CS for this one instruction. For the next instruction the default association will
come back to act. The processor places a special byte before the instruction called a
prefix, just like prefixes and suffixes in English language. No prefix is needed or
placed for default association. For example for CS the byte 2E is placed and for ES
the byte 26 is placed. Opcode has not changed, but the prefix byte has modified the
default association to association with the desired segment register for this one
instruction.
In all our examples, we never declared a segment or used it explicitly, but
everything seemed to work fine. The important thing to note is that CS, DS, SS, and
ES all had the same value. The value itself is not important but the fact that all had
the same value is important. All four segment windows exactly overlap. Whatever
segment register we use the same physical memory will be accessed. That is why
everything was working without the mention of a single segment register. This is the
formation of COM files in IBM PC. A single segment contains code, data, and the
stack. This format is operating system dependant, in our case defined by DOS. And
our operating system defines the format of COM files such that all segments have the
same value. Thus the only meaningful thing that remains is the offset.
For example if BX=0100, SI=0200, and CS=1000 and the memory access under
consideration is [cs:bx+si+0x0700], the effective address formed is bx+si+0700 =
0100 + 0200 + 0700 = 0A00. Now multiplying the segment value by 16 makes it
10000 and adding the effective address 00A00 forms the physical address 10A00.

1.3. ADDRESS WRAPAROUND

There are two types of wraparounds. One is within a single segment and the other
is inside the whole physical memory. Segment wraparound occurs when during the
effective address calculation a carry is generated. This carry is dropped giving the
effect that when we try to access beyond the segment limit, we are actually wrapped
around to the first cell in the segment. For example if BX=9100, DS=1500 and the
access is [bx+0x7000] we form the effective address 9100 + 7000 = 10100. The
carry generated is dropped forming the actual effective address of 0100. Just like a
circle when we reached the end we started again from the beginning. An arc at 370
degrees is the same as an arc at 10 degrees. We tried to cross the segment
boundary and it pushed us back to the start. This is called segment wraparound. The
physical address in the above example will be 15100.
The same can also happen at the time of physical address calculation. For example
BX=0100, DS=FFF0 and the access under consideration is [bx+0x0100]. The
effective address will be 0200 and the physical address will be 100100. This is a 21bit
answer and cannot be sent on the address bus which is 20 bits wide. The carry is
dropped and just like the segment wraparound our physical memory has wrapped
around at its very top. When we tried to access beyond limits the actual access is
made at the very start. This second wraparound is a bit different in newer processor
with more address lines but that will be explained in later chapters.

1.4. ADDRESSING MODES SUMMARY

The iAPX88 processor supports seven modes of memory access. Remember that
immediate is not an addressing mode but an operand type. Operands can be
immediate, register, or memory. If the operand is memory one of the seven
addressing modes will be used to access it. The memory access mechanisms can also
be written in the general form “base + index + offset” and we can define the
possible addressing modes by saying that any one, two, or none can be skipped from
the general form to form a legal memory access.
There are a few common mistakes done in forming a valid memory access. Part of
a register cannot be used to access memory. Like BX is allowed to hold an address
but BL or BH are not. Address is 16bit and must be contained in a 16bit register. BX-
SI is not possible. The only thing that we can do is addition of a base register with an
index register. Any other operation is disallowed. BS+BP and SI+DI are both
disallowed as we cannot have two base or two index registers in one memory access.
One has to be a base register and the other has to be an index register and that is
the reason of naming them differently.

Direct
A fixed offset is given in brackets and the memory at that offset is accessed. For
example “mov [1234], ax” stores the contents of the AX registers in two bytes
starting at address 1234 in the current data segment. The instruction “mov [1234],
al” stores the contents of the AL register in the byte at offset 1234.

Based Register Indirect

A base register is used in brackets and the actual address accessed depends on
the value contained in that register. For example “mov [bx], ax” moves the two byte
contents of the AX register to the address contained in the BX register in the current
data segment. The instruction “mov [bp], al” moves the one byte content of the AL
register to the address contained in the BP register in the current stack segment.

Indexed Register Indirect

An index register is used in brackets and the actual address accessed depends on
the value contained in that register. For example “mov [si], ax” moves the contents
of the AX register to the word starting at address contained in SI in the current data
segment. The instruction “mov [di], ax” moves the word contained in AX to the offset
stored in DI in the current data segment.

Based Register Indirect + Offset

A base register is used with a constant offset in this addressing mode. The value
contained in the base register is added with the constant offset to get the effective
address. For example “mov [bx+300], ax” stores the word contained in AX at the
offset attained by adding 300 to BX in the current data segment. The instruction
“mov [bp+300], ax” stores the word in AX to the offset attained by adding 300 to BP
in the current stack segment.

Indexed Register Indirect + Offset

An index register is used with a constant offset in this addressing mode. The value
contained in the index register is added with the constant offset to get the effective
address. For example “mov [si+300], ax” moves the word contained in AX to the
offset attained by adding 300 to SI in the current data segment and the instruction
“mov [di+300], al” moves the byte contained in AL to the offset attained by adding
300 to DI in the current data segment.

Base + Index
One base and one index register is used in this addressing mode. The value of the
base register and the index register are added together to get the effective address.
For example “mov [bx+si], ax” moves the word contained in the AX register to offset
attained by adding BX and SI in the current data segment. The instruction “mov
[bp+di], al” moves the byte contained in AL to the offset attained by adding BP and
DI in the current stack segment. Observe that the default segment is based on the
base register and not on the index register. This is why base registers and index
registers are named separately. Other examples are “mov [bx+di], ax” and “mov
[bp+si], ax.” This method can be used to access a two dimensional array such that
one dimension is in a base register and the other is in an index register.

Base + Index + Offset

This is the most complex addressing method and is relatively infrequently used. A
base register, an index register, and a constant offset are all used in this addressing
mode. The values of the base register, the index register, and the constant offset are
all added together to get the effective address. For example “mov [bx+si+300], ax”
moves the word contents of the AX register to the word in memory starting at offset
attained by adding BX, SI, and 300 in the current data segment. Default segment
association is again based on the base register. It might be used with the array base
of a two dimensional array as the constant offset, one dimension in the base register
and the other in the index register. This way all calculation of location of the desired
element has been delegated to the processor.

EXERCISES
1. What is a label and how does the assembler differentiates between code
labels and data labels?
2. List the seven addressing modes available in the 8088 architecture.
3. Differentiate between effective address and physical address.
4. What is the effective address generated by the following instructions? Every
instruction is independent of others. Initially BX=0x0100, num1=0x1001,
[num1]=0x0000, and SI=0x0100
a. mov ax, [bx+12]
b. mov ax, [bx+num1]
c. mov ax, [num1+bx]
d. mov ax, [bx+si]
5. What is the effective address generated by the following combinations if
they are valid. If not give reason. Initially BX=0x0100, SI=0x0010,
DI=0x0001, BP=0x0200, and SP=0xFFFF
a. bx-si
b. bx-bp
c. bx+10
d. bx-10
 e. bx+sp
f. bx+di
6. Identify the problems in the following instructions and correct them by
replacing them with one or two instruction having the same effect.
a. mov [02], [ 22]
b. mov [wordvar], 20
c. mov bx, al
d. mov ax, [si+di+100]
7. What is the function of segment override prefix and what changes it
brings to the opcode?
8. What are the two types of address wraparound? What physical
address is accessed with [BX+SI] if FFFF is loaded in BX, SI, and DS.
9. Write instructions to do the following.
a. Copy contents of memory location with offset 0025 in the current
data segment into AX.
b. Copy AX into memory location with offset 0FFF in the current data
segment.
c. Move contents of memory location with offset 0010 to memory
location with offset 002F in the current data segment.
10. Write a program to calculate the square of 20 by using a loop that
adds 20 to the accumulator 20 times.