19-2460; Rev 4; 3/09

4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
General Description
The MAX6954 is a compact display driver that interfaces microprocessors to a mix of 7-segment, 14-segment, and 16-segment LED displays through an SPIor QSPI-compatible 4-wire serial interface. The serial interface may be cascaded through multiple devices. The MAX6954 drives up to 16 digits 7-segment, 8 digits 14-segment, 8 digits 16-segment, or 128 discrete LEDs, while functioning from a supply voltage as low as 2.7V. The driver includes five I/O expander (or GPIO) lines, some or all of which may be configured as a keyswitch reader, which automatically scans and debounces a matrix of up to 32 switches. Included on chip are full 14- and 16-segment ASCII 104-character fonts, a hexadecimal font for 7-segment displays, multiplex scan circuitry, anode and cathode drivers, and static RAM that stores each digit. The maximum segment current for the display digits is set using a single external resistor. Digit intensity can be independently adjusted using the 16-step internal digital brightness control. The MAX6954 includes a low-power shutdown mode, a scan-limit register that allows the user to display from 1 to 16 digits, segment blinking (synchronized across multiple drivers, if desired), and a test mode, which forces all LEDs on. The LED drivers are slew-rate limited to reduce EMI. For a 2-wire interfaced version, refer to the MAX6955 data sheet. An evaluation kit (EV kit) for the MAX6955 is available. 2.7V to 5.5V Operation Drives Up to 16 Digits 7-Segment, 8 Digits 14-Segment, 8 Digits 16-Segment, 128 Discrete LEDs, or a Combination of Digit Types Drives Common-Cathode Monocolor and Bicolor LED Displays Built-In ASCII 104-Character Font for 14-Segment and 16-Segment Digits and Hexadecimal Font for 7-Segment Digits Automatic Blinking Control for each Segment 10A (typ) Low-Power Shutdown (Data Retained) 16-Step Digit-by-Digit Digital Brightness Control Display Blanked on Power-Up Slew-Rate Limited Segment Drivers for Lower EMI Five GPIO Port Pins Can Be Configured as KeySwitch Reader to Scan and Debounce Up to 32 Switches with n-Key Rollover IRQ Output when a Key Input Is Debounced 36-Pin SSOP and 40-Pin DIP and TQFN Packages Automotive Temperature Range Standard

Features
High-Speed 26MHz SPI/QSPI/MICROWIRECompatible Serial Interface

MAX6954

Applications
Set-Top Boxes Panel Meters White Goods Automotive Bar Graph Displays Audio/Video Equipment
ISET CURRENT SOURCE

Functional Diagram
GPIO AND KEY-SCAN CONTROL PWM BRIGHTNESS CONTROL DIGIT MULTIPLEXER P0 TO P4

LED DRIVERS

O0 TO O23

Ordering Information
PART MAX6954AAX MAX6954APL MAX6954ATL+ TEMP RANGE -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 36 SSOP 40 PDIP 40 TQFN-EP*

OSC OSC_OUT

DIVIDER/ COUNTER NETWORK

MAX6954

CHARACTER GENERATOR ROM

BLINK

+Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. Pin Configurations and Typical Operating Circuits appear at end of data sheet.
CLK CS DIN DOUT

BLINK CONTROL

RAM

CONFIGURATION REGISTER

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.

4-WIRE SERIAL INTERFACE

________________________________________________________________ Maxim Integrated Products

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.

4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
ABSOLUTE MAXIMUM RATINGS
(Voltage with respect to GND.) V+ .........................................................................-0.3V to +6V All Other Pins............................................-0.3V to (V+ + 0.3V) Current O0O7 Sink Current ......................................................935mA O0O18 Source Current .................................................55mA DIN, CLK, CS, OSC, DOUT, BLINK, OSC_OUT, ISET ....20mA P0, P1, P2, P3, P4 ...........................................................40mA GND .....................................................................................1A Continuous Power Dissipation (TA = +70C) 36-Pin SSOP (derate at 11.8mW/C above +70C) .....941mW 40-Pin PDIP (derate at 16.7mW/C above +70C).....1333mW 40-Pin TQFN (derate at 37mW/C above +70C) ......2963mW Operating Temperature Range (TMIN to TMAX) ...............................................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(Typical Operating Circuits, V+ = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Operating Supply Voltage SYMBOL V+ Shutdown mode, all digital inputs at V+ or GND All segments on, all digits scanned, intensity set to full, internal oscillator, DOUT open circuit, no display or OSC_OUT load connected TA = +25C TA = TMIN to TMAX CONDITIONS MIN 2.7 10 TYP MAX 5.5 35 A 40 UNITS V

Shutdown Supply Current

ISHDN

TA = +25C

22

30 mA

Operating Supply Current

I+

TA = TMIN to TMAX

35

Master Clock Frequency Dead Clock Protection Frequency OSC Internal/External Detection Threshold OSC High Time OSC Low Time Slow Segment Blink Period Fast Segment Blink Period Fast or Slow Segment Blink Duty Cycle

fOSC fOSC VOSC tCH tCL

OSC = RC oscillator, RSET = 56k, CSET = 22pF, V+ = 3.3V OSC driven externally 1

4 8 95 1.7 50 50 1 0.5 49.5 50.5

MHz kHz V ns ns s s %

OSC = RC oscillator, RSET = 56k, fSLOWBLINK C SET = 22pF, V+ = 3.3V fFASTBLINK OSC = RC oscillator, RSET = 56k, CSET = 22pF, V+ = 3.3V

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuits, V+ = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER Segment Drive Source Current Segment Current Slew Rate Segment Drive Current Matching LOGIC INPUTS AND OUTPUTS Input Leakage Current DIN, CLK, CS, OSC, P0, P1, P2, P3, P4 4-Wire Logic-High Input Voltage DIN, CLK, CS 4-Wire Logic-Low Input Voltage DIN, CLK, CS Port Logic-High Input Voltage P0, P1, P2, P3, P4 Port Logic-Low Input Voltage P0, P1, P2, P3, P4 Port Hysteresis Voltage P0, P1, P2, P3, P4 Port Input Pullup Current from V+ Port Output Low Voltage Blink Output Low Voltage DOUT Output High Voltage DOUT Output Low Voltage OSC_OUT Output High Voltage OSC_OUT Output Low Voltage IIH, IIL -1 +1 A SYMBOL ISEG ISEG/t ISEG VLED = 2.2V, V+ = 3.3V CONDITIONS TA = +25C MIN -34.5 TYP -40 11 5 10 MAX -46.5 UNITS mA mA/s %

MAX6954

TA = +25C, V+ = 3.3V TA = +25C, V+ = 3.3V

VIHSPI VILSPI VIHP VILP VIP IIPU VOLP VOLBK VOHDO VOLDO VOHOSC VOLOSC P0 to P3 configured as keyscan input, V+ = 3.3V ISINK = 8mA ISINK = 0.6mA ISOURCE = 1.6mA ISINK = 1.6mA ISOURCE = 1.6mA ISINK = 1.6mA

1.8 0.6 0.7 x V+ 0.3 x V+ 0.03 x V+ 75 0.3 0.1 V+ 0.2 0.2 V+ 0.4 0.4 0.5 0.3

V V V V V A V V V V V V

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
TIMING CHARACTERISTICS
(Typical Operating Circuits, V+ = 2.7V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER TIMING CHARACTERISTICS CLK Clock Period CLK Pulse Width High CLK Pulse Width Low CS Fall to CLK Rise Setup Time CLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time Output Data Propagation Delay DOUT Output Rise and Fall Times Minimum CS Pulse High tCP tCH tCL tCSS tCSH tDS tDH tDO tFT tCSW V+ = 3.0V to 5.5V V+ = 2.7V CLOAD = 10pF, V+ = 3.0V to 5.5V 19.5 38.4 16 16 9.5 0 9.5 0 19 25 10 ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS

Note 1: All parameters tested at TA = +25C. Specifications over temperature are guaranteed by design.

Typical Operating Characteristics

(V+ = 3.3V, LED forward voltage = 2.4V, typical application circuit, TA = +25C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE
MAX6954 toc01

INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE

MAX6954 toc02

INTERNAL OSCILLATOR WAVEFORM AT OSC AND OSC_OUT PINS

MAX6954 toc03

4.4 OSCILLATOR FREQUENCY (MHz) RSET = 56k CSET = 22pF 4.2

4.4 OSCILLATOR FREQUENCY (MHz)

RSET = 56k CSET = 22pF

RSET = 56k CSET = 22pF OSC

4.2 0V 4.0

4.0

3.8

3.8

OSC_OUT 0V

3.6 -40 -10 20 50 80 110 TEMPERATURE (C)

3.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 100ns/div OSC: 500mV/div OSC_OUT: 2V/div

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
Typical Operating Characteristics (continued)
(V+ = 3.3V, LED forward voltage = 2.4V, typical application circuit, TA = +25C, unless otherwise noted.)
DEAD CLOCK OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
MAX6954 toc04

MAX6954

SEGMENT SOURCE CURRENT vs. SUPPLY VOLTAGE

MAX6954 toc05

110 OSCILLATOR FREQUENCY (kHz) 105 100 95 90 85 80 2.5 3.0 3.5 4.0 4.5 5.0 RSET = 56k OSC = GND

1.02 CURRENT NORMALIZED TO 40mA 1.00

0.98

0.96

0.94 VLED = 1.8V 0.92

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

WAVEFORM AT PINS O0 AND O18, MAXIMUM INTENSITY

MAX6954 toc06

GPIO SINK CURRENT vs. TEMPERATURE

40 GPIO SINK CURRENT (mA) 35 30 25 20 15 10 VCC = 3.3V VCC = 2.5V VCC = 5.5V OUTPUT = LOW VPORT = 0.6V
MAX6954 toc07

45

O0

0V

O18 5 0V 1V/div 200s/div 0 -40 -10 20 50 80 110 TEMPERATURE (C)

PORT INPUT PULLUP CURRENT vs. TEMPERATURE

OUTPUT = HIGH VPORT = 1.4V
MAX6954 toc08

KEYSCAN OPERATION (KEY_A AND IRQ)

MAX6954 toc09

0.30 KEY-SCAN SOURCE CURRENT (mA) 0.25 0.20 0.15 VCC = 5.5V

KEY_A

0V 0.10 0.05 VCC = 2.5V 0 -40 -10 20 50 80 110 TEMPERATURE (C) 400s/div KEY_A: 1V/div IRQ: 2V/div VCC = 3.3V IRQ 0V

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Pin Description
PIN SSOP 1, 2, 34, 35, 36 3 4 5 6 PDIP 1, 2, 38, 39, 40 3 4 5 6 TQFN-EP 36, 37, 33, 34, 35 38 39 40 1 NAME FUNCTION General-Purpose I/O Ports (GPIOs). GPIO can be configured as logic inputs or open-drain outputs. Enabling key scanning configures some or all ports P0P3 as key-switch matrix inputs with internal pullup and port P4 as IRQ output. Chip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent 16 bits of data latch on CSs rising edge. Serial-Data Output. The data into DIN is valid at DOUT 15.5 clock cycles later. Use this pin to daisy-chain several devices or allow data readback. Output is push-pull. Serial-Clock Input. On CLKs rising edge, data shifts into the internal shift register. On CLKs falling edge, data is clocked out of DOUT. CLK is active only while CS is low. Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on CLKs rising edge. Digit/Segment Drivers. When acting as digit drivers, outputs O0 to O7 sink current from the display common cathodes. When acting as segment drivers, O0 to O18 source current to the display anodes. O0 to O18 are high impedance when not being used as digit or segment drivers. Ground Segment Current Setting. Connect ISET to GND through series resistor RSET to set the peak current. Positive Supply Voltage. Bypass V+ to GND with a 47F bulk capacitor and a 0.1F ceramic capacitor. Multiplex Clock Input. To use internal oscillator, connect capacitor CSET from OSC to GND. To use external clock, drive OSC with a 1MHz to 8MHz CMOS clock. Blink Clock Output. Output is open drain. Clock Output. OSC_OUT is a buffered clock output to allow easy blink synchronization of multiple MAX6954s. Output is push-pull. Not Connected Internally Exposed Pad (TQFN package only). Internally connected to GND. Connect to a large ground plane to maximize thermal performance.

P0P4

CS DOUT CLK DIN

715, 2231 16, 18 17 19, 21 20 32 33

715, 2635 17, 18, 20 19 21, 23, 24 22 36 37 16, 25

210, 2130 12, 13, 15 14 16, 18, 19 17 31 32 11, 20

O0O18

GND ISET V+ OSC BLINK OSC_OUT N.C. EP

Detailed Description
The MAX6954 is a serially interfaced display driver that can drive up to 16 digits 7-segment, 8 digits 14-segment, 8 digits 16-segment, 128 discrete LEDs, or a combination of these display types. Table 1 shows the drive capability of the MAX6954 for monocolor and bicolor displays. The MAX6954 includes 104-character ASCII font maps for 14-segment and 16-segment displays, as well as the hexadecimal font map for 7-segment displays. The characters follow the standard ASCII font, with the addition of the following common symbols: , , , , , , , and . Seven bits represent the 104-character font
6

map; an 8th bit is used to select whether the decimal point (DP) is lit. Seven-segment LED digits may be controlled directly or use the hexadecimal font. Direct segment control allows the MAX6954 to be used to drive bar graphs and discrete LED indicators. Tables 2, 3, and 4 list the connection schemes for 16-, 14-, and 7-segment digits, respectively. The letters in Tables 2, 3, and 4 correspond to the segment labels shown in Figure 1. (For applications that require mixed display types, see Tables 3740.)

Serial Interface
The MAX6954 communicates through an SPI-compatible 4-wire serial interface. The interface has three

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
1a 2a a a1 a2

1f

1b

2f

2b

1g

2g

g1

g2

g1

g2

1e

1c 1dp 1d

2e

2c 2dp 2d

c dp

c dp

d2

d1

Figure 1. Segment Labeling for 7-Segment Display, 14-Segment Display, and 16-Segment Display

Table 1. MAX6954 Drive Capability

DISPLAY TYPE Monocolor Bicolor 7 SEGMENT (16-CHARACTER HEXADECIMAL FONT) 16 8 14 SEGMENT/ 16 SEGMENT (104-CHARACTER ASCII FONT MAP) 8 4 DISCRETE LEDs (DIRECT CONTROL) 128 64

inputs: clock (CLK), chip select (CS), and data in (DIN), and one output, data out (DOUT). CS must be low to clock data into or out of the device, and DIN must be stable when sampled on the rising edge of CLK. DOUT is stable on the rising edge of CLK. Note that while the SPI protocol expects DOUT to be high impedance when the MAX6954 is not being accessed, DOUT on the MAX6954 is never high impedance. CLK and DIN may be used to transmit data to other peripherals. The MAX6954 ignores all activity on CLK and DIN except when CS is low.

together. To update just one device in a daisy-chain, the user can send the no-op command (0x00) to the others. Figure 3 is the MAX6954 timing diagram. The MAX6954 is written to using the following sequence: 1) Take CLK low. 2) Take CS low. This enables the internal 16-bit shift register. 3) Clock 16 bits of data into DIN, D15 first to D0 last, observing the setup and hold times. Bit D15 is low, indicating a write command. 4) Take CS high (while CLK is still high after clocking in the last data bit). 5) Take CLK low. Figure 4 shows a write operation when 16 bits are transmitted. If fewer or greater than 16 bits are clocked into the MAX6954 between taking CS low and taking CS high again, the MAX6954 stores the last 16 bits received, including the previous transmission(s). The general case is when n bits (where n > 16) are transmitted to the MAX6954. The last bits are comprising bits {n-15} to {n}, are retained, and are parallel loaded into the 16-bit latch as bits D15 to D0, respectively (Figure 5).

Control and Operation Using the 4-Wire Interface Controlling the MAX6954 requires sending a 16-bit word. The first byte, D15 through D8, is the command, and the second byte, D7 through D0, is the data byte (Table 5). Connecting Multiple MAX6954s to the 4-Wire Bus Multiple MAX6954s may be daisy-chained by connecting the DOUT of one device to the DIN of the next, and driving CLK and CS lines in parallel (Figure 2). Data at DIN propagates through the internal shift registers and appears at DOUT 15.5 clock cycles later, clocked out on the falling edge of CLK. When sending commands to daisy-chained MAX6954s, all devices are accessed at the same time. An access requires (16 x n) clock cycles, where n is the number of MAX6954s connected

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 2. Connection Scheme for Eight 16-Segment Digits
DIGIT O0 0 1 2 3 4 5 6 7 CCO a1 a1 a1 a1 a1 a1 O1 CC1 a2 a2 a2 a2 a2 a2 O2 a1 a1 CC2 b b b b O3 a2 a2 CC3 c c c c O4 b b b b CC4 d1 d1 O5 c c c c CC5 d2 d2 O6 d1 d1 d1 d1 d1 d1 CC6 O7 d2 d2 d2 d2 d2 d2 CC7 O8 e e e e e e e e O9 f f f f f f f f O10 g1 g1 g1 g1 g1 g1 g1 g1 O11 g2 g2 g2 g2 g2 g2 g2 g2 O12 h h h h h h h h O13 i i i i i i i i O14 j j j j j j j j O15 k k k k k k k k O16 l l l l l l l l O17 m m m m m m m m O18 dp dp dp dp dp dp dp dp

Table 3. Connection Scheme for Eight 14-Segment Digits

DIGIT O0 0 1 2 3 4 5 6 7 CCO a a a a a a O1 CC1 O2 a a CC2 b b b b O3 CC3 c c c c O4 b b b b CC4 d d O5 c c c c CC5 O6 d d d d d d CC6 O7 CC7 O8 e e e e e e e e O9 f f f f f f f f O10 g1 g1 g1 g1 g1 g1 g1 g1 O11 g2 g2 g2 g2 g2 g2 g2 g2 O12 h h h h h h h h O13 i i i i i i i i O14 j j j j j j j j O15 k k k k k k k k O16 l l l l l l l l O17 m m m m m m m m O18 dp dp dp dp dp dp dp dp

Table 4. Connection Scheme for Sixteen 7-Segment Digits

DIGIT* O0 0, 0a CC0 1, 1a 2, 2a 3, 3a 4, 4a 5, 5a 6, 6a 7, 7a 1a 1a 1a 1a 1a 1a O1 CC1 O2 1a 1a CC2 1b 1b 1b 1b O3 CC3 1c 1c 1c 1c O4 1b 1b 1b 1b CC4 1d 1d O5 1c 1c 1c 1c CC5 1dp 1dp O6 1d 1d 1d 1d 1d 1d CC6 O7 1dp 1dp 1dp 1dp 1dp 1dp CC7 O8 1e 1e 1e 1e 1e 1e 1e 1e O9 1f 1f 1f 1f 1f 1f 1f 1f O10 1g 1g 1g 1g 1g 1g 1g 1g O11 2a 2a 2a 2a 2a 2a 2a 2a O12 2b 2b 2b 2b 2b 2b 2b 2b O13 2c 2c 2c 2c 2c 2c 2c 2c O14 2d 2d 2d 2d 2d 2d 2d 2d O15 2e 2e 2e 2e 2e 2e 2e 2e O16 2f 2f 2f 2f 2f 2f 2f 2f O17 2g 2g 2g 2g 2g 2g 2g 2g O18 2dp 2dp 2dp 2dp 2dp 2dp 2dp 2dp

*Each cathode driver output (CC0-CC7) connects to two digit common cathode pins.

Table 5. Serial-Data Format (16 Bits)

D15 R/W D14 D13 D12 D11 D10 D9 D8 D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB ADDRESS DATA

Reading Device Registers Any register data within the MAX6954 may be read by sending a logic high to bit D15. The sequence is: 1) Take CLK low.

2) Take CS low. This enables the internal 16-bit shift register. 3) Clock 16 bits of data into DIN, D15 first to D0 last. D15 is high, indicating a read command and bits D14 through D8 contain the address of the register

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
DOUT CLK MICROCONTROLLER CS CS CS CS DIN CLK MAX6954 DOUT DIN CLK MAX6954 DOUT DIN CLK MAX6954 DOUT

DIN

Figure 2. MAX6954 Daisy-Chain Connection

CS

tCSW

tCSS

tCL

tCH

tCP

tCSH

CLK tDS DIN

tDH D14 D1 tDO D0

D15

DOUT

D15

Figure 3. Timing Diagram

to read. Bits D7 to D0 contain dummy data, which is discarded. 4) Take CS high (while CLK is still high after clocking in the last data bit), positions D7 through D0 in the shift register are now loaded with the register data addressed by bits D15 through D8. 5) Take CLK low. 6) Issue another read or write command (which can be a no-op), and examine the bit stream at DOUT; the second 8 bits are the contents of the register addressed by bits D14 through D8 in step 3.

Digit Type Registers

The MAX6954 uses 32 digit registers to store the characters that the user wishes to display. These digit registers are implemented with two planes, P0 and P1. Each digit is represented by 2 bytes of memory, 1 byte in plane P0 and the other in plane P1. The digit registers

are mapped so that a digits data can be updated in plane P0, plane P1, or both planes at the same time (Table 6). If the blink function is disabled through the Blink Enable Bit E (Table 19) in the configuration register, then the digit register data in plane P0 is used to multiplex the display. The digit register data in P1 is not used. If the blink function is enabled, then the digit register data in both plane P0 and plane P1 are alternately used to multiplex the display. Blinking is achieved by multiplexing the LED display using data plane P0 and plane P1 on alternate phases of the blink clock (Table 20). The data in the digit registers does not control the digit segments directly for 14- and 16-segment displays. Instead, the register data is used to address a character generator that stores the data for the 14- and 16segment fonts (Tables 7 and 8). The lower 7 bits of the digit data (D6 to D0) select the character from the font.
9

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
CS

CLK DIN D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DOUT

D15 = 0

Figure 4. Transmission of 16 Bits to the MAX6954

CS

CLK N-15 DIN BIT 1 BIT 2 N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N

DOUT

N-31

N-30

N-29

N-28

N-27

N-26

N-25

N-24

N-23

N-22

N-21

N-20

N-19

N-18

N-17

N-16

N-15

Figure 5. Transmission of More than 16 Bits to the MAX6954

The most significant bit of the register data (D7) controls the DP segment of the digits; it is set to 1 to light DP, and to zero to leave DP unlit (Table 9). For 7-segment displays, the digit plane data register can be used to address a character generator, which contains the data of a 16-character font containing the hexadecimal font. The decode mode register can be used to disable the character generator and allow the segments to be controlled directly. Table 10 shows the one-to-one pairing of each data bit to the appropriate segment line in the digit plane data registers. The hexadecimal font is decoded according to Table 11. The digit-type register configures the display driver for various combinations of 14-segment digits, 16-segment digits, and/or pairs, or 7-segment digits. The function of this register is to select the appropriate font for each digit and route the output of the font to the appropriate MAX6954 driver output pins. The MAX6954 has four digit drive slots. A slot can be filled with various combinations of monocolor and bicolor 16-segment displays, 14-segment displays, or two 7-segment displays. Each pair of bits in the register corresponds to one of the four
10

digit drive slots, as shown in Table 12. Each bit also corresponds to one of the eight common-cathode digit drive outputs, CC0 to CC7. When using bicolor digits, the anode connections for the two digits within a slot are always the same. This means that a slot correctly drives two monocolor or one bicolor 14- or 16-segment digit. The digit type register can be written, but cannot be read. Examples of configuration settings required for some display digit combinations are shown in Table 13.

7-Segment Decode-Mode Register

In 7-segment mode, the hexadecimal font can be disabled (Table 14). The decode-mode register selects between hexadecimal code or direct control for each of eight possible pairs of 7-segment digits. Each bit in the register corresponds to one pair of digits. The digit pairs are {digit 0, digit 0a} through {digit 7, digit 7a}. Disabling decode mode allows direct control of the 16 LEDs of a dual 7-segment display. Direct control mode can also be used to drive a matrix of 128 discrete LEDs.

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
A logic high selects hexadecimal decoding, while a logic low bypasses the decoder. When direct control is selected, the data bits D7 to D0 correspond to the segment lines of the MAX6954. Write x0010000 to blank all segments in hexadecimal decode mode.

Character Generator Font Mapping

The font is composed of 104 characters in ROM. The lower 7 bits of the 8-bit digit register represent the character selection. The most significant bit, shown as x in the ROM map of Tables 7 and 8, is 1 to light the DP segment and zero to leave the DP segment unlit. The character map follows the standard ASCII font for 96 characters in the x0101000 through x1111111 range. The first 16 characters of the 16-segment ROM map cover 7-segment displays. These 16 characters are numeric 0 to 9 and characters A to F (i.e., the hexadecimal set).

MAX6954

Display Blink Mode

The display blinking facility, when enabled, makes the driver flip automatically between displaying the digit register data in planes P0 and P1. If the digit register data for any digit is different in the two planes, then that digit appears to flip between two characters. To make a character appear to blink on or off, write the character to one plane, and use the blank character (0x20) for the other plane. Once blinking has been configured, it continues automatically without further intervention.

Multiplex Clock and Blink Timing

The OSC pin can be fitted with capacitor CSET to GND to use the internal RC multiplex oscillator, or driven by an external clock to set the multiplex clock frequency and blink rate. The multiplex clock frequency determines the frequency that the complete display is updated. With OSC at 4MHz, each display digit is enabled for 200s. The internal RC oscillator uses an external resistor, RSET, and an external capacitor, CSET, to set the oscillator frequency. The suggested values of RSET (56k) and C SET (22pF) set the oscillator at 4MHz, which makes the blink frequency 0.5Hz or 1Hz. The external clock is not required to have a 50:50 duty cycle, but the minimum time between transitions must be 50ns or greater and the maximum time between transitions must be 750ns. The on-chip oscillator may be accurate enough for applications using a single device. If an exact blink rate is required, use an external clock ranging between 1MHz and 8MHz to drive OSC. The OSC inputs of multiple MAX6954s can be tied together to a common external clock to make the devices blink at the same rate. The relative blink phasing of multiple MAX6954s can be synchronized by setting the T bit in the control register for all the devices in quick succession. If the serial interfaces of multiple MAX6954s are daisy-chained by connecting the DOUT of one device to the DIN of the next, then synchronization is achieved automatically by updating the configuration register for all devices simultaneously. Figure 6 is the multiplex timing diagram.

Blink Speed
The blink speed is determined by the frequency of the multiplex clock, OSC, and by the setting of the Blink Rate Selection Bit B (Table 18) in the configuration register. The Blink Rate Selection Bit B sets either fast or slow blink speed for the whole display.

Initial Power-Up
On initial power-up, all control registers are reset, the display is blanked, intensities are set to minimum, and shutdown is enabled (Table 15).

Configuration Register
The configuration register is used to enter and exit shutdown, select the blink rate, globally enable and disable the blink function, globally clear the digit data, select between global or digit-by-digit control of intensity, and reset the blink timing (Tables 1619 and 2124). The configuration register contains 7 bits: S bit selects shutdown or normal operation (read/write). B bit selects the blink rate (read/write). E bit globally enables or disables the blink function (read/write). T bit resets the blink timing (data is not storedtransient bit). R bit globally clears the digit data for both planes P0 and P1 for ALL digits (data is not storedtransient bit). I bit selects between global or digit-by-digit control of intensity (read/write). P bit returns the current phase of the blink timing (read onlya write to this bit is ignored).

OSC_OUT Output The OSC_OUT output is a buffered copy of either the internal oscillator clock or the clock driven into the OSC pin if the external clock has been selected. The feature is useful if the internal oscillator is used, and the user wishes to synchronize other MAX6954s to the same blink frequency. The oscillator is disabled while the MAX6954 is in shutdown.
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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Scan-Limit Register
The scan-limit register sets how many 14-segment digits or 16-segment digits or pairs of 7-segment digits are displayed, from 1 to 8. A bicolor digit is connected as two monocolor digits. The scan register also limits the number of keys that can be scanned. Since the number of scanned digits affects the display brightness, the scan-limit register should not be used to blank portions of the display (such as leading-zero suppression). Table 25 shows the scan-limit register format.

GPIO and Key Scanning

The MAX6954 feature five general-purpose input/output (GPIO) ports: P0 to P4. These ports can be individually enabled as logic inputs or open-drain logic outputs. The GPIO ports are not debounced when configured as inputs. The ports can be read and the outputs set using the 4-wire interface. Some or all of the five ports can be configured to perform key scanning of up to 32 keys. Ports P0 to P4 are renamed Key_A, Key_B, Key_C, Key_D, and IRQ, respectively, when used for key scanning. The full keyscanning configuration is shown in Figure 7. Table 30 is the GPIO data register. One diode is required per key switch. These diodes can be common-anode dual diodes in SOT23 packages, such as the BAW56. Sixteen diodes would be required for the maximum 32-key configuration. The MAX6954 can only scan the maximum 32 keys if the scan-limit register is set to scan the maximum eight digits. If the MAX6954 is driving fewer digits, then a maximum of (4 x n) switches can be scanned, where n is the number of digits set in the scan-limit register. For example, if the MAX6954 is driving four 14-segment digits cathode drivers O0 to O3 are used. Only 16 keys can be scanned in this configuration; the switches shown connected to O4 through O7 are not read. If the user wishes to scan fewer than 32 keys, then fewer scan lines can be configured for key scanning. The unused Key_x ports are released back to their original GPIO functionality. If key scanning is enabled, regardless of the number of keys being scanned, P4 is always configured as IRQ (Table 31). The key-scanning circuit utilizes the LEDs commoncathode driver outputs as the key-scan drivers. O0 to 07 go low for nominally 200s (with OSC = 4MHz) in turn as the displays are multiplexed. By varying the oscillator frequency, the debounce time changes, though key scanning still functions. Key_x inputs have internal pullup resistors that allow the key condition to be tested. The Key_x input is low during the appropriate digit multiplex period when the key is pressed. The timing diagram of Figure 8 shows the normal situation where all eight LED cathode drivers are used.

Intensity Registers
Digital control of display brightness is provided and can be managed in one of two ways: globally or individually. Global control adjusts all digits together. Individual control adjusts the digits separately. The default method is global brightness control, which is selected by clearing the global intensity bit (I data bit D6) in the configuration register. This brightness setting applies to all display digits. The pulse-width modulator is then set by the lower nibble of the global intensity register, address 0x02. The modulator scales the average segment current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current. The minimum interdigit blanking time is set to 1/16 of a cycle. When using bicolor digits, 256 color/brightness combinations are available. Individual brightness control is selected by setting the global intensity bit (I data bit D6) in the configuration register. The pulse-width modulator is now no longer set by the lower nibble of the global intensity register, address 0x02, and the data is ignored. Individual digital control of display brightness is now provided by a separate pulse-width modulator setting for each digit. Each digit is controlled by a nibble of one of the four intensity registers: intensity10, intensity32, intensity54, and intensity76 for all display types, plus intensity10a, intensity32a, intensity54a, and intensity76a for the extra eight digits possible when 7-segment displays are used. The data from the relevant register is used for each digit as it is multiplexed. The modulator scales the average segment current in 16 steps in exactly the same way as global intensity adjustment. Table 26 shows the global intensity register format, Table 27 shows individual segment intensity registers, Table 28 is the even individual segment intensity format, and Table 29 is the odd individual segment intensity format.

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 6. Register Address Map
REGISTER No-Op Decode Mode Global Intensity Scan Limit Configuration GPIO Data Port Configuration Display Test Write KEY_A Mask Read KEY_A Debounce Write KEY_B Mask Read KEY_B Debounce Write KEY_C Mask Read KEY_C Debounce Write KEY_D Mask Read KEY_D Debounce Write Digit Type Read KEY_A Pressed Read KEY_B Pressed* Read KEY_C Pressed* Read KEY_D Pressed* Intensity 10 Intensity 32 Intensity 54 Intensity 76 Intensity 10a (7 Segment Only) Intensity 32a (7 Segment Only) Intensity 54a (7 Segment Only) Intensity 76a (7 Segment Only) Digit 0 Plane P0 Digit 1 Plane P0 Digit 2 Plane P0 Digit 3 Plane P0 Digit 4 Plane P0 Digit 5 Plane P0 Digit 6 Plane P0 Digit 7 Plane P0 Digit 0a Plane P0 (7 Segment Only) Digit 1a Plane P0 (7 Segment Only) Digit 2a Plane P0 (7 Segment Only) Digit 3a Plane P0 (7 Segment Only) ADDRESS (COMMAND BYTE) D15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B

*Do NOT write to register.

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 6. Register Address Map (continued)
REGISTER Digit 4a Plane P0 (7 Segment Only) Digit 5a Plane P0 (7 Segment Only) Digit 6a Plane P0 (7 Segment Only) Digit 7a Plane P0 (7 Segment Only) Digit 0 Plane P1 Digit 1 Plane P1 Digit 2 Plane P1 Digit 3 Plane P1 Digit 4 Plane P1 Digit 5 Plane P1 Digit 6 Plane P1 Digit 7 Plane P1 Digit 0a Plane P1 (7 Segment Only) Digit 1a Plane P1 (7 Segment Only) Digit 2a Plane P1 (7 Segment Only) Digit 3a Plane P1 (7 Segment Only) Digit 4a Plane P1 (7 Segment Only) Digit 5a Plane P1 (7 Segment Only) Digit 6a Plane P1 (7 Segment Only) Digit 7a Plane P1 (7 Segment Only) Write Digit 0 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 1 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 2 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 3 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 4 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 5 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 6 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 7 Planes P0 and P1 with Same Data, Reads as 0x00 Write Digit 0a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 Write Digit 1a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 D15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D14 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ADDRESS (COMMAND BYTE) D13 D12 D11 D10 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0x2C 0x2D 0x2E 0x2F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 6. Register Address Map (continued)
REGISTER Write Digit 2a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 Write Digit 3a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 Write Digit 4a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 Write Digit 5a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 Write Digit 6a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 Write Digit 7a Planes P0 and P1 with Same Data (7 Segment Only), Reads as 0x00 ADDRESS (COMMAND BYTE) D15 R/W R/W R/W R/W R/W R/W D14 1 1 1 1 1 1 D13 1 1 1 1 1 1 D12 0 0 0 0 0 0 D11 1 1 1 1 1 1 D10 0 0 1 1 1 1 D9 1 1 0 0 1 1 D8 0 1 0 1 0 1 HEX CODE 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F

Note: Unused register bits read as zero.

The timing in Figure 8 loops over time, with 32 keys experiencing a full key-scanning debounce over typically 25.6ms. Four keys are sampled every 1.6ms, or every multiplex cycle. If at least one key that was not previously pressed is found to have been pressed during both sampling periods, then that key press is debounced, and an interrupt is issued. The key-scan circuit detects any combination of keys being pressed during each debounce cycle (n-key rollover).

Port Configuration Register

The port configuration register selects how the five port pins are used. The port configuration register format is described in Table 32.

Key Mask Registers The Key_A Mask, Key_B Mask, Key_C Mask, and Key_D Mask write-only registers (Table 33) configure the key-scanning circuit to cause an interrupt only when selected (masked) keys have been debounced. Each bit in the register corresponds to one key switch. The bit is clear to disable interrupt for the switch, and set to enable interrupt. Keys are always scanned (if enabled through the port configuration register), regardless of the setting of these interrupt bits, and the key status is stored in the appropriate Key_x pressed register. Key Debounced Registers The Key_A debounced, Key_B debounced, Key_C debounced, and Key_D debounced read-only registers (Table 34) show which keys have been detected as debounced by the key-scanning circuit.

Each bit in the register corresponds to one key switch. The bit is set if the switch has been correctly debounced since the register was read last. Reading a debounced register clears that register (after the data has been read) so that future keys pressed can be identified. If the debounced registers are not read, the key-scan data accumulates. However, as there is no FIFO in the MAX6954, the user is not able to determine key order, or whether a key has been pressed more than once, unless the debounced key status registers are read after each interrupt, and before the next keyscan cycle. Reading any of the four debounced registers clears the IRQ output. If a key is pressed and held down, the key is reported as debounced (and IRQ issued) only once. The key must be detected as released by the key-scanning circuit, before it debounces again. If the debounced registers are being read in response to the IRQ being asserted, then the user should generally read all four registers to ensure that all the keys that were detected by the key-scanning circuit are discovered.

Key Pressed Registers The Key_A pressed, Key_B pressed, Key_C pressed, and Key_D pressed read-only registers (Table 35) show which keys have been detected as pressed by the key-scanning circuit during the last test. Each bit in the register corresponds to one key switch. The bit is set if the switch has been detected as pressed by the key-scanning circuit during the last test.

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
ONE COMPLETE 1.6ms MULTIPLEX CYCLE AROUND 8 DIGITS 200s DIGIT 0 DIGIT 1 DIGIT 2 DIGIT 3 DIGIT 4 DIGIT 5 DIGIT 6 DIGIT 7 START OF NEXT CYCLE

DIGIT 0 CATHODE DRIVER INTENSITY SETTINGS DIGIT 0's 200s MULTIPLEX TIMESLOT 1/16TH (MIN ON) 2/16TH LOW 3/16TH LOW 4/16TH LOW 5/16TH LOW 6/16TH LOW 7/16TH LOW 8/16TH LOW 9/16TH LOW 10/16TH LOW 11/16TH LOW 12/16TH LOW 13/16TH LOW 14/16TH LOW 15/16TH LOW 15/16TH (MAX ON) HIGH-Z LOW CURRENT SOURCE ENABLED HIGH-Z MINIMUM 12.5s INTERDIGIT BLANKING INTERVAL HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z

ANODE (LIT)

ANODE (UNLIT) HIGH-Z

Figure 6. Multiplex Timing Diagram (OSC = 4MHz)

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
LED OUTPUT O0 SW A0 LED OUTPUT O1 SW A1 LED OUTPUT O2 SW A2 LED OUTPUT O3 SW A3 LED OUTPUT O4 SW A4 LED OUTPUT O5 SW A5 LED OUTPUT O6 SW A6 LED OUTPUT O7 VCC P0 P1 P2 P3 P4 MICROCONTROLLER INTERRUPT SW A7 SW B7 SW C7 SW D7 SW B6 SW C6 SW D6 SW B5 SW C5 SW D5 SW B4 SW C4 SW D4 SW B3 SW C3 SW D3 SW B2 SW C2 SW D2 SW B1 SW C1 SW D1 SW B0 SW C0 SW D0

Figure 7. Key-Scanning Configuration

THE FIRST HALF OF A 25.6ms KEY-SCAN CYCLE 1.6ms MULTIPLEX CYCLE 1 1.6ms MULTIPLEX CYCLE 2 1.6ms MULTIPLEX CYCLE 8

THE SECOND HALF OF A 25.6ms KEY-SCAN CYCLE 1.6ms MULTIPLEX CYCLE 1 1.6ms MULTIPLEX CYCLE 8

12.5s TO 187.5s DIGIT PERIOD LED OUTPUT O0 LED OUTPUT O1 LED OUTPUT O2 LED OUTPUT O3 LED OUTPUT O4 LED OUTPUT O5 LED OUTPUT O6 LED OUTPUT O7 A B C D E A FIRST TEST OF KEY SWITCHES SECOND TEST OF KEY SWITCHES INTERRUPT ASSERTED IF REQUIRED DEBOUNCE REGISTER UPDATED START OF NEXT KEY-SCAN CYCLE

Figure 8. Key-Scan Timing Diagram

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
The bit is cleared if the switch has not been detected as pressed by the key-scanning circuit during the last test. Reading a pressed register does not clear that register or clear the IRQ output.

Applications Information
Driving Bicolor LEDs
Bicolor digits group a red and a green die together for each display element, so that the element can be lit red or green (or orange), depending on which die (or both) is lit. The MAX6954 allows each segments current to be set individually from the 1/16th (minimum current and LED intensity) to 15/16th (maximum current and LED intensity), as well as off (zero current). Thus, a bicolor (red-green) segment pair can be set to 256 color/intensity combinations.

Display Test Register

The display test register (Table 36) operates in two modes: normal and display test. Display test mode turns all LEDs on (including DPs) by overriding, but not altering, all controls and digit registers (including the shutdown register), except for the digit-type register and the GPIO configuration register. The duty cycle, while in display test mode, is 7/16 (see the Choosing Supply Voltage to Minimize Power Dissipation section).

Selecting External Components RSET and CSET to Set Oscillator Frequency and Peak Segment Current
The RC oscillator uses an external resistor, RSET, and an external capacitor, CSET, to set the frequency, fOSC. The allowed range of fOSC is 1MHz to 8MHz. RSET also sets the peak segment current. The recommended values of RSET and CSET set the oscillator to 4MHz, which makes the blink frequencies selectable between 0.5Hz and 1Hz. The recommended value of RSET also sets the peak current to 40mA, which makes the segment current adjustable from 2.5mA to 37.5mA in 2.5mA steps. ISEG = KL / RSET mA fOSC = KF / (RSET x CSET) MHz where: KL = 2240 KF = 5376 RSET = external resistor in k CSET = external capacitor in pF CSTRAY = stray capacitance from OSC pin to GND in pF, typically 2pF The recommended value of RSET is 56k and the recommended value of CSET is 22pF. The recommended value or R SET is the minimum allowed value, since it sets the display driver to the maximum allowed peak segment current. RSET can be set to a higher value to set the segment current to a lower peak value where desired. The user must also ensure that the peak current specifications of the LEDs connected to the driver are not exceeded. The effective value of RSET includes not only the actual external capacitor used, but also the stray capacitance from OSC to GND. This capacitance is usually in the 1pF to 5pF range, depending on the layout used.
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Choosing Supply Voltage to Minimize Power Dissipation

The MAX6954 drives a peak current of 40mA into LEDs with a 2.2V forward-voltage drop when operated from a supply voltage of at least 3.0V. The minimum voltage drop across the internal LED drivers is therefore (3.0V 2.2V) = 0.8V. If a higher supply voltage is used, the driver absorbs a higher voltage, and the drivers power dissipation increases accordingly. However, if the LEDs used have a higher forward voltage drop than 2.2V, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.8V of headroom. The voltage drop across the drivers with a nominal 5V supply (5.0V - 2.2V) = 2.8V is nearly 3 times the drop across the drivers with a nominal 3.3V supply (3.3V 2.2V) = 1.1V. In most systems, consumption is an important design criterion, and the MAX6954 should be operated from the systems 3.3V nominal supply. In other designs, the lowest supply voltage may be 5V. The issue now is to ensure the dissipation limit for the MAX6954 is not exceeded. This can be achieved by inserting a series resistor in the supply to the MAX6954, ensuring that the supply decoupling capacitors are still on the MAX6954 side of the resistor. For example, consider the requirement that the minimum supply voltage to a MAX6954 must be 3.0V, and the input supply range is 5V 5%. Maximum supply current is 35mA + (40mA x 17) = 715mA. Minimum input supply voltage is 4.75V. Maximum series resistor value is (4.75V 3.0V)/0.715A = 2.44. We choose 2.2 5%. Worstcase resistor dissipation is at maximum toleranced resistance, i.e., (0.715A) 2 x (2.2 x 1.05) = 1.18W. The maximum MAX6954 supply voltage is at maximum input supply voltage and minimum toleranced resistance, i.e., 5.25V - (0.715A x 2.2 x 0.95) = 3.76V.

Low-Voltage Operation
The MAX6954 works over the 2.7V to 5.5V supply range. The minimum useful supply voltage is determined by the forward voltage drop of the LEDs at the

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peak current ISEG, plus the 0.8V headroom required by the driver output stages. The MAX6954 correctly regulates ISEG with a supply voltage above this minimum voltage. If the supply drops below this minimum voltage, the driver output stages may brown out, and be unable to regulate the current correctly. As the supply voltage drops further, the LED segment drive current becomes effectively limited by the output driver's onresistance, and the LED drive current drops. The characteristics of each individual LED in a display digit are well matched, so the result is that the display intensity dims uniformly as supply voltage drops out of regulation and beyond. Thus, for a 36-pin SSOP package (TJA = 1 / 0.0118 = +85C/W from Operating Ratings), the maximum allowed ambient temperature TA is given by: TJ(MAX) = TA + (PD x TJA) = +150C = TA + (0.700 x +85C/W) So TA = +90.5C. Thus, the part can be operated safely at a maximum package temperature of +85C.

MAX6954

Power Supplies
The MAX6954 operates from a single 2.7V to 5.5V power supply. Bypass the power supply to GND with a 0.1F capacitor as close to the device as possible. Add a 47F capacitor if the MAX6954 is not close to the board's input bulk decoupling capacitor.

Computing Power Dissipation

The upper limit for power dissipation (P D ) for the MAX6954 is determined from the following equation: PD = (V+ x 35mA) + (V+ - VLED) (DUTY x ISEG x N) where: V+ = supply voltage DUTY = duty cycle set by intensity register N = number of segments driven (worst case is 17) VLED = LED forward voltage at ISEG ISEG = segment current set by RSET PD = Power dissipation, in mW if currents are in mA Dissipation example: ISEG = 30mA, N = 17, DUTY = 15/16, VLED = 2.4V at 30mA, V+ = 3.6V PD = 3.6V (35mA) + (3.6V - 2.4V)(15/16 x 30mA x 17) = 0.700W

Terminating the Serial Interface

The MAX6954 uses fixed voltage thresholds of 0.6V and 1.8V for the 4-wire interface inputs. These fixed thresholds allow the MAX6954 to be controlled by a host operating from a lower supply voltage than the MAX6954; for example, 2.5V. The fixed thresholds also reduce the logic input noise margin when operating the MAX6954 from a higher supply voltage, such as 5V. At higher supply voltages, it may be necessary to fit termination components to the CLK, DIN, and CS inputs to avoid signal reflections that the MAX6954 could respond to as multiple transitions. Suitable termination components can be either a 33pF capacitor or 4.7k resistor fitted from each of the CLK, DIN, and CS inputs to GND.

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 7. 16-Segment Display Font Map
MSB LSB x000 x001 x010 x011 x100 x101 x110 x111

Table 8. 14-Segment Display Font Map

MSB LSB x000 x001 x010 x011 x100 x101 x110 x111

0000

0000

0001

0001

0010

0010

0011

0011

0100

0100

0101

0101

0110

0110

0111

0111

1000

1000

1001

1001

1010

1010

1011

1011

1100

1100

1101

1101

1110

1110

1111

1111
.

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 9. Digit Plane Data Register Format
MODE ADDRESS CODE (HEX) 0x20 to 0x2F 0x40 to 0x4F 0x60 to 0x6F 0x20 to 0x2F 0x40 to 0x4F 0x60 to 0x6F 0x20 to 0x2F 0x40 to 0x4F 0x60 to 0x6F 0x20 to 0x2F 0x40 to 0x4F 0x60 to 0x6F 0x20 to 0x2F 0x40 to 0x4F 0x60 to 0x6F REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0

14-segment or 16-segment mode, writing digit data to use font map data with decimal place unlit

Bits D6 to D0 select font characters 0 to 127

14-segment or 16-segment mode, writing digit data to use font map data with decimal place lit

Bits D6 to D0 select font characters 0 to 127

7-segment decode mode, DP unlit

D3 to D0

7-segment decode mode, DP lit

D3 to D0

7-segment no-decode mode

Direct control of 8 segments

Table 10. Segment Decoding for 7-Segment Displays

MODE ADDRESS CODE (HEX) 0x20 to 0x2F 0x40 to 0x4F 0x60 to 0x6F REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0

Segment Line

dp

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Table 11. 7-Segment Segment Mapping Decoder for Hexadecimal Font
7-SEGMENT CHARACTER D7* 0 1 2 3 4 5 6 7 8 9 A B C D E F REGISTER DATA D6, D5, D4 X X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DP* A 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 ON SEGMENTS = 1 B 1 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 C 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 D 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 E 1 0 1 0 0 0 1 0 1 0 1 1 1 1 1 1 F 1 0 0 0 1 1 1 0 1 1 1 1 1 0 1 1 G 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1

*The decimal point is set by bit D7 = 1.

Table 12. Digit-Type Register

DIGIT-TYPE REGISTER Output Drive Line Slot Identification ADDRESS CODE (HEX) 0x0C REGISTER DATA D7 CC7 Slot 4 D6 CC6 D5 CC5 Slot 3 D4 CC4 D3 CC3 Slot 2 D2 CC2 D1 CC1 Slot 1 D0 CC0

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Table 13. Example Configurations for Display Digit Combinations
DIGIT-TYPE REGISTER SETTING Digits 7 to 0 are 16-segment or 7segment digits. Digit 0 is a 14-segment digit, digits 7 to 1 are 16-segment or 7segment digits. Digits 2 to 0 are 14-segment digits, digits 7 to 3 are 16segment or 7-segment digits. Digits 7 to 0 are 14-segment digits. ADDRESS CODE (HEX) 0x0C REGISTER DATA D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0

0x0C

0x0C

0x0C

Table 14. Decode-Mode Register Examples

DECODE MODE No decode for digit pairs 7 to 0. Hexadecimal decode for digit pair 0, no decode for digit pairs 7 to 1. Hexadecimal decode for digit pairs 2 to 0, no decode for digit pairs 7 to 3. Hexadecimal decode for digit pairs 7 to 0. ADDRESS CODE (HEX) 0x01 0x01 0x01 0x01 REGISTER DATA D7 0 0 0 1 D6 0 0 0 1 D5 0 0 0 1 D4 0 0 0 1 D3 0 0 0 1 D2 0 0 1 1 D1 0 0 1 1 D0 0 1 1 1 HEX CODE 0x00 0x01 0x07 0xFF

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Table 15. Initial Power-Up Register Status
REGISTER Decode Mode Global Intensity Scan Limit Control Register GPIO Data Port Configuration Display Test Key_A Mask Key_B Mask Key_C Mask Key_D Mask Digit Type Intensity10 Intensity32 Intensity54 Intensity76 Intensity10a Intensity32a Intensity54a Intensity76a Digit 0 Digit 1 Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 Digit 0a Digit 1a Digit 2a Digit 3a Digit 4a Digit 5a Digit 6a Digit 7a Key_A Debounced Key_B Debounced Key_C Debounced Key_D Debounced Key_A Pressed Key_B Pressed Key_C Pressed Key_D Pressed POWER-UP CONDITION Decode mode enabled 1/16 (min on) Display 8 digits: 0, 1, 2, 3, 4, 5, 6, 7 Shutdown enabled, blink speed is slow, blink disabled Outputs are low No key scanning, P0 to P4 are all inputs Normal operation None of the keys cause interrupt None of the keys cause interrupt None of the keys cause interrupt None of the keys cause interrupt All are 16 segment or 7 segment 1/16 (min on) 1/16 (min on) 1/16 (min on) 1/16 (min on) 1/16 (min on) 1/16 (min on) 1/16 (min on) 1/16 (min on) Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes Blank digit, both planes No key presses have been detected No key presses have been detected No key presses have been detected No key presses have been detected Keys are not pressed Keys are not pressed Keys are not pressed Keys are not pressed ADDRESS CODE (HEX) 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F REGISTER DATA D7 1 X X 0 X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 1 X X 0 X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 1 X X X X 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 1 X X X 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 0 X 0 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D2 1 0 1 0 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D1 1 0 1 0 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 16. Configuration Register Format
MODE Configuration Register REGISTER DATA D7 P D6 I D5 R D4 T D3 E D2 B D1 X D0 MODE S Shutdown Normal Operation D7 P P D6 I I

Table 17. Shutdown Control (S Data Bit DO) Format

REGISTER DATA D5 R R D4 T T D3 E E D2 B B D1 X X D0 0 1

Table 18. Blink Rate Selection (B Data Bit D2) Format

MODE Slow blinking. Segments blink on for 1s, off for 1s with fOSC = 4MHz. Fast blinking. Segments blink on for 0.5s, off for 0.5s with fOSC = 4MHz. REGISTER DATA D7 P P D6 I I D5 R R D4 T T D3 E E D2 0 1 D1 X X D0 S S

Table 19. Global Blink Enable/Disable (E Data Bit D3) Format

MODE Blink function is disabled. Blink function is enabled. D7 P P D6 I I D5 R R REGISTER DATA D4 D3 T 0 T 1 D2 B B D1 X X D0 S S

Table 20. Digit Register Mapping with Blink Globally Enabled

SEGMENTS BIT SETTING IN PLANE P1 0 0 1 1 SEGMENTS BIT SETTING IN PLANE P0 0 1 0 1 Segment off. Segment on only during the 1st half of each blink period. Segment on only during the 2nd half of each blink period. Segment on. SEGMENT BEHAVIOR

Table 21. Global Blink Timing Synchronization (T Data Bit D4) Format
MODE Blink timing counters are unaffected. Blink timing counters are reset on the rising edge of CS. REGISTER DATA D7 P P D6 I I D5 R R D4 0 1 D3 E E D2 B B D1 X X D0 S S

Table 22. Global Clear Digit Data (R Data Bit D5) Format
MODE Digit data for both planes P0 and P1 are unaffected. Digit data for both planes P0 and P1 are cleared on the rising edge of CS. REGISTER DATA D7 P P D6 I I D5 0 1 D4 T T D3 E E D2 B B D1 X X D0 S S

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Table 23. Global Intensity (I Data Bit D6) Format
MODE Intensity for all digits is controlled by one setting in the global intensity register. Intensity for digits is controlled by the individual settings in the intensity10 and intensity76 registers. REGISTER DATA D7 P P D6 0 1 D5 R R D4 T T D3 E E D2 B B D1 X X D0 S S

Table 24. Blink Phase Readback (P Data Bit D7) Format

MODE P1 Blink Phase P0 Blink Phase D7 0 1 D6 I I D5 R R REGISTER DATA D4 D3 T E T E D2 B B D1 X X D0 S S

Table 25. Scan-Limit Register Format

SCAN LIMIT Display Digit 0 only Display Digits 0 and 1 Display Digits 0 1 2 Display Digits 0 1 2 3 Display Digits 0 1 2 3 4 Display Digits 0 1 2 3 4 5 Display Digits 0 1 2 3 4 5 6 Display Digits 0 1 2 3 4 5 6 7 ADDRESS CODE (HEX) 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 REGISTER DATA D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 X X X X X X X X D3 X X X X X X X X D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 HEX CODE 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07

Table 26. Global Intensity Register Format

DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) TYPICAL SEGMENT CURRENT (mA) 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 37.5 ADDRESS CODE (HEX) 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 REGISTER DATA D7 X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X D4 X X X X X X X X X X X X X X X X D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7 0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF

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Table 27. Individual Segment Intensity Registers
REGISTER FUNCTION Intensity10 Register Intensity32 Register Intensity54 Register Intensity76 Register Intensity10a Register Intensity32a Register Intensity54a Register Intensity76a Register ADDRESS CODE (HEX) 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 REGISTER DATA D7 D6 Digit 1 Digit 3 Digit 5 Digit 7 Digit 1a (7 segment only) Digit 3a (7 segment only) Digit 5a (7 segment only) Digit 7a (7 segment only) D5 D4 D3 D2 Digit 0 Digit 2 Digit 4 Digit 6 Digit 0a (7 segment only) Digit 2a (7 segment only) Digit 4a (7 segment only) Digit 6a (7 segment only) D1 D0

Table 28. Even Individual Segment Intensity Format

DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) TYPICAL SEGMENT CURRENT (mA) 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 37.5 ADDRESS CODE (HEX) 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 See Table 29. REGISTER DATA D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX CODE 0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7 0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF

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Table 29. Odd Individual Segment Intensity Format
DUTY CYCLE 1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on) TYPICAL SEGMENT CURRENT (mA) 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 37.5 ADDRESS CODE (HEX) 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 0x10 to 0x17 REGISTER DATA D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 See Table 28. D3 D2 D1 D0 HEX CODE 0x0X 0x1X 0x2X 0x3X 0x4X 0x5X 0x6X 0x7X 0x8X 0x9X 0xAX 0xBX 0xCX 0xDX 0xEX 0xFX

Table 30. GPIO Data Register

MODE Write GPIO Data Read GPIO Data ADDRESS CODE (HEX) 0x05 0x85 D7 X 0 D6 X 0 D5 X 0 REGISTER DATA D4 D3 P4 P4 or IRQ status P3 P3 D2 P2 P2 D1 P1 P1 D0 P0 P0

Table 31. Port Scanning Function Allocation

KEYS SCANNED None 1 to 8 9 to 16 17 to 24 25 to 36 PORTS AVAILABLE 5 pins 3 pins 2 pins 1 pin None P0 GPIO Key_A Key_A Key_A Key_A P1 GPIO GPIO Key_B Key_B Key_B P2 GPIO GPIO GPIO Key_C Key_C P3 GPIO GPIO GPIO GPIO Key_D P4 GPIO IRQ IRQ IRQ IRQ

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Table 32. Port Configuration Register Format
MODE ADDRESS CODE (HEX) D7 D6 D5 REGISTER DATA D4 D3 D2 D1 D0

GPIO 0x06 Set number of keys scanned Configuration Register PORT ALLOCATION OPTIONS 0 Keys Scanned 0x06 0 0 0 8 Keys Scanned 0x06 0 0 1 16 Keys Scanned 0x06 0 1 0 24 Keys Scanned 0x06 0 1 1 32 Keys Scanned 0x06 1 X X EXAMPLE PORT CONFIGURATION SETTINGS No Keys Scanned, P4 and 0x06 0 0 0 P2 Are Outputs, Others Are Inputs 8 Keys Scanned, P3 and P1 Are 0x06 0 0 1 Outputs, P2 Is an Input 32 Keys Scanned, No 0x06 1 X X GPIO Ports

Set port direction for ports P0 to P4: 0 = output, 1 = input P4 IRQ IRQ IRQ IRQ P3 P3 P3 P3 Key_D P2 P2 P2 Key_C Key_C P1 P1 Key_B Key_B Key_B P0 Key_A Key_A Key_A Key_A

Table 33. Key Mask Register Format

KEY MASK REGISTER Key_A Mask Register Key_B Mask Register Key_C Mask Register Key_D Mask Register ADDRESS CODE (HEX 0x08 0x09 0x0A 0x0B REGISTER DATA WITH APPROPRIATE SWITCH NAMED BELOW D7 SW_A7 SW_B7 SW_C7 SW_ D7 D6 SW_A6 SW_B6 SW_C6 SW_D6 D5 SW_A5 SW_B5 SW_C5 SW_D5 D4 SW_A4 SW_B4 SW_C4 SW_D4 D3 SW_A3 SW_B3 SW_C3 SW_D3 D2 SW_A2 SW_B2 SW_C2 SW_D2 D1 SW_A1 SW_B1 SW_C1 SW_D1 D0 SW_A0 SW_B0 SW_C0 SW_D0

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Table 34. Key Debounced Register Format
KEY DEBOUNCED REGISTER Key_A Debounced Register Key_B Debounced Register Key_C Debounced Register Key_D Debounced Register ADDRESS CODE (HEX) 0x88 REGISTER DATA D7 SW_A7 D6 SW_A6 D5 SW_A5 D4 SW_A4 D3 SW_A3 D2 SW_A2 D1 SW_A1 D0 SW_A0

0x89

SW_B7

SW_B6

SW_B5

SW_B4

SW_B3

SW_B2

SW_B1

SW_B0

0x8A

SW_C7

SW_C6

SW_C5

SW_C4

SW_C3

SW_C2

SW_C1

SW_C0

0x8B

SW_D7

SW_D6

SW_D5

SW_D4

SW_D3

SW_D2

SW_D1

SW_D0

Table 35. Key Pressed Register Format

KEY PRESSED REGISTER Key_A Pressed Register Key_B Pressed Register Key_C Pressed Register Key_D Pressed Register ADDRESS CODE (HEX 0x8C REGISTER DATA D7 SW_A7 D6 SW_A6 D5 SW_A5 D4 SW_A4 D3 SW_A3 D2 SW_A2 D1 SW_A1 D0 SW_A0

0x8D

SW_B7

SW_B6

SW_B5

SW_B4

SW_B3

SW_B2

SW_B1

SW_B0

0x8E

SW_C7

SW_C6

SW_C5

SW_C4

SW_C3

SW_C2

SW_C1

SW_C0

0x8F

SW_D7

SW_D6

SW_D5

SW_D4

SW_D3

SW_D2

SW_D1

SW_D0

Table 36. Display Test Register

MODE Normal Operation Display Test ADDRESS CODE (HEX) 0x07 0x07 REGISTER DATA D7 X X D6 X X D5 X X D4 X X D3 X X D2 X X D1 X X D0 0 1

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Table 37. Slot 1 Configuration
CC0: (2) 7-seg monocolor* or 7-seg bicolor CC1: (2) 7-seg monocolor* or 7-seg bicolor CC0 and CC1: (2) 14-seg monocolor or 14-seg bicolor CC0 CC1 a b c d e f g1 g2 h i j k l m dp 1 1 CC0 and CC1: (2) 7-seg bicolor or (4) 7-seg monocolor or (1) 7-seg bicolor and (2) 7-seg monocolor* CC0: 16-seg monocolor CC1: 16-seg monocolor CC0: 16-seg monocolor CC1: 14-seg monocolor CC0: 14-seg monocolor CC1: 16-seg monocolor CC1 a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp

00 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 ADDRESS CODE (HEX) D7 REGISTER DATA D6 D5 D4 D3 D2 D1 D0

CC0 a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp

CC1 a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp

CC0 CC1 1a 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

CC0 CC1 a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp

CC0 and CC1: (1)16-seg bicolor

CONFIGURATION CHOICE Common-Cathode Drive: Digit Type

CC0 a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp

CC0 1a 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp 0x0C

CC1 a b c d e f g1 g2 h i j k l m dp

CC0 a b c d e f g1 g2 h i j k l m dp

CC1 1a 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

See Table 40. See Table 39. See Table 38. 0 0 1 0 0 1

*7-segment digits can be replaced by directly controlled discrete LEDs according to settings in decode mode register (Table 11). **The highlighted row is used in Typical Operating Circuit 1 for display digits 0 and 1.

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Table 38. Slot 2 Configuration
CC2: (2) 7-seg monocolor* or 7-seg bicolor CC3: (2) 7-seg monocolor* or 7-seg bicolor CC2 and CC3: (2) 14-seg monocolor or 14-seg bicolor a CC2 CC3 b c d e f g1 g2 h i j k l m dp 1 1 CC2 and CC3: (2) 7-seg bicolor or (4) 7-seg monocolor or (1) 7-seg bicolor and (2) 7-seg monocolor* CC2: 16-seg monocolor CC3: 16-seg monocolor CC2: 16-seg monocolor CC3: 14-seg monocolor CC2: 14-seg monocolor CC3: 16-seg monocolor a1 a2 CC3 b c d1 d2 e f g1 g2 h i j k l m dp

00 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 ADDRESS CODE (HEX) D7 REGISTER DATA D6 D5 D4 D3 D2 D1 D0

a1 a2 CC2 b c d1 d2 e f g1 g2 h i j k l m dp

a1 a2 CC3 b c d1 d2 e f g1 g2 h i j k l m dp

1a CC2 CC3 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

CC2 and CC3: (1)16-seg bicolor a1 a2 CC2 CC3 b c d1 d2 e f g1 g2 h i j k l m dp

CONFIGURATION CHOICE Common-Cathode Drive: Digit Type

a1 a2 CC2 b c d1 d2 e f g1 g2 h i j k l m dp

1a CC2 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp 0x0C

a CC3 b c d e f g1 g2 h i j k l m dp

a CC2 b c d e f g1 g2 h i j k l m dp

1a CC3 1b 1c 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

See Table 40. See Table 39. 0 0 1 0 See Table 37. 0 1

*7-segment digits can be replaced by directly controlled discrete LEDs according to settings in decode mode register (Table 11). **The highlighted row is used in Typical Operating Circuit 1 for display digits 2 and 3.

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Table 39. Slot 3 Configuration
CC4: (2) 7-seg monocolor* or 7-seg bicolor CC5: (2) 7-seg monocolor* or 7-seg bicolor CC4 and CC5: (2) 14-seg monocolor or 14-seg bicolor a b c CC4 CC5 d e f g1 g2 h i j k l m dp 1 1 CC4 and CC5: (2) 7-seg bicolor or (4) 7-seg monocolor or (1) 7-seg bicolor and (2) 7-seg monocolor* CC4: 16-seg monocolor CC5: 16-seg monocolor CC4: 16-seg monocolor CC5: 14-seg monocolor CC4: 14-seg monocolor CC5: 16-seg monocolor a1 a2 b c CC5 d1 d2 e f g1 g2 h i j k l m dp

00 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 ADDRESS CODE (HEX) D7 REGISTER DATA D6 D5 D4 D3 D2 D1 D0

a1 a2 b c CC4 d1 d2 e f g1 g2 h i j k l m dp

a1 a2 b c CC5 d1 d2 e f g1 g2 h i j k l m dp

1a 1b 1c CC4 CC5 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

CC4 and CC5: (1)16-seg bicolor a1 a2 b c CC4 CC5 d1 d2 e f g1 g2 h i j k l m dp

CONFIGURATION CHOICE Common-Cathode Drive: Digit Type

a1 a2 b c CC4 d1 d2 e f g1 g2 h i j k l m dp

1a 1b 1c CC4 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp 0x0C

a b c CC5 d e f g1 g2 h i j k l m dp

a b c CC4 d e f g1 g2 h i j k l m dp

1a 1b 1c CC5 1d 1dp 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

See Table 40. 0 0 1 0 See Table 38. See Table 37. 0 1

*7-segment digits can be replaced by directly controlled discrete LEDs according to settings in decode mode register (Table 11). **The highlighted row is used in Typical Operating Circuit 1 for display digits 4 and 5.

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Table 40. Slot 4 Configuration
CC6: (2) 7-seg monocolor* or 7-seg bicolor CC7: (2) 7-seg monocolor* or 7-seg bicolor CC6 and CC7: (2) 14-seg monocolor or 14-seg bicolor a b c d CC6 CC7 e f g1 g2 h i j k l m dp 1 1 CC6 and CC7: (2) 7-seg bicolor or (4) 7-seg monocolor or (1) 7-seg bicolor and (2) 7-seg monocolor* CC6: 16-seg monocolor CC7: 16-seg monocolor CC6: 16-seg monocolor CC7: 14-seg monocolor CC6: 14-seg monocolor CC7: 16-seg monocolor a1 a2 b c d1 d2 CC7 e f g1 g2 h i j k l m dp

00 01 02 03 04 05 06 07 08 09 010 011 012 013 014 015 016 017 018 ADDRESS CODE (HEX) D7 REGISTER DATA D6 D5 D4 D3 D2 D1 D0

a1 a2 b c d1 d2 CC6 e f g1 g2 h i j k l m dp

a1 a2 b c d1 d2 CC7 e f g1 g2 h i j k l m dp

1a 1b 1c 1d 1dp CC6 CC7 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

CC6 and CC7: (1)16-seg bicolor a1 a2 b c d1 d2 CC6 CC7 e f g1 g2 h i j k l m dp

CONFIGURATION CHOICE Common-Cathode Drive: Digit Type

a1 a2 b c d1 d2 CC6 e f g1 g2 h i j k l m dp

1a 1b 1c 1d 1dp CC6 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp 0x0C

a b c d CC7 e f g1 g2 h i j k l m dp

a b c d CC6 e f g1 g2 h i j k l m dp

1a 1b 1c 1d 1dp CC7 1e 1f 1g 2a 2b 2c 2d 2e 2f 2g 2dp

0 0

1 0 See Table 39. See Table 38. See Table 37.

0 1

*7-segment digits can be replaced by directly controlled discrete LEDs according to settings in the decode mode register (Table 11). **The highlighted row is used in Typical Operating Circuit 1 for display digits 6 and 7.

34

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Typical Operating Circuits
3.3V V+ V+ V+ 47F 100nF GND GND GND O0 O1 O2 O3 O4 O5 O6 O11 O12 O13 O14 O15 O16 O17 O18 O0 O1 a b c d e f g dp Rcc Gcc DIGIT 0b (RED), DIGIT 1b (GREEN) 7-SEGMENT BICOLOR LED O2 O4 O5 O6 O8 O9 O10 O7 a b c d e f g dp

MAX6954

O7 O8 O9 O10 O0 O4 O5 O6 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O2 O3

CLK DIN DOUT CS

O11 O12 O13 O14 O15

BLINK

O16 O17

OSC_OUT

O18 P0

OSC

P1 P2

22pF 56k

ISET

P3 P4

a b c d e f g1 g2 h i j k l m dp Rcc Ccc DIGITS 2 AND 3 14-SEGMENT BICOLOR

O1 O0

CC1 CC0 DIGITS 0a AND 1a 7-SEGMENT MONOCOLOR

O0 O2 O3 O4

O0 O2 O3 O4

O0 O1 O2 O3 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O5

a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 5 16-SEGMENT MONOCOLOR

O5 O8 O9 O10

O5 O8 O9 O10

O11 O12 O13 O14

O11 O12 O13 O14

O15 O16 O17 O18 O6 DIGIT 6 4 x 4 MATRIX OF DISCRETE MONOCOLOR LEDs

O15 O16 O17 O18 O7 DIGIT 7 4 x 4 MATRIX OF DISCRETE MONOCOLOR LEDs

O0 O1 O2 O3 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O4

a1 a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 4 16-SEGMENT MONOCOLOR

______________________________________________________________________________________

35

4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Typical Operating Circuits (continued)
3.3V V+ V+ V+ 47F 100nF GND GND GND O0 O1 O2 O3 O4 O5 O6 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O0 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 0 O0 O1 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O2 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 2 O0 O1 O2 O3 O6 O6 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O4 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 4 O0 O1 O2 O3 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O5 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 5 O0 O1 O2 O3 O4 O5 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O6 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 6 O0 O1 O2 O3 O4 O5 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O7 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 7 O0 O1 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O3 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 3 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O1 a a2 b c d1 d2 e f g1 g2 h i j k l m dp cc DIGIT 1

MAX6954

O7 O8 O9 O10

CLK DIN DOUT CS

O11 O12 O13 O14 O15

BLINK

O16 O17

OSC_OUT

O18 P0

OSC

P1 P2

22pF 56k

ISET

P3 P4

36

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
Pin Configurations

MAX6954

TOP VIEW
P0 P1 CS DOUT CLK DIN O0 O1 O2 1 2 3 4 5 6 7 8 9 36 P4 35 P3 34 P2 33 OSC_OUT 32 BLINK 31 O18 30 O17 29 O16 P0 1 P1 2 CS 3 DOUT 4 CLK 5 DIN 6 O0 7 O1 8 O2 9 O3 10 O4 11 O5 12 O6 13 O7 14 O8 15 N.C. 16 GND 17 GND 18 ISET 19 40 P4 39 P3 P2 OSC_OUT
33 32

38 P2 P1 P0 P4/IRQ P3 CLK 37 OSC_OUT 36 BLINK 35 O18 34 O17 33 O16 32 O15 DIN O0 O1 O2 O3 O4 O5 O6 O7 O8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

40

39

38

37

36

35

34

31

BLINK

DOUT CS

30 29 28 27 26 25 24 23 22 21 18 19 20

O18 O17 O16 O15 O14 O13 O12 O11 O10 O9

MAX6954AAX

28 O15 27 O14 26 O13 25 O12 24 O11 23 O10 22 O9 21 V+ 20 OSC 19 V+

O3 10 O4 11 O5 12 O6 13 O7 14 O8 15 GND 16 ISET 17 GND 18

MAX6954APL

31 O14 30 O13 29 O12 28 O11 27 O10 26 O9 25 N.C. 24 V+ 23 V+ 22 OSC 21 V+

MAX6954

EP*

GND ISET GND V+ OSC

V+

GND

N.C.

TQFN-EP
*EP = EXPOSED PAD. CONNECT EP TO GND.

SSOP

GND 20

PDIP

Chip Information
PROCESS: CMOS

______________________________________________________________________________________

V+ N.C.

37

4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan MAX6954
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 36 SSOP 40 PDIP 40 TQFN PACKAGE CODE A36-2 P40-2 T4066-5 DOCUMENT NO. 21-0040 21-0044 21-0140

38

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4-Wire Interfaced, 2.7V to 5.5V LED Display Driver with I/O Expander and Key Scan
Revision History
REVISION NUMBER 3 4 REVISION DATE 6/08 3/09 Added TQFN package option Corrected errors in Tables 3740 DESCRIPTION PAGES CHANGED 1, 2, 6, 37 3134

MAX6954

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