project2-exp1;

project5-expi2&deco_enco_mux_demux are exp2;

project8-flipflop_shiftregster_counters-exp3;
project8-seqdetector_serialadder_paritydetectors-exp4;

DSD

ADDERS - HALF ADDER

//data flow
module h2(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;

endmodule

//behavioural
module h2(a,b,sum,carry);
input a,b;
output reg sum,carry;
always @(*)
begin
sum=a^b;
carry=a&b;
end
endmodule

//gate level
module h2(a,b,sum,carry);
input a,b;
output sum,carry;
xor (sum,a,b);
or(carry,a,b);

endmodule

//test bench
module h2_tb();
reg a,b;
wire sum,carry;
h2 uut(a,b,sum,carry);
initial
begin
a=0;b=0;
#5 a=0;b=1;
#5 a=1;b=0;
#5 a=1;b=1;
#5 $finish;
end
endmodule

ADDERS - FULL ADDER

//gate level
module f2(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire s1,c1,c2;
xor(s1,a,b);
xor(sum,s1,c);
and(c1,a,b);
and(c2,s1,c);
or(carry,c1,c2);
endmodule

//data flow level

module f2(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire s1,c1,c2;
assign s1=a^b;
assign sum=s1^c;
assign c1=a&b;
assign c2=s1&c;
assign carry=c1|c2;
endmodule

//behavioural modelling
module f2(a,b,c,sum,carry);
input a,b,c;
output reg sum,carry;
always @(*)
begin
sum=a^b^c;
carry=(a&b)|(a^b&c);
end
endmodule

//test bench
module f2_tb();
reg a,b,c;
wire sum,carry;
f2 uut(a,b,c,sum,carry);
initial
begin
a=0;b=0;c=0;
#5 a=0;b=0;c=1;
#5 a=0;b=1;c=0;
#5 a=0;b=1;c=1;
#5 a=1;b=0;c=0;
#5 a=1;b=0;c=1;
#5 a=1;b=1;c=0;
#5 a=1;b=1;c=1;
#5 $finish;
end
endmodule
ADDERS - FULL ADDER USING 2 HALF ADDER

//behavioural
module fa_u_ha(s,c,a,b,c4);
input a,b,c4;
wire s1,c2,c1;
output s,c;
half h1(s1,c1,a,b);
half h2(s,c2,s1,c4);
or rl(c,c1,c2);
endmodule

module half(s,c,a,b);
input a,b;
output reg s,c;
always @ (*)
begin
s=a^b;
c=a&b;
end
endmodule

//data flow
module fa_u_ha(s,c,a,b,c4);
input a,b,c4;
wire s1,c2,c1;
output s,c;
half h1(s1,c1,a,b);
half h2(s,c2,s1,c4);
or rl(c,c1,c2);
endmodule

module half(s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

//gate level
module fa_u_ha(s,c,a,b,c4);
input a,b,c4;
wire s1,c2,c1;
output s,c;
half h1(s1,c1,a,b);
half h2(s,c2,s1,c4);
or rl(c,c1,c2);
endmodule

module half(s,c,a,b);
input a,b;
output s,c;
xor(s,a,b);
and(c,a,b);
endmodule
 //test bench

module fauha_t_b();
reg a,b,c4;
wire s,c;
fa_u_ha uut(s,c,a,b,c4);
initial
begin
c4=0; b=0; a=0;
#5 c4=0; b=0; a=1;
#5 c4=0; b=1; a=0;
#5 c4=0; b=1; a=1;
#5 c4=1; b=0; a=0;
#5 c4=1; b=0; a=1;
#5 c4=1; b=1; a=0;
#5 c4=1; b=1; a=1;
#5 $finish;
end
endmodule

ADDER-4 bit adder

1.//behavioural
module fourbitadd2(sum,carry,a,b);
input [3:0]a;
input [3:0]b;
output reg [3:0]sum;
output reg carry;
reg[2:0]cout;
always@(*)
begin
{cout[0],sum[0]}=a[0]+b[0]+0;
{cout[1],sum[1]}=a[1]+b[1]+cout[0];
{cout[2],sum[2]}=a[2]+b[2]+cout[1];
{carry,sum[3]}=a[3]+b[3]+cout[2];
end
endmodule

//data flow
module fourbitadd2(sum,carry,a,b);
input [3:0]a;
input [3:0]b;
output [3:0]sum;
output carry;
wire[2:0]cout;
assign{cout[0],sum[0]}=a[0]+b[0]+0;
assign{cout[1],sum[1]}=a[1]+b[1]+cout[0];
assign{cout[2],sum[2]}=a[2]+b[2]+cout[1];
assign{carry,sum[3]}=a[3]+b[3]+cout[2];
endmodule

//gate level
module fourbitadd2(sum,carry,a,b);
input [3:0]a;
input [3:0]b;
output [3:0]sum;
output carry;
wire [3:0]cout;
full_add u1(a[0],b[0],0,sum[0],cout[0]);
full_add u2(a[1],b[1],cout[0],sum[1],cout[1]);
full_add u3(a[2],b[2],cout[1],sum[2],cout[2]);
full_add u4(a[3],b[3],cout[2],sum[3],carry);
endmodule

module full_add(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire s1,c1,c2;
xor(s1,a,b);
xor(sum,s1,c);
and(c1,a,b);
and(c2,s1,c);
or(carry,c1,c2);
endmodule

//test bench
module fourbitadd2_tb();
reg [3:0]a;
reg [3:0]b;
wire [3:0]sum;
wire carry;
fourbitadd2 uut(sum,carry,a,b);
initial
begin
a=4'b0001;b=4'b0001;
#10 a=4'b0001;b=4'b0011;
#10 a=4'b0001;b=4'b000;
#10 a=4'b0111;b=4'b0011;
#10 $finish;
end
endmodule

2.module fourbitadd(s,cout,a,b,c );
input [3:0]a;
input [3:0]b;
input c;
output reg [3:0]s;
output reg cout;
reg[4:0]sum;
always@(*)
begin
sum=a+b+c;
s=sum[3:0];
cout=sum[4];
end
endmodule
//test bench
module fourbitadd_tb();
reg [3:0]a;
reg [3:0]b;
reg c;
wire [3:0]s;
wire cout;
fourbitadd uut(s,cout,a,b,c);
initial
 begin
a=4'b0000; b=4'b0000;c=1'b1;
#10 a=4'b0001; b=4'b0001;c=1'b0;
#10 $finish;
end
endmodule

SUBSTRACTOR - HALF

//gate level
module hs2(a,b,diff,borrow);
input a,b;
output diff,borrow;
wire x;
xor(diff,a,b);
not(x,a);
and(borrow,x,b);
endmodule

//data flow
module hs2(a,b,diff,borrow);
input a,b;
output diff,borrow;
wire x;
assign diff=a^b;
assign x=~a;
assign borrow=x&b;
endmodule

//behavioural
module hs2(a,b,diff,borrow);
input a,b;
output reg diff,borrow;
always @(*)
begin
diff=a^b;
borrow=~a&b;
end
endmodule

//test bench
module hs2_tb();
reg a,b;
wire diff,borrow;
hs2 uut(a,b,diff,borrow);
initial
begin
a=0;b=0;
#5 a=0;b=1;
#5 a=1;b=0;
#5 a=1;b=1;
#5 $finish;
end
endmodule

SUBSTRACTOR - FULL

//data flow
module fs(diff,borrow,a,b,c);
input a,b,c;
output diff,borrow;
wire s1,s2;
assign diff=a^b^c;
assign s1=(~a)&b;
assign s2=~(a^b)&c;
assign borrow=s1|s2;
endmodule

//gate level
module fs(diff,borrow,a,b,c);
input a,b,c;
output diff,borrow;
wire s1,s2,n1,L,n2;
xor (L,a,b);
xor(diff,L,c);
and(n1,a);
and(s1,n1,b);
not(n2,L);
and(s2,n2,c);
or(borrow,s1,s2);
endmodule

//behavioural
module fs(diff,borrow,a,b,c);
input a,b,c;
output reg diff,borrow;
always @ (*)
begin
diff=a^b^c;
borrow=(~a&b)|(~(a^b)&c);
end
endmodule

//test bench
module fs_tb( );
reg a ,b,c;
wire diff,borrow;
fs uut(diff,borrow,a,b,c);
initial
begin
c=1'b0; b=1'b0; a=1'b0;
#5 c=1'b0; b=1'b0; a=1'b1;
#5 c=1'b0; b=1'b1; a=1'b0;
#5 c=1'b0; b=1'b1; a=1'b1;
#5 c=1'b1; b=1'b0; a=1'b0;
#5 c=1'b1; b=1'b0; a=1'b1;
#5 c=1'b1; b=1'b1; a=1'b0;
#5 c=1'b1; b=1'b1; a=1'b1;
#5 $finish;
end
endmodule

MULTIPLIERS - 2 BIT(2X2)

//gate level
module twobitmul(p,a,b);
input [1:0]a;
input [1:0]b;
output [3:0]p;
wire a1,a2,a3,a4;
and(p[0],a[0],b[0]);
and(a1,a[1],b[0]);
and(a2,a[0],b[1]);
xor(p[1],a1,a2);
and(a3,a1,a2);
and(a4,a[1],b[1]);
xor(p[2],a3,a4);
and(p[3],a4,a3);
endmodule

//data flow
module twobitmul(p,a,b);
input [1:0]a;
input [1:0]b;
output [3:0]p;
assign p=a*b;
endmodule

//behavioral
module twobitmul(p,a,b);
input [1:0]a;
input [1:0]b;
output reg [3:0]p;
always@(*)
begin
p=a*b;
end
endmodule

//test bench
module twobitmul_tb();
reg [1:0]a;
reg [1:0]b;
wire[3:0]p;
twobitmul uut(p,a,b);
initial
begin
a=2'b00; b=2'b00;
#10 a=2'b11; b=2'b11;
#10a=2'b10; b=2'b11;
#10a=2'b11; b=2'b01;
#10 $finish;
end
endmodule
CODE CONVERTERS -
1. BINARY TO BCD
//data flow
module bi_bcd(bo,bi);
input [3:0]bi;
output [4:0]bo;
assign bo[0]=bi[3];
assign bo[1]=(bi[0]&bi[1]&(~bi[2])) | ((~bi[0])&bi[2]);
assign bo[2]=((~bi[0])&bi[1]) | (bi[2]&bi[1]);
assign bo[3]=(bi[0]&(~bi[1])&(~bi[2]));
assign bo[4]=(bi[0]&bi[1]) | (bi[1]&bi[2]);
endmodule

//behavioural
module bi_bcd(bo,bi);
input [3:0]bi;
output reg [4:0]bo;
always@(*)
begin
case(bi)
4'b0000:bo=5'b0_0000;
4'b0001:bo=5'b0_0001;
4'b0010:bo=5'b0_0010;
4'b1010:bo=5'b1_0000;
4'b1011:bo=5'b1_0001;
4'b1100:bo=5'b1_0010;
4'b1011:bo=5'b1_0011;
4'b1110:bo=5'b1_0100;
4'b1111:bo=5'b1_0101;
default:bo=5'bXXXXX;
endcase
endmodule

//gate level
module bi_bcd(bo,bi);
input [3:0]bi;
output [4:0]bo;
wire notbi0,notbi1,notbi2;
wire [5:0]y;
not n1(notbi0,bi[0]);
not n2(notbi1,bi[1]);
not n3(notbi2,bi[2]);
and a1(y[0],bi[0],bi[1]);
and a2(y[1],bi[1],bi[2]);
or o1(bo[4],y[0],y[1]);
and a3(bo[3],notbi1,notbi2);
and a4(y[2],notbi0,bi[1]);
and a5(y[3],bi[1],bi[2]);
or o2(bo[2],y[2],y[3]);
 and a6(y[4],bi[0],bi[1],notbi2);
and a7(y[5],notbi0,bi[2]);
or o3(bo[1],y[4],y[5]);
buf o4(bo[0],bi[3]);
endmodule

//test bench
module bi_bcd_tb();
reg [3:0]bi;
wire[4:0]bo;
bi_bcd uut(.bo(bo),.bi(bi));
initial
begin
bi=4'b1100;
#5 bi=4'b1011;
#5 bi=4'b1010;
#5 $finish;
end
endmodule

2.BINARY TO GRAY

//behavioural
module bi_gray(b,g);
input [3:0]b;
output reg [3:0]g;
always @(b) begin
g[3]=b[3];
g[2]=b[3]^b[2];
g[1]=b[2]^b[1];
g[0]=b[1]^b[0];
end
endmodule

//data flow
module bi_gray(b,g);
input [3:0]b;
output [3:0]g;
assign g[3] = b[3];
assign g[2] = b[3]^b[2];
assign g[1] = b[2]^b[1];
assign g[0] = b[1]^b[0];
endmodule

//gate level
module bi_gray(b,g);
input [3:0]b;
output [3:0]g;
buf b1(g[3],b[3]);
xor x3(g[2],b[3],b[2]);
xor x2(g[1],b[2],b[1]);
xor x1(g[0],b[1],b[0]);
endmodule

//test bench
module bi_gray_tb();
reg [3:0] b;
wire [3:0] g;
bi_gray uut(.b(b),.g(g));
initial begin
b =4'b0000;
#1 b =4'b0010;
#1 b =4'b1010;
#1 b =4'b1111;
#1 b =4'b0111;
#1 b =4'b0100;
#20 $finish;
end
endmodule

3.BCD TO EXCESS3

//behavioural
module bcd_excess(e,b);
input[3:0]b;
output reg [3:0]e;
always @(b)
begin
e[3]=b[3]|b[2]&b[1]|b[2]&b[0];
e[2]=~b[2]&b[1]|~b[2]&b[0]|b[2]&~b[1]&~b[0];
e[1]=b[1]&b[0]|~b[1]&~b[0];
e[0]=~b[0];
end
endmodule

//data flow
module bcd_excess(e,b);
input[3:0]b;
output [3:0]e;
assign e[3]=b[3]|b[2]&b[1]|b[2]&b[0];
assign e[2]=~b[2]&b[1]|~b[2]&b[0]|b[2]&~b[1]&~b[0];
assign e[1]=b[1]&b[0]|~b[1]&~b[0];
assign e[0]=~b[0];
endmodule

//gate level
module bcd_excess(e,b);
input[3:0]b;
output [3:0]e;
wire notbo,notb1,notb2;
wire [9:1]t;
not no(notbo,b[0]);
not n1(notb1,b[1]);
not n2(notb2,b[2]);
and a1(t[1],b[2],b[1]);
and a2(t[2],b[2],b[0]);
and a3(t[4],notb2,b[1]);
and a4(t[5],notb2,b[0]);
and a5(t[7],b[2],notbo,notb1);
and a6(t[8],b[1],b[0]);
and a7(t[9],notbo,notb1);
buf go(e[0],notbo);
or o1(t[3],t[1],t[2]);
or o2(e[3],t[3],b[3]);
or o3(t[6],t[4],t[5]);
or o4(e[2],t[6],t[7]);
or o5(e[1],t[8],t[9]);
endmodule

//test bench

module bcd_excess_tb();
reg [3:0] b;
wire [3:0] e;
bcd_excess uut(.b(b),.e(e));
initial
begin

b=4'b0000;
#10 b=4'b0001;
#10 b=4'b0010;
#10 b=4'b0011;
#10 b=4'b0100;
#10 b=4'b0101;
#10 b=4'b0110;
#10 b=4'b0111;
#10 b=4'b1000;
#10 b=4'b1001;
end
endmodule

MULTIPLEXERS - 4x1

//behavioural
module mux4x1(out,i0,i1,i2,i3,s0,s1);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output reg out;
always @(*)
begin
if(s1==0 & s0==0)
out=i0;
else if(s1==0 & s0==1)
out=i1;
else if(s1==1 & s0==0)
out=i2;
else if(s1==1 & s0==1)
out=i3;
end
endmodule

//data flow
module mux4x1(out,i0,i1,i2,i3,s0,s1);
input i0;
input i1;
input i2;
 input i3;
input s0;
input s1;
output out;
assign out=s1?(s0?i3:i2):(s0?i1:i0);
endmodule

//gate level
module mux4x1(out,i0,i1,i2,i3,s0,s1);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s0bar,s1bar,t1,t2,t3,t4;
not n1(s0bar,s0);
not n2(s1bar,s1);
and a1(t1,i0,s1bar,s0bar);
and a2(t2,i1,s1bar,s0);
and a3(t3,i2,s1,s0bar);
and a4(t4,i3,s1bar,s0);
or o1(out,t1,t2,t3,t4);
endmodule

//test bench

module mux4x1_tb();
reg i0,i1,i2,i3,s0,s1;
wire out;
mux4x1 uut(out,i0,i1,i2,i3,s0,s1);
initial
begin
i0=1;i1=0;i2=1;i3=0;
s1=0;s0=0;
#10 s1=0;s0=1;
#10 s1=1;s0=0;
#10 s1=1;s0=1;
end
endmodule

MULTIPLEXER - 8X1

//behavioural modelling
module mux8x1(D0,D1,D2,D3,D4,D5,D6,D7,S0,S1, S2,OUT);
input D0,D1,D2,D3,D4,D5,D6,D7,S0,S1, S2;
output reg OUT;
always @(*)
begin
case({S2,S1,S0})
3'b000: OUT=D0;
3'b001: OUT=D1;
3'b010: OUT=D2;
3'b011: OUT=D3;
3'b100: OUT=D4;
 3'b101: OUT=D5;
3'b110: OUT=D6;
3'b111: OUT=D7;
default: OUT=1'b0;
endcase
end
endmodule

//gate level
module mux8x1(D0,D1,D2,D3,D4,D5,D6,D7,S0,S1,S2,OUT);
input D0,D1,D2,D3,D4,D5,D6,D7,S0,S1,S2;
output OUT;
wire t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11;

not(t1, S0);
not(t2, S1);
not(t3, S2);

and(t4, D0, t1, t2, t3);

and(t5, D1, S0, t2, t3);
and(t6, D2, t1, S1, t3);
and(t7, D3, S0, S1, t3);
and(t8, D4, t1, t2, S2);
and(t9, D5, S0, t2, S2);
and(t10, D6, t1, S1, S2);
and(t11, D7, S0, S1, S2);

or(OUT, t4, t5, t6, t7, t8, t9, t10, t11);

endmodule

//data flow
module mux8x1(D0,D1,D2,D3,D4,D5,D6,D7,S0,S1,S2,OUT);
input D0,D1,D2,D3,D4,D5,D6,D7,S0,S1,S2;
output OUT;
wire s0bar, s1bar, s2bar;
assign s0bar = ~S0;
assign s1bar = ~S1;
assign s2bar = ~S2;
assign OUT = (D0 & s2bar & s1bar & s0bar) |(D1 & s2bar & s1bar & S0)|
(D2 & s2bar & S1 & s0bar)|(D3 & s2bar & S1 & S0)|
(D4 & S2 & s1bar & s0bar)|(D5 & S2 & s1bar & S0)|
(D6 & S2 & S1 & s0bar)|(D7 & S2 & S1 & S0);
endmodule

//test bench

module mux8x1_tb();
reg D0,D1,D2,D3,D4,D5,D6,D7,S0,S1, S2;
wire OUT;
mux8x1 uut(D0,D1,D2,D3,D4,D5,D6,D7,S0,S1, S2,OUT);
initial begin
D0=1'b0;D1=1'b0;D2=1'b0;D3=1'b0;D4=1'b0;D5=1'b0;D6=1'b0;D7=1'b0;
S0=1'b0;S1=1'b0;S2=1'b0;
#50 $finish;
end
always #1 D0=~D0;
always #2 D1=~D1;
always #3 D2=~D2;
always #4 D3=~D3;
always #5 D4=~D4;
always #6 D5=~D5;
always #7 D6=~D6;
always #8 D7=~D7;
always #9 S0=~S1;
always #10 S1=~S1;
always #11 S2=~S2;
endmodule

DEMULTIPLEXER - 1X4

//behavioural
module de_1x4(y0, y1, y2, y3, d, s0, s1);
input d, s0, s1;
output reg y0, y1, y2, y3;
always @ (d or s0 or s1)
case ({s1, s0})
2'b00: begin y0 = d; y1 = 1'b0; y2 = 1'b0; y3 = 1'b0; end
2'b01: begin y0 = 1'b0; y1 = d; y2 = 1'b0; y3 = 1'b0; end
2'b10: begin y0 = 1'b0; y1 = 1'b0; y2 = d; y3 = 1'b0; end
2'b11: begin y0 = 1'b0; y1 = 1'b0; y2 = 1'b0; y3 = d; end
default: {y0, y1, y2, y3} = 4'bxxxx; // Reset all outputs to 'xxxx'
endcase

endmodule

//gate level
module de_1x4(y0, y1, y2, y3, d, s0, s1);
input d, s0, s1;
output y0, y1, y2, y3;
wire s1n, s0n;
not(s1n,s1);
not(s0n,s0);
and(y0,d,s0n,s1n);
and(y1,d,s0,s1n);
and(y2,d,s0n,s1);
and(y3,d,s0,s1);
endmodule

//data flow
module de_1x4(y0, y1, y2, y3, d, s0, s1);
input d, s0, s1;
output y0, y1, y2, y3;
wire s1n, s0n;

assign s1n = ~s1;

assign s0n = ~s0;
assign y0 = d & s0n & s1n;
assign y1 = d & s0 & s1n;
assign y2 = d & s0n & s1;
assign y3 = d & s0 & s1;
endmodule

//test bench
module de_1x4_tb();
wire y0, y1, y2, y3;
reg d, s0, s1;
de_1x4 uut (.y0(y0),.y1(y1),.y2(y2),.y3(y3),.d(d),.s0(s0),.s1(s1)
);
initial begin
d = 1; s0 = 0; s1 = 0;
#100; d = 1; s0 = 1; s1 = 0;
#100; d = 1; s0 = 0; s1 = 1;
#100; d = 1; s0 = 1; s1 = 1;
#100 $finish;
end
endmodule

DEMULTIPLEXER - 1X8

//behavioural modelling
module de_1x8(d0,d1,d2,d3,d4,d5,d6,d7,s0,s1,s2,in);
input s0,s1,s2,in;
output reg d0,d1,d2,d3,d4,d5,d6,d7;
always @(*) begin
case({s2, s1, s0})
3'b000: begin d0 = in; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0; end
3'b001: begin d0 = 0; d1 = in; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0; end
3'b010: begin d0 = 0; d1 = 0; d2 = in; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0; end
3'b011: begin d0 = 0; d1 = 0; d2 = 0; d3 = in; d4 = 0; d5 = 0; d6 = 0; d7 = 0; end
3'b100: begin d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = in; d5 = 0; d6 = 0; d7 = 0; end
3'b101: begin d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = in; d6 = 0; d7 = 0; end
3'b110: begin d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = in; d7 = 0; end
3'b111: begin d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = in; end
default: begin d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 =0; end
endcase
end
endmodule

//gate level
module de_1x8(d0, d1, d2, d3, d4, d5, d6, d7, s0, s1, s2, in);
input s0, s1, s2, in;
output d0, d1, d2, d3, d4, d5, d6, d7;
wire nots0, nots1, nots2;

not n0(nots0, s0);

not n1(nots1, s1);
not n2(nots2, s2);
and a0(d0, in, nots0, nots1, nots2);
and a1(d1, in, s0, nots1, nots2);
and a2(d2, in, nots0, s1, nots2);
and a3(d3, in, s0, s1, nots2);
and a4(d4, in, nots0, nots1, s2);
and a5(d5, in, s0, nots1, s2);
and a6(d6, in, nots0, s1, s2);
and a7(d7, in, s0, s1, s2);
endmodule

//data flow
module de_1x8(
input in,
input s0,
input s1,
input s2,
output d0,
output d1,
output d2,
output d3,
output d4,
output d5,
output d6,
output d7
);
assign d0=(in & ~s2 & ~s1 &~s0);
assign d1=(in & ~s2 & ~s1 &s0);
assign d2=(in & ~s2 & s1 &~s0);
assign d3=(in & ~s2 & s1 &s0);
assign d4=(in & s2 & ~s1 &~s0);
assign d5=(in & s2 & ~s1 &s0);
assign d6=(in & s2 & s1 &~s0);
assign d7=(in & s2 & s1 &s0);
endmodule

//test bench

module de_1x8_tb( );
wire d0,d1,d2,d3,d4,d5,d6,d7;
reg in,s0,s1,s2;
de_1x8 uut(d0,d1,d2,d3,d4,d5,d6,d7,in,s0,s1,s2);
initial begin
in = 0;
s0 = 0;
s1 = 0;
s2 = 0;
#100;
in = 1; s0 = 0; s1 = 1; s2 = 0;
#100;
in = 1; s0 = 1; s1 = 1; s2 = 0;
#100;
in = 1; s0 = 1; s1 = 0; s2 = 0;
#100;
in = 1; s0 = 0; s1 = 0; s2 = 1;
#100;
in = 1; s0 = 1; s1 = 0; s2 = 1;
#100;
in = 1; s0 = 0; s1 = 1; s2 = 1;
#100;
in = 1; s0 = 1; s1 = 1; s2 = 1;
#100;
end
endmodule
ENCODER - 4X2

//behavioural modelling
module enco_4x2(d,y);
input [3:0]d;
output reg[1:0]y;
always @(d) begin
case(d)
4'b0001:y=2'b00;
4'b0010:y=2'b01;
4'b0100:y=2'b10;
4'b1000:y=2'b11;
endcase
end
endmodule

//data flow
module enco_4x2(d,y);
input [3:0]d;
output [1:0]y;
assign y[0]=(d[3]|d[1]);
assign y[1]=(d[3]|d[2]);
endmodule

//gate level
module enco_4x2(d,y);
input [3:0]d;
output [1:0]y;
or(y[0],d[3],d[1]);
or(y[1],d[3],d[2]);
endmodule

//test bench
module enco_4x2_tb();
reg [3:0]d;
wire [1:0]y;
enco_4x2 uut(d,y);
initial begin
d[3]=0;d[2]=0;d[1]=0;d[0]=0;
#10 d[3]=0;d[2]=0;d[1]=0;d[0]=1;
#10 d[3]=0;d[2]=0;d[1]=1;d[0]=0;
#10 d[3]=0;d[2]=1;d[1]=0;d[0]=0;
#10 d[3]=1;d[2]=0;d[1]=0;d[0]=0;
#10 $finish;
end
endmodule

ENCODER - 8X3
//behavioural modelling
module enco_8x3(din,dout);
 input [7:0]din;
output reg [2:0]dout;
always @(din) begin
if(din==8'b00000001) dout=3'b000;
else if(din==8'b00000010) dout=3'b001;
else if(din==8'b00000100) dout=3'b010;
else if(din==8'b00001000) dout=3'b011;
else if(din==8'b00010000) dout=3'b100;
else if(din==8'b00100000) dout=3'b101;
else if(din==8'b01000000) dout=3'b110;
else if(din==8'b10000000) dout=3'b111;
else dout=3'bX;
end
endmodule

//data flow
module enco_8x3(din,dout);
input [7:0]din;
output [2:0]dout;
assign dout[2]=(din[7]|din[6]|din[5]|din[4]);
assign dout[1]=(din[7]|din[6]|din[3]|din[2]);
assign dout[0]=(din[7]|din[5]|din[3]|din[1]);
endmodule

//gate level
module enco_8x3(din,dout);
input [7:0]din;
output [2:0]dout;
or g1(dout[0],din[1],din[3],din[5],din[7]);
or g2(dout[1],din[2],din[3],din[6],din[7]);
or g3(dout[2],din[4],din[5],din[6],din[7]);
endmodule

//test bench
module enco_8x3_tb();
reg [7:0]din;
wire [2:0]dout;
enco_8x3 uut(din,dout);
initial begin
din = 0; #10;
din = 8'b00000001; #10;
din = 8'b00000010; #10;
din = 8'b00000100; #10;
din = 8'b00001000; #10;
din = 8'b00010000; #10;
din = 8'b00100000; #10;
din = 8'b01000000; #10;
din = 8'b10000000; #10; //invalid
din = 8'b11000000; #10;// invalid
din = 8'b00000000; #10;
$display("test complete");
$finish;
end
endmodule
DECODER - 2x4
//gate level_2x4_ decoder
module decoder_2x4(d,E,y);
input [1:0]d;
input E;
output [3:0]y;
wire notd1, notd0;
not n1(notd1,d[1]);
not n2(notd0,d[0]);
and a1(y[3],E,d[1],d[0]);
and a2(y[2],E,d[1],notd0);
and a3(y[1], E, notd1,d[0]);
and a4(y[0], E, notd1, notd0);

endmodule

//behavioural modelling
module decoder_2x4(d,E,y);
input [1:0]d;
input E;
output reg[3:0]y;
always @(*) begin
if (E == 1) begin
case(d)
2'b00: y = 4'b0001;
2'b01: y = 4'b0010;
2'b10: y = 4'b0100;
2'b11: y = 4'b1000;
default: $display("INVALID");
endcase
end else begin
y = 0;
end
end
endmodule

//data flow
module decoder_2x4(d,E,y);
input [1:0]d;
input E;
output [3:0]y;
assign y[3] = E & d[1] & d[0];
assign y[2] = E & d[1] & (~d[0]);
assign y[1] = E & (~d[1]) & d[0];
assign y[0] = E & (~d[1]) & (~d[0]);
endmodule

//test bench
module decoder_2x4_tb();
reg [1:0]d;
reg E;
wire [3:0]y;
decoder_2x4 uut(d,E,y);
initial begin
E =0; #2; d=2'b11;
#2 E = 1;
#2 d =2'b0; #2 d =2'b01;
#2 d =2'b10; #2 d =2'b11;
#20; $finish;
end
endmodule

DECODER - 3x8

//behavioural
module decoder_3x8(y, E, d);
input [2:0] d;
input E;
output reg [7:0] y;
always@(d or E) begin
if(E==1) begin
case(d)
3'b000: y =8'b0000_0001;
3'b001: y =8'b0000_0010;
3'b010: y =8'b0000_0100;
3'b011: y =8'b0000_1000;
3'b100: y =8'b0001_0000;
3'b101: y =8'b0010_0000;
3'b110: y= 8'b0100_0000;
3'b111: y =8'b1000_0000;
default: $display("Invalid");
endcase
end
else begin
y = 0;
end
end
endmodule

data flow
module decoder_3x8(y, E, d);
input [2:0] d;
input E;
output [7:0] y;
assign y = E? 1<<d:0;
endmodule

//gate level
module decoder_3x8(y, E, d);
input [2:0] d;
input E;
output [7:0] y;
wire notd0, notd1, notd2;
not n0(notd0, d[0]);
not n1(notd1, d[1]);
not n2(notd2, d[2]);
and a0(y[0], notd0, notd1, notd2, E);
and a1(y[1], d[0], notd1, notd2, E);
and a2(y[2], notd0, d[1], notd2, E);
and a3(y[3], d[0], d[1], notd2, E);
and a4(y[4], notd0, notd1, d[2], E);
and a5(y[5], d[0], notd1, d[2], E);
 and a6(y[6], notd0, d[1], d[2], E);
and a7(y[7], d[0], d[1], d[2], E);
endmodule

//test bench
module decoder_3x8_tb();
reg [2:0] d;
reg E;
wire [7:0] y;

// Instantiate the Unit Under Test (UUT)

decoder_3x8 uut (
.y(y),
.E(E),
.d(d)
);

initial begin
// Initialize Inputs
d = 0;
E = 0;

// Wait 100 ns for global reset to finish

#100;

// Test Case 1: E = 0 (Decoder Disabled)

E = 0; d = 3'b000; #10;
E = 0; d = 3'b001; #10;
E = 0; d = 3'b010; #10;
E = 0; d = 3'b011; #10;
E = 0; d = 3'b100; #10;
E = 0; d = 3'b101; #10;
E = 0; d = 3'b110; #10;
E = 0; d = 3'b111; #10;

// Test Case 2: E = 1 (Decoder Enabled)

E = 1; d = 3'b000; #10;
E = 1; d = 3'b001; #10;
E = 1; d = 3'b010; #10;
E = 1; d = 3'b011; #10;
E = 1; d = 3'b100; #10;
E = 1; d = 3'b101; #10;
E = 1; d = 3'b110; #10;
E = 1; d = 3'b111; #10;

$display("Test complete");
$finish;
end
endmodule

SR FLIP FLOP

//data flow
module sr_ff(s,r,clk,q,qbar);
 input s;
input r;
input clk;
output q;
output qbar;
assign q = clk? (s + ((~r) & q)) : q;
assign qbar = ~q;
endmodule

//behavioural modelling
module sr_ff(s,r,clk,q,qbar);
input s;
input r;
input clk;
output reg q;
output reg qbar;
always @(posedge clk) begin
if (s == 1) begin
q <= 1;
qbar <= 0;
end
else if (r == 1) begin
q <= 0;
qbar <= 1;
end
end
endmodule

//gate level
module sr_ff(s,r,clk,q,qbar);
input s;
input r;
input clk;
output q;
output qbar;
wire nand1,nand2;
nand (nand1,clk,s);
nand (nand2,clk,r);
nand (q,nand1,qbar);
nand (qbar,nand2,q);
endmodule

//test bench
module sr_ff_tb();
reg s, r, clk;
wire q, qbar;

sr_ff uut (s, r, clk, q, qbar);

initial begin
clk = 0;
forever #10 clk = ~clk;
end

initial begin
s = 1; r = 0;
#100 s = 0; r = 1;
#100 s = 0; r = 0;
 #100 s = 1; r = 1;
#100 $finish;
end
endmodule

JK FLIP FLOP

//behavioural
module jk_ff (j, k, clk, q, qbar);
input clk, j, k;
output reg q, qbar;

always @(posedge clk) begin

if (k == 0 && j == 0) begin
q <= q;
qbar <= qbar;
end
else if (j == 1 && k == 0) begin
q <= 1;
qbar <= 0;
end
else if (j == 0 && k == 1) begin
q <= 0;
qbar <= 1;
end
else if (j == 1 && k == 1) begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule

//data flow
module jk_ff (j, k, clk, q, qbar);
input j;
input k;
input clk;
output reg q;
output reg qbar;

wire next_q;

assign next_q = (j & ~k) ? 1 :

(~j & k) ? 0 :
(j & k) ? ~q : q;

always @(posedge clk) begin

q <= next_q;
end
endmodule

//gate level
module jk_ff(j,k,clk,q,qbar);
input j;
input k;
input clk;
output q;
output qbar;
 wire nand1,nand2;
nand (nand1,j,clk);
nand (nand2,k,clk);
nand (q,qbar,nand1);
nand (qbar,q,nand2);
endmodule

//test bench
module jk_ff_tb();
reg j, k, clk;
wire q, qbar;

jk_ff uut (j, k, clk, q, qbar);

always #5 clk = ~clk;

initial begin
j = 0; k = 0; clk = 0;
#10 j = 1; k = 0;
#20 j = 0; k = 1;
#30 j = 1; k = 1;
#40 j = 0; k = 0;
#100 $finish;
end
endmodule

D FLIP FLOP

//data flow
module d_ff (d, clk, clear, q, qbar);
input d;
input clk;
input clear;
output reg q;
output reg qbar;
always @(posedge clk or posedge clear)
begin
if (clear)
q <= 1'b0;
else
q <= d;
qbar <= ~q; // Complementary output
end
endmodule

//behavioural modelling
module d_ff (d, clk, clear, q, qbar);
input d;
input clk;
input clear;
output reg q;
output reg qbar;

always @(posedge clk) begin

if (clear == 1) begin
q <= 0;
qbar <= 1;
 end else begin
q <= d;
qbar <= !d;
end
end
endmodule

//test bench
module d_ff_tb();
reg d,clk,clear;
wire q,qbar;
d_ff uut(d, clk, clear, q, qbar);
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
clear=1; d<=0;
#100; clear=0; d<= 1;
#100; d<= 0;
#100; d<= 1;
#100 $finish;
end
endmodule

T FLIP FLOP

//gate level
module t_ff(input t,input clk,input reset,output q,output qbar) ;
wire S,R;
and(R,qbar,t,clk);
and(S,q,t,clk);
SRLatch srt(S,R,q,qbar);
endmodule
module SRLatch(input S,input R, output q, output qbar);
nand(q,R,qbar);
nand(qbar,S,q);
endmodule

//DATA FLOW
module t_ff (t, clk, reset, q, qbar);
input t;
input clk;
input reset;
output q;
output qbar;
assign sbar= ~(t & clk & qbar & reset);
assign rbar= ~(t & clk & q);
assign q= ~(sbar & qbar);
assign qbar= ~(rbar & q & reset);
endmodule

//behavioural modelling
module t_ff (t, clk, reset, q, qbar);
input t;
input clk;
 input reset;
output reg q;
output reg qbar;

always @(posedge clk or posedge reset) begin

if (reset) begin
q <= 0;
qbar <= 1;
end else if (t) begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule

//test bench
module t_ff_tb();
reg t, clk, reset;
wire q, qbar;

t_ff uut (t, clk, reset, q, qbar);

initial begin
clk = 0;
forever #25 clk = ~clk;
end

initial begin
t = 1'b1;
reset = 1;
#10 reset = 0; t = 1'b0;
#100 t = 1'b1;
#100 t = 1'b1;
#100 t = 1'b0;
#100 reset = 1;
t = 1'b1;
#100 $finish;
end
endmodule

SHIFT REGISTER - SISO

module siso(clk,clear,si,so);
input clk;
input clear;
input si;
output reg so;
reg [3:0]tmp;
always @(posedge clk) begin
if (clear) begin
tmp <= 4'b0000;
end else begin
tmp <= {tmp[2:0], si}; // Shift left and insert si at the LSB
end
so <= tmp[3];
end
endmodule
//test bench
module siso_tb();
reg clk,clear,si;
wire so;
siso uut(clk,clear,si,so);
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
clk = 0;
clear = 0;
si = 0;
#100;

clear = 1; #10;
clear = 0; #10;
si = 1; #20; // Apply first bit and wait a clock period
si = 1; #20; // Apply second bit and wait a clock period
si = 1; #20; // Apply third bit and wait a clock period
si = 1; #20; // Apply fourth bit and wait a clock period
#100;
$finish;
end
endmodule

SHIFT REGISTERS - SIPO

module sipo(clk,si,q);
input clk;
input si;
output reg [3:0]q=0;
always@(posedge clk) begin
q[3]<=si;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

//test bench

module sipo_tb();
reg clk,si;
wire [3:0]q;
sipo uut(clk,si,q);

initial
begin
clk=0;
si=1;
#10;
si=0;
#10
si=0;
#10;
si=1;
end
always #5 clk=~clk;

endmodule

SHIFT REGISTERS - PISO

module piso(clk, mode, d, so);

input clk;
input mode;
input [3:0] d;
output so; // Only the least significant bit is output
reg [3:0] q = 0; // Register to hold the shift register values

always @(posedge clk) begin

if (mode)
q <= d; // Parallel load when mode is 1
else begin
q[3] <= q[2]; // Shift left
q[2] <= q[1];
q[1] <= q[0];
q[0] <= 1'b0; // Shift in 0 on the right end
end
end

assign so = q[0]; // Assign the least significant bit to the output

endmodule

//test bench
module piso_tb();
reg clk,mode;
reg [3:0]d;
wire so;
piso uut(clk,mode,d,so);
initial begin
clk=0;
d=4'b1001;
mode=1;
#10;
mode=0;
end
always #5 clk=~clk;
endmodule

SHIFT REGISTERS - PIPO

module pipo(clk,d,q);
input clk;
input [3:0]d;
output reg [3:0]q;
always@(posedge clk) begin
q[3]<=d[3];
q[2]<=d[2];
 q[1]<=d[1];
q[0]<=d[0];
end
endmodule

//test bench

module pipo_tb();
reg clk;
reg [3:0]d;
wire [3:0]q;
pipo uut(clk,d,q);
initial
begin
clk=0;
d=0;
#100;
d=4'b1001;
end
always #5 clk=~clk;
endmodule

SYNCHRONOUS COUNTER - UP

module up_syn(clk,rst,din,load,count);
input clk;
input rst;
input [3:0]din;
input load;
output reg [3:0]count;
always @(posedge clk)
begin
if (rst)
count <= 0;
else if (load)
count <= din;
else count<=count+1'd1;
end
endmodule

//test bench

module up_syn_tb();
reg clk,rst,load;
reg [3:0]din;
wire [3:0]count;
up_syn uut(clk,rst,din,load,count);
initial
begin
clk = 1'b0;
forever #5 clk = ~clk ;
end
initial
begin
{rst, load} = 0;
din =4'd0 ;
#10;
end
initial
begin
{rst ,load} =2'b10 ; din =4'd3;#10;
{rst ,load} =2'b01 ; din =4'd4;#10;
{rst ,load} =2'b00 ; din =4'd4;#10;
{rst ,load} =2'b00 ; din =4'd4;#10;
{rst ,load} =2'b00 ; din =4'd4;#10;
{rst ,load} =2'b11 ; din =4'd4;#10;
{rst ,load} =2'b00 ; din =4'd9;#10;
{rst ,load} =2'b10 ; din =4'd2;#10;
end
initial
begin
$monitor($time,"input din=%b output count=%b", din,count);
#120 $finish;
end
endmodule

SYNCHROUNOUS COUNTER - DOWN

module down_syn(clk,reset,q);
input clk;
input reset;
output [3:0]q;
reg [3:0]q=4'b1111;
always@(posedge clk) begin
if(reset)
q<=0;
else q<=q-1;
end
endmodule
//test bench
module down_syn_tb();
reg clk,reset;
wire [3:0]q;
down_syn uut(clk,reset,q);
initial
begin
clk <= 0 ;
end
initial
begin
reset <= 1;
#5 reset <= 0;
#50 reset <= 0;
#5 reset <=100;
end
always #5 clk <= ~clk;
initial
begin
$monitor ("q=%b, clk=%b, reset=%b",$time,q,clk,reset);
#120 $finish;
end
endmodule

SYNCHRONOUS COUNTER - UPDOWN

module updown1(clk,rst,load,din,updown,count);
input clk;
input rst;
input updown;
input load;
input [3:0]din;
output reg [3:0]count;
always @(posedge clk)
begin
if (rst)
count <= 0;
else if (load)
count<=din;
else if (updown)
count<=count+4'd1 ;
else
count<=count-4'd1;
end
endmodule

//test bench
module updown1_tb();
reg [3:0] din;
reg clk,rst, load,updown;
wire [3:0] count;
updown1 dut (clk,rst,load,din,updown,count);
initial
begin
clk =1'b0;
forever #5 clk = ~clk ;
end
initial
begin
{rst,load,updown} = 3'd0;
din =4'd0 ;
#10;
end
initial
begin
{rst,load,updown} = 3'b100; din =4'd3;#10;
{rst,load,updown} = 3'b010; din =4'd4;#10;
{rst,load,updown} = 3'b001; din =4'd0;#10;
{rst,load,updown} = 3'b001; din =4'd0;#10;
{rst,load,updown} = 3'b001; din =4'd0;#10;
{rst,load,updown} = 3'b001; din =4'd9;#10;
{rst,load,updown} = 3'b001; din =4'd9;#10;
{rst,load,updown} = 3'b001; din =4'd9;#10;
{rst,load,updown} = 3'b000; din =4'd9;#10;
{rst,load,updown} = 3'b000; din =4'd9;#10;
{rst,load,updown} = 3'b010; din =4'd1;
#150 $finish;
end
endmodule

ASYNCHRONOUS COUNTER - UP

module asyup(clk,rst,count);
input clk;
input rst;
output reg [3:0]count;
initial count=0;
always @(posedge clk)
begin
if(rst)
count=0;
else
count[0]=~count[0];
end

always @(posedge ~count[0])

begin
if(rst)
count=0;
else
count[1]=~count[1];
end

always @(posedge ~count[1])

begin
if(rst)
count=0;
else
count[2]=~count[2];
end

always @(posedge ~count[2])

begin
if(rst)
count=0;
else
count[3]=~count[3];
end
endmodule

//test bench

module asyup_tb();
reg clk;
reg rst;
wire [3:0] count;
asyup uut(clk,rst,count);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
#10 rst = 0;

#10;

repeat (16) begin

#20;

$display("Count: %d", count);

rst = 1;
#5 rst = 0;
end

#10 $finish;
end
endmodule

ASYNCHRONOUS COUNTER - DOWN

module asydown(clk,rst,count);
input clk;
input rst;
output reg [3:0]count;

initial count=0;

always @(posedge clk)

begin
if(rst)
count=0;
else
count[0]=~count[0];
end

always @(posedge count[0])

begin
if(rst)
count=0;
else
count[1]=~count[1];
end

always @(posedge count[1])

begin
if(rst)
count=0;
 else
count[2]=~count[2];
end

always @(posedge count[2])

begin
if(rst)
count=0;
else
count[3]=~count[3];
end
endmodule

//test bench

module asydown_tb();
reg clk;
reg rst;
wire [3:0] count;
asydown uut(clk,rst,count);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
#10 rst = 0;
#10;

repeat (16) begin

#20;

$display("Count: %d", count);

rst = 1;
#5 rst = 0;
end

#10 $finish;
end
endmodule

SEQUENCE DETECTOR-MEALY

module seq_mealy(clk,reset,x,z);
input clk;
input reset;
 input x;
output reg z;
parameter s0=0,s1=1,s2=2,s3=3;
reg [0:1] ps,ns;
always @(ps,x) begin
case(ps)
s0:begin
z=x?0:0;
ns=x?s0:s1;end
s1:begin
z=x?0:0;
ns=x?s2:s1;end
s2:begin
z=x?0:0;
ns=x?s3:s1;end
s3:begin
z=x?0:1;
ns=x?s0:s1;end
endcase
end
endmodule

//test bench

module seq_mealy_tb();
reg x, clk, reset;

wire z;
seq_mealy uut(clk,reset,x,z);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
x = 0;
reset = 1;
#10 reset = 1;

#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;

#10 $finish;
end
endmodule

SEQUENCE DETECTOR-MOORE

module seq_moore(clk,x,reset,z);
input x;
input clk;
input reset;
output reg z;
parameter S0=3'b000,S1=3'b001,S2=3'b011,S3=3'b010,S4=3'b110;
reg[0:2] cs,ns;
always @(posedge clk,posedge reset) begin
if (reset==1)
cs=S0;
else
cs=ns;
end
always @(cs,x) begin
case(cs)
S0:begin
if(x==1)
ns=S1;
else
ns=S0;
end
S1:begin
if(x==0)
ns=S2;
else
ns=S1;
end
S2:begin
if(x==0)
ns=S0;
else
ns=S3;
end
S3:begin
if(x==0)
ns=S2;
else
ns=S4;
end
S4:begin
if(x==0)
ns=S2;
else
ns=S1;
end
default:ns=S0;
endcase
end

always @(cs) begin

case(cs)
S0:z=0;S1:z=0;
S2:z=0;S3:z=0;
S4:z=1;
endcase
end
endmodule

//test bench
module seq_moore_tb();
reg x, clk, reset;
wire z;
seq_moore uut(clk,x,reset,z);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
x = 0;
reset = 1;
#30 reset = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 $finish;
end
endmodule

SERIAL ADDER-MEALY

module ser_add_mealy(a,b,cin,clk,reset,sum,ns);

input a;
input b;
input cin;
input clk;
input reset;
output reg sum,ns;
reg [1:0] cst;
parameter s0 = 2'b00, s1 = 2'b01;
initial begin
cst = 2'b00;end

always @(posedge clk or posedge reset) begin

if (reset)
cst <= s0;
else
cst <= ns;
end
always @(posedge clk) begin
case(cst)
s0: begin
sum = a ^ b;
if (a & b)
ns = s1;
else
ns = s0;
end
s1: begin
sum = a ^ b;
if (a & b)
ns = s0;
else
ns = s1;
end
default: ns = s0;
endcase
end
endmodule

//test bench

module ser_add_mealy_tb();
reg a, b, cin, clk, reset;
wire sum, ns;

ser_add_mealy uut(a,b,cin,clk,reset,sum,ns);
initial begin

a = 0;
b = 0;
cin = 0;
clk = 0;
reset = 1;

#5 reset = 0;

#10 a = 0; b = 0; cin = 0;
#10

#10 a = 1; b = 0; cin = 0;
#10

#10 a = 1; b = 1; cin = 0;
#10

#10 a = 0; b = 1; cin = 0;
#10

#10 a = 1; b = 0; cin = 1;
#10

#10 a = 1; b = 1; cin = 1;
#10

#10 a = 0; b = 1; cin = 1;
#10
 #10 $finish;
end
always #5 clk = ~clk;
endmodule

SERIAL ADDER-MOORE
module ser_add_moore(x,y,clk,reset,cout,sum);
input x;
input y;
input clk;
input reset;
output reg cout;
output reg sum;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
reg [1:0] state_reg, next_state;
always @(*) begin
case(state_reg)
S0: begin
sum = 1'b0;
cout = 1'b0;
end
S1: begin
sum = x ^ y;
cout = x & y;
end
S2: begin
sum = x ^ y ^ cout;
cout = (x & y) | (x & cout) | (y & cout);
end
default: begin
sum = 1'b0;
cout = 1'b0;
end
endcase
end

always @(posedge clk, posedge reset) begin

if (reset) begin
state_reg <= S0;end
else begin
state_reg <= next_state;end
end

always @(state_reg, x, y) begin

case(state_reg)
S0: begin
next_state = S1;
end
S1: begin
next_state = S2;
end
S2: begin
next_state = S0;
end
default: begin
next_state = S0;
end
 endcase
end
endmodule

//test bench
module ser_add_moore_tb();
reg x,y,clk,reset;
wire sum,cout;
ser_add_moore uut(x,y,clk,reset,cout,sum);
initial begin
clk=0;end
initial begin
reset=1; #10 reset=0; end
always #5 clk=~clk;
initial begin
#20 x=0;y=0;
#40 x=1;y=1;
#60 x=0;y=0;
#80 x=1;y=1;
#100 x=1;y=0;
#120 x=0;y=1;
#140 $finish;
end
endmodule

EVEN PARITY DETECTOR

module even_parity_detec(input wire [7:0] data_in,output reg parity_error);

integer i;
reg parity_bit;

always @* begin
parity_bit = ^data_in;end

always @* begin
parity_error = (parity_bit == 1'b1) ? 1'b0 : 1'b1;end

endmodule

//test bench

module even_parity_tb();
parameter DATA_WIDTH = 8;
reg [DATA_WIDTH-1:0] data_in;
wire parity_error;
even_parity_detec uut(data_in,parity_error);

initial begin
data_in = 8'b10101010;
#10 data_in = 8'b10101011;
#10 data_in = 8'b11110000;
#10 data_in = 8'b11110001;
#10 $finish;
end
endmodule
ODD PARITY DETECTOR

module odd_par_detector(data_in,parity_error);
input wire [7:0] data_in;
output reg parity_error;
integer i;
reg parity_bit;

always @* begin
parity_bit = ^data_in;
end

always @* begin
parity_error = (parity_bit == 1'b1) ? 1'b1 : 1'b0;
end
endmodule

//test bench

module odd_par_dete_tb();

parameter DATA_WIDTH = 8;
reg [DATA_WIDTH-1:0] data_in;
wire parity_error;
odd_par_detector uut(data_in,parity_error);

initial begin
data_in = 8'b10101010;
#10 data_in = 8'b10101011;
#10 data_in = 8'b11110000;
#10 data_in = 8'b11110001;
#10 $finish;
end
endmodule