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Simple Processor Notes

The document provides an overview of a simple processor with four n-bit registers and control signals for loading, moving, and performing arithmetic operations. Load and move operations take 1 clock cycle, while addition and subtraction require 3 clock cycles due to multiple steps involved. It also includes details on control signals, timing, and Verilog code for processor design and testing.

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Simple Processor Notes

The document provides an overview of a simple processor with four n-bit registers and control signals for loading, moving, and performing arithmetic operations. Load and move operations take 1 clock cycle, while addition and subtraction require 3 clock cycles due to multiple steps involved. It also includes details on control signals, timing, and Verilog code for processor design and testing.

Uploaded by

mamahlo543
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Simple Processor Overview

- The processor has four n-bit registers: R0, R1, R2, and R3.

- External data can be loaded into the processor through a control signal called Extern.

- The AddSub control signal determines the arithmetic operation:

- AddSub = 0: perform addition (A + B)

- AddSub = 1: perform subtraction (A - B)

- Registers A and G are used during computation, controlled by signals:

- Ain, Gin, and Gout

Operations and Timing

Load Operation

- Format: Rx <- Data

- Data is loaded into register Rx through the bus.

- Completed in 1 clock cycle.

Move Operation

- Transfers data between two registers.

- Also completed in 1 clock cycle.

Add/Subtract Operation

Takes 3 clock cycles:

1. T1: Transfer Rx to bus and store in register A.

2. T2: Transfer Ry to bus, and perform Add/Sub. Store result in register G.

3. T3: Transfer result from G to the destination register.


Q: Why Load/Move take 1 cycle but Add/Sub need 3?

- Load/Move are direct transfers.

- Add/Sub involve multiple steps: data move, calculation, and result storage.

Control Signals and Functions

- Function Selector (f1 f0):

- 00: Load

- 01: Move

- 10: Add

- 11: Subtract

- W = 1: Operation active

- Done = 1: Operation complete

- Frin = 1: Function input given

Timing Control (T0-T3)

- Operations progress through time steps T0 to T3.

- At T0, no action happens.

- At T1-T3, different parts of operations occur.

- Clear signal: Resets the timing when W = 0.

Register Control via X and Y Signals

- Rin = X: Load into registers using X0 to X3

- Rin = Y: Load using Y0 to Y3


- Rout = X or Y: Similarly determines which register outputs to the bus

Important Equations

- Extern = I0 * T1

- Done = (I0 + I1) * T1 + (I2 + I3) * T3

- Ain = (I2 + I3) * T1

- Gin = 1 at T2, Gout = 1 at T3

These control signals help build the control logic for operations.

Processor Coding

- Verilog Code for processor design is included.

- Testbench verifies functionality.

- Mistake to avoid: Not resetting the processor initially.

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