UNIT – IV

SPECIAL ICs

Functional block – characteristics of 555 Timer and its PWM application - IC – 566
voltage controlled oscillator IC – 565 phase lock loop IC – AD 633 Analog multiplier ICs.
Part – B – 16Mark Questions

4.1 FUNCTIONAL BLOCK

1. Sketch the functional block diagram of IC555 and explain their working principle.
[May/June 2012][April/May 2017][Nov/Dec 2015] (8)
(or)
Explain the functional block diagram of NE 561 phase locked loop. (May-2018) (7)
(or)
Explain the functional block and characteristics of IC 555 timer with its PWM application.
[Apr/May 2019] 13 marks
(or)
Demonstrate with neat functional diagram, the working of 555 IC timer. Develop the
expression for pulse with of rectangular output pulse. Nov/Dec 2019 (13 marks)
4.1.1 Introduction:
 The 555 timer is a highly stable device for generating accurate time delay or oscillation.
 Signeta Corporation first introduced this device as the SE555/NE555.
 It is available in two package styles, 8 – pin circular style, TO – 99 can or 8 – pin mini DIP
or as 14 –pin DIP.
 The 556 timer contains two 555 timers and is a 14 – pin DIP.
 There is also available counter timer such as Exar’s XR – 2240 which contains a 555 timer
plus a programmable binary counter in a single 16 – pin package.
 A single 555 timer can provide time delay ranging from microseconds to hours whereas
counter timer can have a maximum timing range of days.

Figure 1: Pin Diagram

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 The 555 timer can be used with supply voltage in the range of + 5V to +18V and can drive
load till 200 mA.
 It is compatible with both TTL and CMOS logic circuits.
 Because of the wide range of supply voltage, the 555 timer is versatile and easy to use in
various applications.
 Various applications include oscillator, pulse generator, ramp and square wave generator
mono-shot multivibrator, burglar alarm, traffic light control and voltage monitor etc.

4.1.2 DESCRIPTION OR FUNCTIONAL DIAGRAM:

 Fig. 1 gives the pin diagram and Fig. 2 gives the functional diagram for 555 IC timers.
 Referring to Fig.2, three 5 kΩ internal resistors act as voltage divider, providing bias voltage
of (2/3) VCC to the upper comparator (UC) and (1/3) VCC to the lower comparator (LC),
where VCC is the supply voltage.
 Since these two voltages fix the necessary comparator threshold voltage, they also aid in
determining the timing interval.
 It is possible to vary time electronically too, by applying a modulation voltage to the control
voltage input terminal (pin 5).
 In applications where no such modulation as intended it is recommended by manufacturers
that a capacitor (0.01 MF) be connected between control voltage terminal (pin 5) and ground
to by-pass noise or ripple from the supply.

Figure 2: Functional diagram of 555 timers

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 In the standby (stable) state, the output 𝑄̅ of the centrol flip-flop (FF) is HIGH. This makes
the output LOW because of power amplifier which is basically an inverter.
 A negative going trigger pulse is applied to pin 2 and should have its dc level greater than the
threshold level of the lower comparator (i.e. VCC/3).
 At the negative going edge of the trigger as the trigger passes through (VCC/3), the output of
the lower comparator goes HIGH and sets the FF (Q = 1, 𝑄̅= 0).
 During the positive excursion when the threshold voltage at pin 6 passes through (2/3) VCC,
the output of the upper comparator goes HIGH and resets the FF (Q = 0, 𝑄̅= 1).
 The reset input (pin 4) provides a mechanism to reset the FF in a manner which overrides the
effect of any instruction coming to FF from lower comparator.
 This overriding reset is effective when the reset input is less than about 0.4 V. When this
reset is not used, it is returned to VCC.
 The transistor Q2 serves as a buffer to isolate the reset input from the FF and transistor Q 1.
 The transistor Q2 is driven by an internal reference voltage Vref obtained from supply voltage
VCC.

4.2 CHARACTERISTICS OF 555 TIMER AND ITS PWM APPLICATION

4.2.1 MONOSTABLE OPERATION

2. With neat diagrams, explain the working of IC555 in mono stable mode. (8)

 Figure 3 shows a 555 timer connected for monostable operation and its functional diagram is
shown in Fig. 4.
 In the standby state, FF holds transistor Q1ON, thus clamping the external timing capacitor C
to ground.
 The output remains at ground potential, i.e. LOW. As the trigger passes through V CC/3, the
FF is set, i.e. 𝑄̅= 0.
 This makes the transistor Q1OFF and the short circuit across the timing capacitor C is
released.
 As 𝑄̅is LOW, output goes HIGH (= VCC). The timing cycle now begins.
 Since C is unclamped, voltage across it rises exponentially through R towards VCC with a
time constant RC as in Fig. 5(b).
 After a time period T, the capacitor voltage is just greater than (2/3) VCC and the upper
comparator resets the FF, that is, R = 1, S = 0 (assuming very small trigger pulse width).
 This makes 𝑄̅= 1, transistor Q1 goes ON (i.e. saturates), thereby, discharging the capacitor C
rapidly to ground potential.
 The output returns to the standby state or ground potential as shown in Fig. 5(c).

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 Figure 3: Monostable multivibrator

Figure 4: Timer in monostable operation with functional diagram

 The voltage across the capacitor as in Fig. 5(b) is given by

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 𝑉𝑐 = 𝑉𝐶𝐶 (1 − 𝑒 −𝑡 ⁄𝑅𝐶 ) (1)
At t = T, vc = (2/3) VCC
2
∴ 𝑉 = 𝑉𝐶𝐶 (1 − 𝑒 −𝑡⁄𝑅𝐶 )
3 𝐶𝐶
or, T = RC ln (1/3)
or, T = 1.1 RC (sec) (2)
 It is evident from Eq. (2) that the timing interval is independent of the supply voltage.
 It may also be noted that once triggered, the output remains in the HIGH state until time T
elapses, which depends only upon R and C.
 Any additional trigger pulse coming during this time will not change the output state.
 However, if a negative going reset pulse as in Fig. 5(d) is applied to the reset terminal (pin –
4) during the timing cycle, transistor Q2 goes OFF, Q1 becomes ON and the external timing
capacitor C is immediately discharged.
 The output now will be as in Fig. 5(e). It may be seen that the output of Q2 is connected
directly to the input of Q1 so as to turn ON Q1 immediately and thereby avoid the
propagation delay through the FF.
 Now, even if the reset is released, the output will still remain LOW until a negative going
trigger pulse is again applied at pin 2.

Figure 5: Timing pulses

 Fig. 6 shows a graph of the various combinations of R and C necessary to produce a given
time delay.

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 Figure 6: Graph of RC combinations for different time delays

 Sometimes the monostable circuit of Fig.3 mis-triggers on positive pulse edges, even with
the control pin bypass capacitor.
 To prevent this, a modified circuit as shown in Fig.7 is used.
 Here the resistor and capacitor combination of 10 kΩ and 0.001 µF at the input forms a
differentiator.
 During the positive going edge of the trigger, diode D becomes forward biased, thereby
limiting the amplitude of the positive spike to 0.7V.

Figure 7: Modified monostable circuit

4.2.2 Applications In Monostable Mode

3. Discuss in detail the applications of Monostable Mode?

4.2.2.1 Missing Pulse Detector

 Missing pulse detector circuit using 555 timer is shown in Fig. 8. Whenever, input trigger is
low, the emitter diode of the transistor Q is forward biased.
 The capacitor C gets clamped to few tenths of a volt (~ 0.7V). The output of the timer goes
HIGH.

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 The circuit is designed so that the time period of the monostable circuit is slightly greater
(1/3 longer) than that of the triggering pulses.
 As long as the trigger pulse train keeps coming at pin 2, the output remains HIGH.
 However, if a pulse misses, the trigger input is high and transistor Q is cut off. The 555 timer
enters into normal state of monostable operation.
 The output goes LOW after time T of the mono-shot. Thus this type of circuit can be used to
detect missing heartbeat.
 It can also be used for speed control and measurement. If input trigger pulses are generated
from a rotating wheel, the circuit tells when the wheel speed drops below a predetermined
value.

Figure 8: A missing pulse detector monostable circuit

Figure 9: Output of missing pulse detector

4.2.2.2 Linear Ramp Generator

 Linear ramp can be generated by the circuit shown in Fig. 10. The resistor R of the
monostable circuit is replaced by a constant current source.
 The capacitor is charged linearly by the constant current source formed by the transistor Q3.
 The capacitor voltage vC can be written as,

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 1 𝑡
𝑣𝐶 = ∫ 𝑖 𝑑𝑡 (3)
𝐶 0
 Where, iis the current supplied by the constant current source. Further, the KVL equation can
be written as,
𝑅1
𝑉 − 𝑉𝐵𝐸 = (𝛽 + 1)𝐼𝐵 𝑅𝐸 ≈ 𝛽𝐼𝐵 𝑅𝐸 = 𝐼𝐶 𝑅𝐸 = 𝑖𝑅𝐸  (4)
𝑅1 + 𝑅2 𝐶𝐶
 Where, IB, IC are the base current and collector current respectively, β is the current
amplification factor in CE mode and is very high.
Therefore,
𝑅1 𝑉𝐶𝐶 − 𝑉𝐵𝐸 (𝑅1 + 𝑅2 )
𝑖=  (5)
𝑅𝐸 (𝑅1 + 𝑅2 )

Figure 10: Linear ramp generator

 Now putting the value of the current i in equation (3), we get,

𝑅1 𝑉𝐶𝐶 − 𝑉𝐵𝐸 (𝑅1 + 𝑅2 )
𝑣𝐶 = × 𝑡 (6)
𝐶𝑅𝐸 (𝑅1 + 𝑅2 )
 At time t = T, the capacitor voltage vc becomes (2/3) VCC. Then we get,
2 𝑅1 𝑉𝐶𝐶 − 𝑉𝐵𝐸 (𝑅1 + 𝑅2 )
𝑉𝐶𝐶 = × 𝑇 (7)
3 𝐶𝑅𝐸 (𝑅1 + 𝑅2 )
 This gives the time period of the linear ramp generator as,
(2⁄3)𝑉𝐶𝐶 𝑅𝐸 (𝑅1 + 𝑅2 )𝐶
𝑇=  (8)
𝑅1 𝑉𝐶𝐶 − 𝑉𝐵𝐸 (𝑅1 + 𝑅2 )
 The capacitor discharges as soon as its voltage reaches (2/3) V CC which is the threshold of
the upper comparator in the monostable circuit functional diagram.

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 The capacitor voltage remains zero till another trigger is applied. The various waveforms are
shown in Fig. 11.
 The practical values can be noted as
R1 = 47 kΩ R2 = 100 kΩ
RE = 2.7 kΩ C = 0.1 µF
VCC = 5 V (any value between 5 to 18 V can be chosen)

Figure 11: Linear Ramp generator output

4.2.2.3 Frequency Divider:

 A continuously triggered monostable circuit when triggered by a square wave generator can
be used as a frequency divider, if the timing interval is adjusted to be longer than the period
of the triggering square wave input signal.
 The monostable multivibrator will be triggered by the first negative going edge of the square
wave input but the output will remain HIGH (because of greater timing interval) for next
negative going edge of the input square wave as shown in Fig. 12.
 The mono-shot will however be triggered on the third negative going input, depending on the
choice of the time delay.
 In this way, the outputs can be made integral fractions of the frequency of the input
triggering square wave.

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 Figure 12: Frequency divider waveform

4.2.2.4 Pulse Width Modulation:

 The circuit is shown in Fig. 13. This is basically a monostable multivibrator with a
modulating input signal applied at pin – 5.
 By the application of continuous trigger at pin – 2, a series of output pulses are obtained, the
duration of which depends on the modulating input at pin – 5.
 The modulating signal applied at pin – 5 gets superimposed upon the already existing voltage
(2/3) VCC at the inverting input terminal of UC.
 This in turn changes the threshold level of UC and the output pulse width modulation takes
place.
 The modulating signal and the output waveform are shown in Fig. 14.It may be noted from
the output waveform that the pulse duration, that is, the duty cycle only varies, keeping the
frequency same as that of the continuous input pulse train trigger.

Figure 13: Pulse width modulator

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 Figure 14: Pulse width modulator waveforms

4.2.3 ASTABLE OPERATION

4. With neat diagrams, explain the working of IC555 in Astable mode. (8) [May/June
2011] [April/May 2015]

 The device is connected for an Astable operation as shown in Fig. 15. For better
understanding, the complete diagram of an Astable multivibrator with detailed internal
diagram of 555 is shown in Fig. 16.
 Comparing with monostable operation, the timing resistor is now split into two sections RA
and RB.
 Pin 7 of discharging transistor Q1 is connected to the junction of RA and RB. When the power
supply VCC is connected, the external timing capacitor C charges towards VCC with a time
constant (RA + RB)C.
 During this time, output (pin 3) is high (equals VCC) as Reset R = 0, Set S = 1 and this
combination makes 𝑄̅ = 0 which has unclamped the timing capacitor C.

Figure 15: Astable multivibrator using 555 timer

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 Figure 16: Functional diagram of astable multivibrator using 555 timer

 When the capacitor voltage equals (2/3) VCC the upper comparator triggers the control flip-
flop so that 𝑄̅= 1.
 This, in turn, makes transistor Q1 ON and capacitor C starts discharging towards ground
through RB and transistor Q1 with a time constant RBC (neglecting the forward resistance of
Q1).
 Current also flows into transistor Q1 through RA.
 Resistors RA and RB must be large enough to limit this current and prevent damage to the
discharge transistor Q1.
 The minimum value of RA is approximately equal to VCC/0.2 where 0.2 A is the maximum
current through the ON transistor Q1.
 During the discharge of the timing capacitor C, as it reaches V CC/3, the lower comparator is
triggered and at this stage S = 1, R = 0, which turns 𝑄̅ = 0.
 Now 𝑄̅= 0 unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between (2/3) VCC and (1/3) VCC respectively.
 Fig. 17 shows the timing sequence and capacitor voltage wave form.
 The length of time that the output remains HIGH is the time for the capacitor to charge from
(1/3) VCC to (2/3) VCC.
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 It may be calculated as follows:

Figure 17: Timing sequence of Astable multivibrator

 The capacitor voltage for a low pass RC circuit subjected to a step input of VCC is given by,
𝑣𝐶 = 𝑉𝐶𝐶 (1 − 𝑒 −𝑡⁄𝑅𝐶 )
 The time taken by the circuit to charge from 0 to (2/3) V CC is,
2
𝑉 = 𝑉𝐶𝐶 (1 − 𝑒 −𝑡1 ⁄𝑅𝐶 ) (9)
3 𝐶𝐶
or, t1 = 1.09 RC
and the time t2 to charge from 0 to (1/3) VCC is,
1
𝑉 = 𝑉𝐶𝐶 (1 − 𝑒 −𝑡2 ⁄𝑅𝐶 ) (10)
3 𝐶𝐶
or, t2 = 0.405 RC
 So the time to charge from (1/3) VCC to (2/3) VCC is,
tHIGH = t1 – t2
tHIGH = 1.09 RC – 0.405 RC = 0.69RC
 So, for the given circuit,
tHIGH = 0.69 (RA + RB) C  (11)
 The output is low while the capacitor discharges from (2/3) VCC to (1/3) VCC and the voltage
across the capacitor is given by,
1 2
𝑉𝐶𝐶 = 𝑉𝐶𝐶 (1 − 𝑒 −𝑡 ⁄𝑅𝐶 )
3 3
Solving, we get t = 0.69 RC
 So, for the given circuit,
tLOW = 0.69 RC (12)
 Here, both RA and RB are in the charge path, but only RB is in the discharge path. Therefore,
the total time is given by,
T = tHIGH + tLOW
or T = 0.69 (RA + 2RB) C
So,
1 1.45
𝑓= =  (13)
𝑇 (𝑅𝐴 + 2𝑅𝐵 )𝐶

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 Fig. 18 shows a graph of the various combinations of (RA + 2RB) and C necessary to produce
a given stable output frequency.
 The duty cycle D of a circuit is defined as the ratio of ON time to the total time period T =
(tON + tOFF).

Figure 18: Frequency dependence of RA, RB and C

 In this circuit, when the transistor Q1 is ON, the output goes low. Hence,
𝑡𝐿𝑂𝑊
%𝐷 = × 100
𝑇
𝑅𝐵
% 𝐷 = 𝑅 +2𝑅 × 100  (14)
𝐴 𝐵

 With the circuit configuration of Fig. 15, it is not possible to have a duty cycle more than
50% since tHIGH = 0.69 (RA + RB) C will always be greater than t LOW=0.69RBC.
 In order to obtain a symmetrical square wave i.e. D = 50%, the resistance R A must be
reduced to zero.
 However, now pin 7 is connected directly to VCC and extra current will flow through Q1
when it is on.
 This may damage Q1 and hence the timer.
 An alternative circuit which will allow duty cycle to be set at practically any level is shown
in Fig. 19.
 During the charging portion of the cycle, diode D1 is forward biased effectively short
circuiting RB so that,
tHIGH = 0.69 RAC

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 Figure 19: Adjustable duty cycle rectangular wave generator

 However, during the discharging portion of the cycle, transistor Q 1 becomes ON, thereby
grounding pin 7 and hence the diode D1 is reverse biased.
So, tLOW = 0.69 RBC  (15)
T = tHIGH + tLOW = 0.69 (RA + RB) C  (16)
Or,
1 1.45
𝑓= =  (17)
𝑇 (𝑅𝐴 + 𝑅𝐵 )𝐶
And Duty Cycle is,
𝑅𝐵
𝐷=
𝑅𝐴 + 𝑅𝐵
 Resistors RA and RB could be made variable to allow adjustment of frequency and pulse
width.
 However, a series resistor of 100 Ω (fixed) should be added to each RA and RB. This will
limit peak current to the discharge transistor Q1 when the variable resistors are at minimum
value.
 And, if RA is made equal to RB, then 50% duty cycle is achieved.
 Symmetrical square wave generator by adding a clocked JK flip-flop to the output of the
non-symmetrical square wave generator is shown in Fig. 20.
 The clocked flip-flop acts as binary divider to the timer output. The output frequency in this
case will be one half that of the timer.
 The advantage of this circuit is of having output of 50% duty cycle without any restriction on
the choice of RA and RB.

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 Figure 20: Symmetrical waveform generator
5. Design an astable multivibrator that can produce an output with T on= Toff= 1msec. The
OP-AMP is driven with a +15 and -15 V supply. Draw the waveforms across capacitors,
feedback and output. The hysteresis should not exceed 0.1V. Nov/Dec 2019.
Given Data:
Ton= Toff = 1msec
C= 0.01 µF
T= Ton + Toff
T= 2 msec
D= Ton/ (Ton + Toff)
= (1msec/ 2 msec) = 0.5
RA= (4/3)RB
The period of oscillation T= 0.693(RA + 2RB) x C1
T= 0.693 x (10/3 RB) x 10-8
RB= 2ms x (3/10) x (1/ 0.693 x 10-8)
RB= 86.5 KΩ
RA= (4/3) x RB
= 115 KΩ

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 4.2.4 Applications in an Astable Mode:
6. Discuss some of the applications of Astable mode in detail?

4.2.4.1 FSK Generator

 In digital data communication, binary code is transmitted by shifting a carrier frequency
between two pre-set frequencies.
 This type of transmission is called frequency shift keying (FSK) technique.
 A 555 timer in an Astable mode can be used to generate FSK signal.
 The circuit is as shown in Fig. 21. The standard digital data input frequency is 150 Hz.
 When input is HIGH, transistor Q is off and 555 timer works in the normal Astable mode of
operation.
 The frequency of the output waveform given by equation (1) can be rewritten as,
1.45
𝑓0 =  (18)
(𝑅𝐴 + 2𝑅𝐵 )𝐶
 In a tele-typewriter using a modulator-demodulator (MODEM), a frequency between 1070
Hz to 1270 Hz is used as one of the standard FSK signals.
 The components RA and RB and the capacitor C can be selected so that f0 is 1070 Hz.

Figure 21 FSK generator

 When the input is LOW, Q goes on and connects the resistance RC across RA. The output
frequency is now given by,
1.45
𝑓0 =  (19)
(𝑅𝐴 ║𝑅𝐶 ) + 2𝑅𝐵
 The resistance RC can be adjusted to get an output frequency of 1270 Hz.

4.2.4.2 Pulse Position Modulator

 The pulse position modulator can be constructed by applying a modulating signal to pin 5 of
555 timer connected for an Astable operation as shown in Fig. 22.

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 Figure 22: Pulse position modulator

Figure 23: Pulse position modulator output

 The output pulse position varies with the modulating signal, since the threshold voltage and
hence the time delay is varied.
 Fig. 23 shows the output waveform generated for a triangle wave modulation signal.
 It may be noted from the output waveform that the frequency is varying leading to pulse
position modulation.
 The typical practical component values may be noted as,
RA=3.9kΩ RB=3kΩ C= 0.01 µF
VCC = 5V (any value between 5V to 18V may be chosen)

4.2.4.3 Schmitt Trigger

5 Write short notes on Schmitt Trigger.
 The use of a 555 timer as a Schmitt Trigger is shown in Fig. 24.
 Here the two internal comparators are tied together and externally biased at V CC/2 through R1
and R2.

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 Since the upper comparator will trip at (2/3) VCC and lower comparator at (1/3) VCC, the bias
provided byR1 and R2 is centered within these two thresholds.

Figure 24: Timer in Schmitt trigger operation

 Thus, a sine wave of sufficient amplitude (> VCC/6= 2/3 VCC – VCC/2) to exceed the reference
levels causes the internal flip-flop to alternately set and reset, providing a square wave output
as shown in Fig. 25.

Figure 25: Input Output waveforms of Schmitt Trigger

 It may be noted that unlike conventional multivibrator, no frequency division is taking place
and frequency of square wave remains the same as that of input signal.

4.3 566 VOLTAGE CONTROLLED OSCILLATOR IC

5 Give the block diagram of IC 566 VCO and explain its operation.[Nov/Dec
2012][April/May 2011][Nov/Dec 2010][Nov/Dec 2016].
(or)
6 Discuss the ICC 566 as a voltage controlled oscillator with necessary illustrations.
[Apr/May 2019].

4.3.1 Voltage Controlled Oscillator (VCO):

 A common type of VCO available in IC form is Signetics NE/SE566.The pin configuration
and basic block diagram of 566 VCO are shown in Fig. 26 (a, b).
 Referring to Fig. 26 (b), a timing capacitor C, is linearly charged or discharged by a constant
current source/sink.

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 The amount of current can be controlled by changing the voltage vC applied at the
modulating input (pin 5) or by changing the timing resistor RT external to IC chip.
 The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the modulating voltage at
pin 5 is increased, the voltage at pin 6 also increases, resulting in less voltage across RT and
thereby decreasing the charging current.
 The voltage across the capacitor CT is applied to the inverting input terminal of Schmitt
trigger A2 via buffer amplifier A1.
 The output voltage swing of the Schmitt trigger is designed to VCC and 0.5 VCC.
 If Ra =Rb in the positive feedback loop, the voltage at the non-inverting input terminal of A2
swings from 0.5 VCC to 0.25 VCC.
 In Fig. 26 (c), when the voltage on the capacitor CT exceeds 0.5 VCC during charging, the
output of the Schmitt trigger goes LOW (0.5 VCC).
 The capacitor now discharges and when it is at 0.25 V CC, the output of Schmitt trigger goes
HIGH (VCC).

Figure 26 (a) Pin configuration

Figure 26(b): Block diagram

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 Since the source and sink currents are equal, capacitor charges and discharges for the same
amount of time.
 This gives a triangular voltage waveform across CT which is also available at pin 4.
 The square wave output of the Schmitt trigger is inverted by inverter A3 and is available at
pin 3.
 The output waveforms are shown in Fig. 26 (c). The output frequency of the VCO can be
calculated as follows:
 The total voltage on the capacitor changes from 0.25 VCC to 0.5 VCC. Thus ∆v = 0.25 VCC.
The capacitor charges with a constant current source.
So,
∆𝑣 𝑖
=
∆𝑡 𝐶𝑇
Or,
0.25𝑉𝐶𝐶 𝑖
=
∆𝑡 𝐶𝑇
Or,
0.25𝑉𝐶𝐶 𝐶𝑇
∆𝑡 = →1
𝑖
 The time period T of the triangular waveform = 2∆t. The frequency of oscillator f0 is,
1 1 𝑖
𝑓0 = = =
𝑇 2∆𝑡 0.5𝑉𝐶𝐶 𝐶𝑇
But,
𝑉𝐶𝐶 − 𝑣𝐶
𝑖= →2
𝑅𝑇
Where, vC is the voltage at pin 5. Therefore,
2(𝑉𝐶𝐶 − 𝑣𝐶 )
𝑓0 = →3
𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇

Figure 26(c): Output waveform (d): Typical connection diagram

21
 The output frequency of the VCO can be changed either by (i) RT, (ii) CT, or (iii) the voltage
vC at the modulating input terminal pin 5.
 The voltage vC can be varied by connecting a R1R2 circuit as shown in Fig.26 (d).
 The components RT and CT are first selected so that VCO output frequency lies in the centre
of the operating frequency range.
 Now the modulating input voltage is usually varied from 0.75 V CC to VCC which can produce
a frequency variation of about 10 to 1.
 With no modulating input signal, if the voltage at pin 5 is biased at (7/8) VCC, Eq. (9 10)
gives the VCO output frequency as,

2(𝑉𝐶𝐶 − (7⁄8)𝑉𝐶𝐶 ) 1 0.25

𝑓0 = = = →4
𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇 4𝐶𝑇 𝑅𝑇 𝐶𝑇 𝑅𝑇

4.3.2 Voltage to Frequency Conversion Factor:

 A parameter of importance for VCO is voltage to frequency conversion factor Kv and is
defined as,
∆𝑓0
𝐾𝑣 =
∆𝑣𝐶
 Here ∆vC is the modulation voltage required to produce the frequency shift ∆f0for a VCO.
 If we assume that the original frequency is f0 and the new frequency is f1 then,
2(𝑉𝐶𝐶 − 𝑣𝐶 + ∆𝑣𝐶 ) 2(𝑉𝐶𝐶 − 𝑣𝐶 )
∆𝑓0 = 𝑓1 − 𝑓0 = −
𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇 𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇
2∆𝑣𝐶
∆𝑓0 = →5
𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇
Or,
∆𝑓0 𝑉𝐶𝐶 𝐶𝑇 𝑅𝑇
∆𝑣𝐶 = →6
2
Putting the value of CTRT from equation ()
∆𝑣𝐶 = ∆𝑓0 𝑉𝐶𝐶 ⁄8𝑓0 → 7
Or,
∆𝑓0 8𝑓0
𝐾𝑣 = = →8
∆𝑣𝐶 𝑉𝐶𝐶

22
 4.4 565- PHASE LOCKED LOOP IC

7 Explain the principle and operation of a PLL. [Nov/Dec 2013]

(or)
Explain the working of IC 565. [Nov/Dec 2013][April/May 2010][April/May
2011][April/May 2017][Nov/Dec 2015]
(or)
Explain with neat diagram, the working of a phase locked loop. Nov/Dec 2019.

4.4.1 MONOLITHIC PHASE-LOCKED LOOP:

 All the different building blocks of PLL are available as independent IC packages and can be
externally interconnected to make a PLL.
 However, a number of manufacturers have introduced monolithic PLLs too.
 Some of the important monolithic PLLs are SE/NE560 series introduced by Signetics and
LM560 series by National Semiconductor.
 The SE/NE 560, 561, 562, 564, 565 and 567 mainly differ in operating frequency range,
power supply requirement, frequency and bandwidth adjustment ranges.
 Since 565 is the most commonly used PLL, we will discuss some of the important features of
this IC chip.
4.4.2 IC PLL 565:
 565 are available as a 14-pin DIP package and as 10-pin metal can package. The pin
configuration and the block diagram are shown in Fig. 27 (a, b).
 The output frequency of the VCO (both inputs 2, 3 grounded) as given by equation () can be
rewritten as,
0.25
𝑓0 = 𝐻𝑧 →1
𝐶𝑇 𝑅𝑇
Where RT and CT are the external resistor and capacitor connected to pin 8 and pin 9.
 A value between 2 kΩ and 20 kΩ is recommended for RT. The VCO free running frequency
is adjusted with RT and CT to be at the centre of the input frequency range.
 It may be seen that phase locked loop is internally broken between the VCO output and the
phase comparator input.
 A short circuit between pins 4 and 5 connects the VCO output to the phase comparator so as
to compare f0 with input signal fS.
 A capacitor C is connected between pin 7 and pin 10 (supply terminal) to make a low pass
filter with the internal resistance of 3.6 kΩ.

23
 Figure 27(a): Pin Diagram

Figure 27 (b) NE/SE565 PLL block diagram

 The important electrical parameters of 565 PLL are:

Operating frequency range : 0.001 Hz to 500 kHz

Operating voltage range : ±6V to ±12V
Input level : 10 mV rms min. to 3VPP max
Input impedance : 10 kΩ typical
Outputs sink current : 1 mA typical
Drift in VCO centre frequency: 300 ppm/°C (parts per million per degree with
Temperature centigrade)
Drift in VCO centre frequency: 1.5 percent / Vmax
With supply voltage

24
 Triangle wave amplitude : 2.4 Vpp at ± 6 V supply voltage
Square wave amplitude : 5.4Vpp at ± 6 V supply voltage
Bandwidth adjustment range: <± 1 to±60%

 The capture range is symmetrically located with respect to VCO free running frequency f0 as
is shown in Fig. 28.
 The PLL cannot acquire a signal outside the capture range, but once captured, it will hold on
till the signal frequency goes beyond the lock-in range.
 In order to increase the ability of lock-in range, large capture range is required.
 However, a large capture range will make the PLL more susceptible to noise and undesirable
signal.
 Hence a suitable compromise is often reached between these two opposing requirements of
the capture range.
 Many a times the LPF band-width is first set for a large value for initial acquisition of signal,
then once the signal is captured, the band-width of LPF is reduced substantially. This will
minimize the interference of undesirable signals and noise.

8 With Usual notations, show that the ‘lock-in-range’ of PLL is ∆𝒇𝑳=±𝟕.𝟖𝒇𝟎 / V. [Nov/Dec
2011].
 If 𝜑radians are the phase difference between the signal and the VCO voltage, then the
output voltage of the analog phase detector is given by,
𝑣𝑒= (φ – π/2) ------------------- (1)

𝑊ℎ, is the phase angle-to-voltage transfer coefficient of the phase detector.

 The control voltage to VCO is,
𝑣𝑐= (φ – π/2) ------------------ (2)

Where, A is the voltage gain of the amplifier. This 𝑣𝑐shifts VCO frequency from its free
running frequency fo to a frequency f given by,
𝑓 = 𝑓0 + Kvvc------------------- (3)

Where, Kv is the voltage to frequency transfer coefficient of the VCO.

When PLL is locked-in to signal frequency fs, then we have
𝑓 = 𝑓𝑠 = 𝑓0 + Kvvc ------------------ (4)
Since, vc= (𝑓𝑠 - 𝑓0 ) / Kv = 𝐴𝐾𝜑(φ – π/2) ------------------ (5)
Thus, 𝜑 = 𝜋/2 + (𝑓𝑠 − 𝑓0 )/𝐾𝑉 𝐾𝜑 𝐴 ------------------ (6)
 The maximum output voltage magnitude available from the phase detector occurs for φ =
π and 0 radian and (max) = ±𝐾𝜑 . 𝜋⁄2The corresponding value of the maximum control
voltage available to drive the VCO will be,
𝜋
𝑣𝑐(max) = ± ( 2 ) . 𝐾𝜑 . 𝐴 -------------------- (7)

25
  The maximum VCO frequency swing that can be obtained is given by,
𝜋
(𝑓 − 𝑓0 )𝑚𝑎𝑥 = 𝐾𝑣 𝑉𝑐(max) = 𝐾𝑉 𝐾𝜑 𝐴 ( ) -------------------- (8)
2

 Therefore, the maximum range of signal frequencies over which the PLL can remain
locked will be,
𝑓𝑠 = 𝑓0 ± (𝑓 − 𝑓0 )𝑚𝑎𝑥
𝜋
= 𝑓0 ± 𝐾𝑉 𝐾𝜑 𝐴 ( 2 ) = 𝑓0 ± ∆𝑓𝐿 ------------------- (9)

Where 2 ∆𝑓𝐿 will be lock-in frequency range and is given by,

Lock-in range = 2 ∆𝑓𝐿 = 𝐾𝑉 𝐾𝜑 𝐴𝜋 ------------------- (10)
𝜋
∆𝑓𝐿 = ±𝐾𝑉 𝐾𝜑 𝐴 ( 2 ) ------------------- (11)

 The lock in range is symmetrically located with respect to VCO free running frequency .
For IC PLL 565,
8𝑓0
𝐾𝑉 =
𝑉

Where, V = +Vcc – (-Vcc)

1.4
Again, 𝐾𝜑 = 𝜋
And A = 1.4
Hence the lock-in range from eqn (11) becomes,

---------------- (12)

9 Derive the expression for the capture range of PLL.

 When PLL is not initially locked to the signal, the frequency of the VCO will be free
running frequency fo. The phase angle difference between the signal and the VCO output
voltage will be,
𝜑 = (𝜔𝑠 𝑡 + 𝜃𝑠 ) − (𝜔0 𝑡 + 𝜃0 ) = (𝜔𝑠 − 𝜔0 )𝑡 + ∆𝜃 ---------------- (13)

 Thus the phase angle difference does not remain constant but will change with time at a
rate given by
𝑑𝜑
= 𝜔𝑠 − 𝜔0 ---------------- (14)
𝑑𝑡

 The phase detector output voltage will therefore not have a dc component but will
𝜋
produce an ac voltage with a triangular waveform of peak amplitude 𝐾𝜑 ( )and a
2
fundamental frequency(𝑓 − 𝑓0 ) = ∆𝑓.
 The low pass filter (LPF) is a simple RC network having transfer function
1
T(jf) ≈ f ---------------- (15)
1+j( )
f1

26
 Where, f1 = ½ RC is the 3 dB point of LPF. In the slope portion of LPF where (f/f1) 2 >> 1,
then
𝑓1
T(f) = ----------------- (16)
jf

 The fundamental frequency term supplied to the LPF by the phase detector will be the
difference frequency ∆𝑓 = 𝑓𝑠 − 𝑓0 . If∆𝑓 > 3𝑓1 , the LPF transfer function will be
approximately,

𝑇(∆𝑓) ≈ 𝑓1 /∆𝑓 = 𝑓1 /(𝑓𝑠 − 𝑓0 ) ----------------- (17)

 The voltage vc to drive the VCO is,
𝑣𝑐 = 𝑣𝑒 × 𝑇(𝑓) × 𝐴 ----------------- (18)
Or, 𝑣𝑐(𝑚𝑎𝑥) = 𝑣𝑒(𝑚𝑎𝑥) × 𝑇(𝑓) × 𝐴
𝜋
= ±𝐾𝜑 ( 2 ) 𝐴(𝑓1 ⁄∆𝑓) [From eqn.7] ----------------- (19)

 Then the corresponding value of the maximum VCO frequency shift is,
𝜋
(𝑓 − 𝑓0 )𝑚𝑎𝑥 = 𝐾𝑉 𝑣𝑐(𝑚𝑎𝑥) = ±𝐾𝜑 ( ) 𝐴(𝑓1 ⁄∆𝑓) ------------------ (20)
2

 For the acquisition of signal frequency, we should put f = fs so that the maximum signal
frequency range that can be acquired by PLL is,
𝜋
(𝑓 − 𝑓0 )𝑚𝑎𝑥 = ±𝐾𝑉 𝐾𝜑 ( ) 𝐴(𝑓1 ⁄∆𝑓𝑐 )------------------ (21)
2

Now, ∆𝑓𝑐 = (𝑓 − 𝑓0 )𝑚𝑎𝑥

So,
𝜋
(∆𝑓𝑐 )2 = ±𝐾𝑉 𝐾𝜑 ( ) 𝐴𝑓1 [From eqn.21]
2
𝜋
Since, ∆𝑓𝐿 = ±𝐾𝑉 𝐾𝜑 ( 2 ) 𝐴

We get,(∆𝑓𝑐 ) = ±√𝑓1 ∆𝑓𝐿 ----------------- (22)

 Therefore, the total capture range is,

2∆𝑓𝑐 ≈ 2√𝑓1 ∆𝑓𝐿

Where the lock-in range = 2∆𝑓𝑐 = 𝐾𝑉 𝐾𝜑 𝐴𝜋. In case of IC PLL 565, R = 3.6 K , so
the capture range is

----------------- (23)

Where, C is in farads.
 The capture range is symmetrically located with respect to VCO free running frequency f0 as
shown in the figure below.

27
 The PLL cannot acquire a signal outside the capture range, but once captured, it will hold on
till the signal frequency goes beyond the lock-in range.
 In order to increase the ability of lock-in range large capture range is required.
 However, a large capture range will make the PLL more susceptible to noise and undesirable
signal.
 Hence a suitable compromise is often reached between these two opposing requirements of
the capture range.
 Many a times the LPF bandwidth is first set for a large value for initial acquisition of signal,
then once the signal is captured, the bandwidth of LPF is reduced substantially.
 This will minimize the interference of undesirable signals and noise.

Figure 28: PLL lock in range and capture range

PROBLEM:

10 Determine the output frequency f0, lock range ∆fl and capture range ∆fc of IC 565. Assume R1
= 15Ω, C1= 0.01µF and the supply voltage is +12V. (Apr/May 2019) 15 marks.

Output frequency (f0)

0.25
𝑓0 = 𝐻𝑧
𝐶𝑇 𝑅𝑇

= 0.25/ (0.01 x 10-6 x 15)

f0 = 1.6 MHz

lock range (∆fL)

fL = ± 7.8 f0/ V

fL = 1.03 MHz

capture range ∆fc

28
 [1.3×𝟏𝟎𝟔 ]
√
𝟐 𝝅 × 𝟑. 𝟔 × 𝟏𝟎𝟑 × 𝟏 × 𝟏𝟎−𝟔

∆fc = 127.6MHz

4.4.3 PLL APPLICATIONS

11 Mention briefly the applications of PLL. [April/May 2008][Apr/May 2011][April/May
2013][Nov/Dec 2016]

 The output from a PLL system can be obtained either as the voltage 7 signal vc(t)
corresponding to the error voltage in the feedback loop, or as a frequency signal at VCO
output terminal.
 The voltage output is used in frequency discriminator application whereas the frequency
output is used in signal conditioning, frequency synthesis or clock recovery applications.
 Consider the case of voltage output.
 When PLL is locked to an input frequency, the error voltage v c(t) is proportional to (fs-f0).
 If the input frequency is varied as in the case of FM signal, vc will also vary in order to
maintain the lock.
 Thus the voltage output serves as a frequency discriminator which converts the input
frequency changes to voltage changes.
 In the case of frequency output, if the input signal is comprised of many frequency
components corrupted with noise and other disturbances, the PLL can be made to lock,
selectively on one particular frequency component at the input.
 The output of VCO would then regenerate that particular frequency (because of LPF which
gives output for beat frequency) and attenuate heavily other frequencies.
 VCO output thus can be used for regenerating or reconditioning a desired frequency signal
(which is weak and buried in noise) out of many undesirable frequency signals.
Some of the typical applications of PLL are discussed now.
4.4.3.1 Frequency Multiplication/Division
 Figure 30 gives the block diagram of a frequency multiplier using PLL.
 A divide by N network 18 inserted between the VCO output and the phase comparator input.
 In the locked state, the VCO output frequency fo is given by,
f0 = N fs1
 The multiplication factor can be obtained by selecting a proper scaling factor N of the
counter.
 Frequency multiplication can also be obtained by using PLL in its harmonic locking mode.
 If the input signal is rich in harmonics e.g. square wave, pulse train etc., then VCO can be
directly locked to then the harmonic of the input signal without connecting any frequency
divider in between.

29
 Figure 29: Frequency multiplier using IC PLL

 However, as the amplitude of the higher order harmonics becomes less, effective locking
may not take place for high values of 12. Typically n is kept less than 10.
 The circuit of Fig. 28 can also be used for frequency division.
 Since the VCO output (a square wave) is rich in harmonics, it is possible to lock the m-th
harmonic of the VCO output with the input signal f5.
 The output f0 of VCO is now given by
fo = fs/m 2
4.4.3.2 Frequency Translation
 A schematic for shifting the frequency of an oscillator by a small factor is shown in Fig. 31.
 It can be seen that a mixer (or multiplier) and a low-pass filter are connected externally to the
PLL.
 The signal fS which has to be shifted and the output frequency fo of the VCO are applied as
inputs to the mixer.
 The output of the mixer contains the sum and difference of fs and f0.
 However, the output of LPF contains only the difference signal (fo - fs).
 The translation or offset frequency f1(fl<<fs) is applied to the phase comparator.

Figure 30: PLL used as a frequency translator

30
 When PLL is in locked state,
fo - fs= f1
fo = fs+ f13
Thus, it is possible to shift the incoming frequency fs by f1.

4.4.3.3 AM Detection
 The PLL may be used to demodulate AM signals as shown in figure below. The PLL is
locked to the carrier frequency of the incoming AM signal.
 The output of VCO which has the same frequency as the carrier, but un modulated is fed to
the multiplier.
 Since VCO output is always 900 out of phase with the incoming AM signal under the locked
condition, the AM input signal is also shifted in phase by 900 before being fed to the
multiplier.
 This makes both the signals applied to the multiplier in same phase.
 The output of the multiplier contains both the sum and the difference signals; the
demodulated output is obtained after filtering high frequency components by the LPF.
 Since the PLL responds only to the carrier frequencies which are very close to the VCO
output, a PLL AM detector exhibits a high degree of selectivity and noise immunity which is
not possible with conventional peak detector type AM modulators.

Figure 31: PLL used as AM demodulator

4.4.3.4 FM Demodulation
 If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of the input
signal.
 The filtered error voltage which controls the VCO and maintains lock with the input signal is
the demodulated FM output.
 The VCO transfer characteristics determine the linearity of the demodulated output.
 Since, VCO used in IC PLL is highly linear, it is possible to realize highly linear FM
demodulators.
4.4.3.5 Frequency Shift Keying (FSK) Demodulator
12 Narrate the process of FSK demodulation using PLL [Nov/Dec 2015] [May 2018] [6].

 In digital data communication and computer peripheral, binary data is transmitted by means
of a carrier frequency which is shifted between two preset frequencies.
 This type of data transmission is called frequency shift keying (FSK) technique.

31
 The binary data can be retrieved using a FSK demodulator at the receiving end.
 The 565 PLL is very useful as a FSK demodulator.
 Figure 30 shows FSK demodulator using PLL fortele - typewriter signals of 1070 Hz and
1270 Hz.
 As the signal appears at the input, the loop locks to the input frequency and tracks it between
the two frequencies with a corresponding dc shift at the output.
 A three stage filter removes the carrier component and the output signal is made logic
compatible by a voltage comparator.

Figure 32: FSK Demodulator

4.5 ANALOG MULTIPLIER IC

13 Discuss the modes of operation and applications of analog multiplier.

 A multiplier is a circuit which produces output that is the product of two inputs applied.
 A circuit which performs multiplication of two analog voltages is called as analog multiplier.
 If V1 and V2 were the two input analog voltages applied, then the output voltage V0 is given
as,
V0 = k V1 V2
Where, k – scaling factor
 The use of a scaling factor k is to avoid the saturating output.
 This is because; the product of two input voltages with moderate value could cause the
output to reach saturation.
 In such a situation, it may become impossible to measure the desired product output V 0.
 The above expression for V0 is the ideal output voltage. They are
(i) Input signal offset (φ1& φ2)
(ii) Error in scaling factor k (e)
(iii) Output signal offset (φ0)
 With all these parameters, the output of a practical multiplier is given as V 0 defined by,

32
 (𝑉1 + 𝜑1 )(𝑉2 + 𝜑2 )
𝑉0 = + 𝜑0
10𝑋 (1 + 𝑒)
 Note that x can be any integer or fractional value.
4.5.1 Modes of operation of a multiplier
 The modes of operation of multiplier tell about the restriction on polarity of one or both input
voltages V1 and V2 applied to multiplier. There were three modes
 One quadrant multiplication
 Two quadrant multiplication
 Four quadrant multiplication
One quadrant
 Both input voltages V1 and V2 are restricted to positive
polarity.
 That is, V1 and V2 must be positive as shown here. It uses
first quadrant.

Figure 33(a): one quadrant

Two quadrant
 In this mode, any one input voltage V1 or V2 is held positive and the other is allowed to
swing in both positive and negative polarity.
 It uses any two of four quadrants (Quadrant I and II or I and IV) as shown here.

Figure 33(b): two quadrant

Four quadrant (Gilbert cell)
 In this mode, both the input voltages V1 and V2 are allowed to swing in both positive and
negative polarity.
 It uses all four quadrants and hence the same. The figure here shows the four quadrant
multiplication.
 Also, it is clear that not only the input voltages are restricted in the modes; the output voltage
V0 is also restricted.
 In one quadrant multiplication, the output voltage V0 must be positive since both inputs are
positive.
 But, in two quadrant and four quadrant multiplication, the output can be positive or negative
depending on input voltage polarity.

33
 Three quadrant operations is impossible in multiplier because no restriction can be made in
input voltages.
 Out of all modes of operation, four quadrants is best and popular.

Figure 33(c): four quadrant

4.5.2 Types of Analog multipliers

 The basic techniques used to achieve multiplication are
 Logarithmic type
 Quarter square type
 Pulse width / height modulation type
 Current rating type
 Triangle averaging type
 Emitter coupled transistor pair type
 Variable Trans conductance type
 Four quadrant type based on variable Trans conductance (or) simply, Gilbert cell.
4.5.3 Characteristics (or) Requirements of a multiplier
 The following characteristics or requirements are very important for a multiplier to achieve
maximum efficiency. They are defined here,
Accuracy
 The derivation of practical output from the ideal output of multiplier for the given input
voltages within the operating range of multiplier.
 This characteristic tells how accurate the multiplier is and whether the expected output is
obtained or not.
Linearity
 It is the maximum percentage deviation that a practical output compared with a linear straight
line output (ideal output).
Squaring mode accuracy
 The accuracy of multiplier when both inputs tied together gives square-law curve.
 The deviation of practical squared output versus ideal square-law curve is squaring mode
accuracy.
Bandwidth
 The operating capability of an amplifier for high frequency analog inputs is indicated with
bandwidth.

34
 Capability with as high frequency as possible indicates the improvement in bandwidth.
Quadrant
 Defines the unipolar or bipolar capabilities of input voltages applied.
14 Explain the working of an analog multiplier using emitter coupled transistor pair.
[Nov/Dec 2014][May/June 2014][Nov/Dec 2011]
 A pair of transistor with their emitter connected together forms a basic multiplier.
 One input V1 can be directly applied to the base of transistors Q1 and Q2.
 The other input V2 is applied as the emitter current to both transistors as shown in figure
below.

Figure 34: Emitter coupled transistor

 Taking only the emitter coupled transistor pair stage, the output currents (collector currents)
IC1 and IC2 are related to the differential input voltage V1 by
𝐼𝐸𝐸
𝐼𝐶1 =
1 + 𝑒 −𝑉1 ⁄𝑉𝑇
𝐼𝐸𝐸
𝐼𝐶2 =
1 + 𝑒 𝑉1 ⁄𝑉𝑇
Where VT is the temperature equivalent voltage and the polarity in exponential terms
depends on the input voltage V1.
 The polarity is negative when positive input of V1 applied to base of transistor Q1
 The polarity is positive when the negative input of V1 applied to base of transistor Q2.
 Taking the difference between two collector currents I C1 and IC2 as ΔIC, we can write
ΔIC = IC1 - IC2
Substituting the values of IC1 and IC2 in above expression
𝐼𝐸𝐸 𝐼𝐸𝐸
∆𝐼𝐶 = −
1 + 𝑒 1 𝑇 1 + 𝑒 𝑉1 ⁄𝑉𝑇
−𝑉 ⁄𝑉

35
 1 1
= 𝐼𝐸𝐸 [ − ]
1 + 𝑒 −𝑉1 ⁄𝑉𝑇 1 + 𝑒 𝑉1 ⁄𝑉𝑇
𝑉
∆𝐼𝐶 = 𝐼𝐸𝐸 𝑡𝑎𝑛ℎ (2𝑉1 ) ------------------- (1)
𝑇

 The DC transfer characteristics of the emitter coupled pair are shown in figure below.

Figure 35: DC characteristics

 If V1<< VT, eqn. (1) can be approximated as
𝑉 𝑉
∆𝐼𝐶 = 𝐼𝐸𝐸 𝑡𝑎𝑛ℎ (2𝑉1 ) ≅ 𝐼𝐸𝐸 (2𝑉1 ) ------------------- (2)
𝑇 𝑇

 IEE is the bias current for emitter-coupled pair. If IEE is made proportional to the second input
V2, then eqn. (2) becomes
𝑉1
∆𝐼𝐶 = 𝑉2 ( ) 𝑤ℎ𝑒𝑟𝑒 𝑉2 𝛼 𝐼𝐸𝐸
2𝑉𝑇
 Thus the collector difference current is proportional to the product of two input voltages V 1
1
and V2 multiplied by factor2𝑉 . But, considering the base to emitter voltage of transistor, I EE
𝑇
can be written as
𝐼𝐸𝐸 ≅ 𝐾0 (𝑉2 − 𝑉𝐵𝐸(𝑂𝑁) ) ------------------- (3)

Substitute the value of IEE from eqn. (3) in ΔIC of eqn. (2) we get

𝐾0 𝑉1 (𝑉2 − 𝑉𝐵𝐸(𝑂𝑁) )
∆𝐼𝐶 =
2𝑉𝑟
 Where, k0 is the scaling factor. Two conditions must be satisfied by the input voltages in
order to perform multiplication. V1 must be less than 50 mV and V2 must be greater than
VBE(ON).

4.5.4 Drawbacks
 The input voltage V2 is offset by VBE(ON). So the desired input V2 cannot be multiplied with
other input V1. Thus the preciseness in getting the product output is affected.
 V2 must be always positive resulting in two-quadrant multiplication.
𝑉1 𝑉1
 𝑡𝑎𝑛ℎ ( ) is approximated as ( ) with the assumption V1<< VT
2𝑉𝑇 2𝑉𝑇

36
 In room temperature, VT = 26mV. Therefore, V1 must be very small to satisfy the
approximation.

15 Explain Gilbert multiplier cell. Under what condition the Gilbert multiplier cell will
work as a modulator. [Nov/Dec 2009][Nov/Dec 2013]
 The first two drawbacks of emitter coupled transistor pair multiplier can be eliminated by
Gilbert multiplier cell.
 Gilbert multiplier cell is also known as four-quadrant multiplier cell.
 It allows the two input voltages to swing in both polarities.
 This method is an extension of emitter coupled transistor pair. The circuit of Gilbert cell is
shown in figure below.

Figure 36: Gilbert multiplier cell

 The circuit consists of three stages with each stage having a pair of transistors.
 All the stages are emitter coupled transistor pair with cross coupled stages 1 and 2 in series
with stage 3.
 The analysis of the circuit can be done using two methods.
 Analysis 1 uses hyperbolic tangent function and analysis 2 uses the basic principle of Tran’s
conductance dependence.

Analysis 1:
 As related to discussion of emitter coupled transistor pair, the collector currents of all stages
are related with input voltages as follows.
 The collector current of Q1 and Q2 are given as,
𝐼
𝐶5
𝐼𝐶1 = 1+𝑒 −𝑉 1 ⁄𝑉𝑇
------------------- (1)

37
 𝐼
𝐼𝐶2 = 1+𝑒 𝑉𝐶51 ⁄𝑉𝑇 [IC5 is emitter current of pair Q1 and Q2]------------------- (2)

 Similarly, collector currents of Q3 and Q4 are given as,

𝐼𝐶6
𝐼𝐶3 = ------------------- (3)
1+𝑒 𝑉1 ⁄𝑉𝑇

𝐼
𝐶6
𝐼𝐶3 = 1+𝑒 −𝑉 1 ⁄𝑉𝑇
[IC6 is emitter current of pair Q3 and Q4] ------------------- (4)

 And the collector current of Q5 and Q6 can be given as,

𝐶5 𝐼
𝐼𝐶1 = 1+𝑒 −𝑉 1 ⁄𝑉𝑇
------------------- (5)

𝐼
𝐼𝐶2 = 1+𝑒 𝑉𝐶51 ⁄𝑉𝑇 [IC5 is emitter current of pair Q1 and Q2] ------------------- (6)

 Substituting the values of IC5 and IC6 from eqns. (5) and (6) in equations (1), (2), (3) and (4),
we get,
𝐼
𝐼𝐶1 = [1+𝑒 −𝑉1 ⁄𝑉𝑇𝐸𝐸 ------------------- (7)
][1+𝑒 −𝑉2 ⁄𝑉𝑇 ]

𝐼𝐸𝐸
𝐼𝐶2 = ------------------- (8)
[1+𝑒 𝑉1 ⁄𝑉𝑇 ][1+𝑒 −𝑉2 ⁄𝑉𝑇 ]

𝐼
𝐼𝐶3 = [1+𝑒 𝑉1 ⁄𝑉𝑇𝐸𝐸 ------------------- (9)
][1+𝑒 𝑉2 ⁄𝑉𝑇 ]

𝐼
𝐼𝐶4 = [1+𝑒 −𝑉1 ⁄𝑉𝑇𝐸𝐸 ------------------- (10)
][1+𝑒 𝑉2 ⁄𝑉𝑇 ]

 The differential output current ΔI is given as,

∆I = IL1 − IL2

Where, IL1 =IC1 + IC3 and IL2 = IC2 + IC4 from the figure

∴ ∆𝐼 = (𝐼𝐶1 + 𝐼𝐶3 ) − (𝐼𝐶2 + 𝐼𝐶4 )

[or]
∆𝐼 = (𝐼𝐶1 + 𝐼𝐶4 ) − (𝐼𝐶2 + 𝐼3 )------------------- (11)
 Substitute the equation (7) to (10) in (11) and taking exponential terms as hyperbolic tangent
functions, we get
𝑉1 𝑉2
∴ ∆𝐼 = 𝐼𝐸𝐸 [𝑡𝑎𝑛ℎ ( ) 𝑡𝑎𝑛ℎ ( )]
2𝑉𝑇 2𝑉𝑇

 Thus the differential output ΔI is the product of the hyperbolic tangent of two input voltages
V1 and V2.

38
 The output voltage V0 can be obtained from ΔI by using two equal value resistors R
connected to VCC and sending current IL1 = (IC1 + IC3) through one resistor and IL2 = (IC2 +
IC4) through other resistor.

Analysis 2
 The emitter currents of stage 1 and 2 are the collector currents of stage 3 (I C5 and IC6 in the
figure).
 The current relationships are
IC1 + IC2 = IC5
IC3 + IC4 = IC6
IC5 + IC6 = IEE
 Assume that |𝑉1 |𝑎𝑛𝑑|𝑉2 | ≪ 𝑉𝑇 and current imbalance is given by
IC1 − IC2 = (g m )12 V1 ------------------------ (1)
IC3 − IC4 = (g m )34 V1 ------------------------ (2)
Where, (gm)12 and (gm)34 are Trans conductance of pairs Q1 – Q2& Q3 – Q4 respectively.
𝐼
(𝑔𝑚 )12 = 𝐶5
𝑉𝑇
𝐼𝐶6
(𝑔𝑚 )34 =
𝑉𝑇
𝐼
[In general, 𝑔𝑚 = 𝑉𝐸 in Transconductance technique]
𝑇

 Here, IC5 and IC6 are nothing but emitter currents of stage 1 and stage 2 respectively.
The differential output voltage V0 is

V0 = RL [(IC1 - IC2) – (IC3 - IC4)] ------------------------ (3)

Substitute the equations (1) and (2) in (3), we get

V0 = R L [(g m )12 V1 − (g m )34 V1 ]

𝐼𝐶5 𝐼𝐶6
𝑉0 = 𝑅𝐿 𝑉1 [ − ]
𝑉𝑇 𝑉𝑇
𝑅𝐿 𝑉1
𝑉0 = (𝐼𝐶5 − 𝐼𝐶6 )------------------------ (4)
𝑉𝑇

If RE is chosen such that

IC5 RE>> VT& IC6 RE>> VT then,
𝑉
𝐼𝐶5 − 𝐼𝐶6 = 𝑅2 ------------------------ (5)
𝐸

Substitute eqn. (5) in (4)

𝑅𝐿 𝑉1 𝑉2
𝑉0 = ( )
𝑉𝑇 𝑅𝐸

39
 Rearranging we get
𝑅𝐿
𝑉0 = (𝑉1 𝑉2 )
𝑉𝑇 𝑅𝐸

V0 = KV1V2
𝑅𝐿
Where 𝐾 = 𝑉 is the scaling factor.
𝑇 𝑅𝐸

 Thus the output voltage V0 is the product of two input voltages V1 and V2 multiplied by
scaling factor k.
Applications
 Used in most of the IC multipliers as a four quadrant cell.
 Used as modulators or mixers in communication circuits
 Used in signal processors.
 Used as detectors or demodulators to recover low frequency signals
 Used as phase detectors.
 Used as frequency doubler, squarer, square rooter, divider, etc.
17. with a neat diagram, explain the variable Trans conductance technique in analog
multiplier and give its output equation. [April/May 2010][May/June 2009, 2018] [13].

 The following figure shows the differential stage used for variable Transconductance
technique.
 The principle of operation is the dependence of transistor Transconductance on the emitter
current bias applied.
 The emitter current bias is controlled by the second input voltage V 2. Q1 and Q2 in the circuit
form the differential amplifier.

Figure 37: Variable trans conductance amplifier

 For very small differential voltage V1<< VT the output voltage is given as
V0 = gm RL V1 -------------------- (1)

40
 𝐼
Where, 𝑔𝑚 = 𝑉𝐸 is the Trans conductance ------------------- (2)
𝑇

 Note that V0 depends on gm and gm depends on IE. By changing V2, IE changes, thereby gm
changes. From the diagram,
𝑉2 = 𝐼𝐸 𝑅𝐸 + 𝑉𝐵𝐸3
 If IERE>>VBE3
V2 = IERE&
𝑉
Thus 𝐼𝐸 = 𝑅2
𝐸

Substitute IE in (2) and then gm in (1) we get

𝑉2
𝑉0 = 𝑅 . 𝑅𝐿 𝑉1 -------------------- (3)
𝐸 𝑉𝑇

Rearranging (3), we get

𝑅𝐿
𝑉0 = (𝑉1 . 𝑉2 )
𝑅𝐸 𝑉𝑇
𝑅𝐿
Take 𝐾 = 𝑅
𝐸 𝑉𝑇

V0 = k V1.V2
& ‘k’ is the scaling factor.

 To improve linearity of the multiplier, exponential current voltage characteristics can be

converted to linear characteristics as shown in the following figure.

Figure 38: Improved linearity of multiplier

 The two transistors QA& QB is a diode connected transistor and are driven by I A& IB, I1& I2
are related as

41
 𝐼1
= 𝑒 (𝑉1 ⁄𝑉2 ) ------------------ (4)
𝐼2

And the net bias voltage V1 is logarithmic and given as

𝐼𝐵
𝑉1 = 𝑉𝑇 ln ( )
𝐼𝐴

And substituting V1 in I1/I2 we get

𝐼1 𝐼
= 𝐼𝐵 ; Assuming that VT is very small.
𝐼2 𝐴
A four quadrant multiplier – complete circuit

 As shown in figure, the complete circuit consists of voltage to current converters or current to
voltage converters.
 The currents I9 and I10 through the emitters of Q 7 and Q8 generate a voltage between two
emitter terminals that is proportional to inverse hyperbolic tangent of V1.
 It uses Gilbert cell for four quadrant multiplication.

Figure 39: four quadrant multiplication using Gilbert multiplier

42
 4.6 AD633 ANALOG MULTIPLIER ICS

18. Write short notes on Analog multiplier ICs (Monolithic multipliers).

There were several multiplier Ics available. Important Ics are AD 533, AD 534 & AD
633.
4.6.1 AD 533
 Accepts input upto 1 MHZ with 1% error.
4.6.2 AD 534
 Provides maximum gain with error of 0.25%.
 Also provides excellent stability upto 10 KHz and a flexible IC.
4.6.3AD 633
 This is a four quadrant analog multiplier.
 It has high input impedance, operates with voltage ranging from 8V to 18V.
 This IC needs no external components and calibration.
 The range of the two input signals is 10 V.
 The pin diagram of AD 633 is shown in figure (b) and basic symbol of multiplier is
shown in figure (a).
4.6.4 Symbol of a multiplier

Figure 40(a): symbol for multiplier

1 1
 The output voltage V0 = k VxVy where k is selected as 𝐾 = 𝑉 = 10𝑉 .
𝑟𝑒𝑓

 The reference voltage Vref is internally set to 10 V.

 The operating input voltage as can be Vx = Vy≤ 10V until then the multiplier do not saturate.
 The transfer characteristics of a four quadrant multiplier is shown in fig (b)
 The above characteristics diagram shows the output voltage for both positive and
negative input voltages.
 The output voltage is positive when both inputs Vx and Vy are positive (or) negative.
 The output is negative if any one input is (Vx or Vy) is negative.
 The AD633 is a low cost multiplier comprising a translinear core, a buried Zener
reference, and a unity gain connected output amplifier with an accessible summing
node.

43
 Fig 40(b) Transfer characteristics
 The differential X and Y inputs are converted to differential currents by voltage-to-current
converters.
 The product of these currents is generated by the multiplying core.
 A buried Zener reference provides an overall scale factor of 10 V. The sum of (X × Y)/10 +
Z are then applied to the output amplifier.
 The amplifier summing node Z allows the user to add two or more multiplier outputs, convert
the output voltage to a current, and configure various analog computation functions.

4.6.5 APPLICATIONS
The AD633 is well suited for such applications as,
 Modulation
 Demodulation
 Automatic gain control
 Power measurement
 Voltage controlled amplifiers
 Frequency doublers

19. Discuss in detail the various applications of multiplier ICs. [May/June 2014][May/June
2012][April/May 2011].

4.6.5.1 Voltage Squarer

 The simplest application of multiplier is voltage squarer.
 When both inputs of multiplier tied together and applied with same input then, the
resulting application is voltage squarer.
Inputs Vx= Vy = Vi
Output Vo = k VxVy
44
 = k. Vi2
1 1
=𝑉 . 𝑉𝑖2 [ 𝐾 = 𝑉 , the scaling factor]
𝑟𝑒𝑓 𝑟𝑒𝑓

𝑉2
𝑉0 = 𝑉 𝑖
𝑟𝑒𝑓

Figure 41: Voltage squarer

The above figure shows the voltage squarer using multiplier.
4.6.5.2 Frequency Doubler
 The circuit diagram in fig (a) and the waveform diagram in fig (b) and expressions for a
frequency doubler are given.
 In this input signal Vi =5sin2𝜋(10,000)t ; Av = 5 V is the peak amplitude and 10k is the
frequency in Hertz.
 According to output voltage expression and substituting Av and f, V0 is given as

𝐴2𝑉
𝑉0 = (1 − 𝑐𝑜𝑠4𝜋𝑓𝑡)
20
(5)2
= (1 − 𝑐𝑜𝑠4𝜋(10𝐾)𝑡)
20
V0 = 1.25 – 1.25 cos 2π (20000) t

45
 Figure 42: Frequency doubler

𝐴𝑉 𝑠𝑖𝑛2𝜋𝑓𝑡𝑋𝐴𝑉 𝑠𝑖𝑛2𝜋𝑓𝑡
𝑉0 =
10
𝐴2𝑉
= 𝑠𝑖𝑛2 (2𝜋𝑓𝑡)
10
𝐴2𝑉
𝑉0 = (1 − 𝑐𝑜𝑠4𝜋𝑓𝑡)
20

 This input voltage V0 is passed to a HPF to take ac term alone.

 The first term 1.25 V represents the peak level of dc component and second term is the ac
component.
 The shape of the signal changes in the output from sine to cosine and note the amplitude
of output decreases and frequency is doubled from 10 KHz to 20 KHz.

4.6.5.3 Voltage Divider

 Voltage divider can be implemented by connecting a multiplier in the feedback loop of an

op-amp as shown here in figure below.

Vnum is the numerator voltage and Vden is the denominator voltage.

 Note that node ‘a’ is at virtual ground and other end of R c is physically grounded.
From the diagram,

46
 𝑉𝑛𝑢𝑚 𝑉𝑜𝑚
i1 + i2 = 0 and substituting 𝑖1 = ; 𝑖2 =
𝑅 𝑅
𝑉𝑛𝑢𝑚 𝑉𝑜𝑚
+ =0
𝑅 𝑅

&Vom = k VOAVden = -Vnum

[Where Vom is output of multiplier with two inputs VOA and Vden]
−𝑉𝑛𝑢𝑚
𝑉𝑂𝐴 =
𝐾𝑉𝑑𝑒𝑛
K is the scale factor. Thus output VOA from op-amp is the divided voltage.

Figure 43: Voltage divider

4.6.5.4 Square rooter

 The figure of divider circuit can be used as square rooter by connecting both inputs of the
multiplier to the output of op-amp.

Vnum = k VOAVden

& VOA&Vden are tied together we get,

VOA = Vden = V0 [V0 is a common name assumed]

∵ 𝑉𝑛𝑢𝑚 = 𝐾𝑉02 ;

1
Take k = 10as scaling factor.

𝑉02 = 10 Vnum

𝑉0 = √10|𝑉𝑛𝑢𝑚 |

 Thus the output voltage is proportional to square root of V num applied to inverting
terminal of op-amp.

47
4.6.5.5 Phase angle detector

 The figure (a) shows the circuit and the figure (b) shows the input and output waveforms
of phase angle detector using a multiplier.

Figure 44: Phase angle detector

 Two sine waves with same frequency are applied to multiplier.
 They have different phase angles. The connection shown above in multiplier IC can be
used to detect the phase angle difference between two input signals.
1
Using sinAsinB = 2(cos(A-B)- cos(A- B))
1
[Sin (2πft + θ)] [Sin (2πft)] = 2[Cos𝜃 − cos(4𝜋𝑓𝑡 + 𝜃)]
1
= 2[dc – ac frequency term]
1 1
 The output of multiplier is passed to a LPF which provides 2dc as output. That is, 2cos θ.
𝑉𝑥𝑝 𝑉𝑦𝑝 1
∴ 𝑉𝑂(𝑑𝑐) = ( cos 𝜃)
10 2

𝑉𝑥𝑝 𝑉𝑦𝑝
∴ 𝑉𝑂(𝑑𝑐) = (cos 𝜃)
20

 The product Vxp Vyp is made to 20. So that output voltage is proportional to θ and the
phase angle difference between two sinusoidal input voltages applied.

48
49