UNIT – II

1. IDEAL OP-AMP CHARACTERISTICS

Part – B – 16Mark Questions
1.1 OPERATIONAL AMPLIFIER:
 The operational amplifier, most commonly referred as ‘op-amp’ was introduced in 1940s. The
first operational amplifier was designed in 1948 using vacuum tubes.
 In those days, it was used in the analog computers to perform a variety of mathematical
operations such as addition, subtraction, multiplication etc. Due to its use in performing
mathematical operations it has been given a name operational amplifier.
 Due to the use of vacuum tubes, the early op-amps were bulky, power consuming and
expensive.
 Robert J. Widlar at Fairchild brought out the popular 741 integrated circuit (IC) op-amp
between 1964 and 1968.
 The IC version of op-amp uses BITS and FETs which are fabricated along with the other
supporting components, on a single semiconductor chip or wafer which is of a pinhead size.
 With the help of IC op-amp, the circuit design becomes very simple. The variety of useful
circuits can be built without the necessity of knowing about the complex internal circuitry.
 Moreover, IC op-amps are inexpensive, take up less space and consume less power.
 The IC op-amp has become an integral part of almost every electronic circuit which uses linear
integrated circuit.
 The modern linear IC op-amp works at lower voltages. It is so low in cost that millions are now
in use annually.
Key Point: Because of their low cost, small size, versatility, flexibility and dependability, op-amps are
used in the fields of process control, communications, computers, power and signal sources, displays
and measuring systems. The op-amp is basically an excellent high gain d.c. amplifier.
Symbol:
The symbol for an op-amp along with its various terminals is as follows:

 The op-amp is indicated basically by a triangle which points in the direction of the signal flow.
All the op-amps have at least following five terminals:
 The positive supply voltage terminal VCC or + V.
 The negative supply voltage terminal - VEEor V.
 The output terminal.
 The inverting input terminal, marked as negative.
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  The non-inverting input terminal, marked as positive.
 The input at inverting input terminal results in opposite polarity (antiphase) output.
 While the input at non-inverting input terminal results in the same polarity (phase) output.
 This is shown in the Fig. (a) and (b). The input and output are in antiphase means having 180°
phase difference in between them while in-phase input and output means having 0° phase
difference in between them.

1. Draw the Schematic block diagram of the basic OP-AMP.

1.2 BLOCK DIAGRAM REPRESENTATION OF OP-AMP:
 As mentioned earlier, now-a-days op-amps are available in an integrated Circuit form.
 Commercial integrated circuit op-amps usually consist of four cascaded blocks. The block
diagram of IC op-amp is shown in the Fig.

1.2.1 Input Stage:

 The input stage requires high input impedance to avoid loading on the sources. It requires two
input terminals.

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  It also requires low output impedance. All such requirements are achieved by using the dual
input, balanced output differential amplifier as the input stage.
 The function of a differential amplifier is to amplify the difference between the two input
signals.
 The differential amplifier has high input impedance. This stage provides most of the voltage
gain of the amplifier.
1.2.2 Intermediate Stage:
 The output of the input stage drives the next stage which is an intermediate stage.
 This is another differential amplifier with dual input, unbalanced i.e. single ended output.
 The overall gain requirement of the op-amp is very high. The input stage alone cannot provide
such a high gain.
 The main function of the intermediate stage is to provide an additional voltage gain required.
 Practically, the intermediate stage is not a single amplifier but the chain of cascaded amplifiers
called multistage amplifiers.
1.2.3 Level Shifting Stage:
 All the stages are directly coupled to each other.
 As the op-amp amplifies d.c. signals also, the coupling capacitors are not used to cascade the
stages.
 Hence the d.c. quiescent voltage level of previous stage gets applied as the input to the next
stage.
 Hence stage by stage d.c. level increases well above ground potential. Such a high d.c. voltage
level may drive the transistor into saturation.
 This further may cause distortion in the output due to clipping.
 This may limit the maximum a.c. output voltage swing without any distortion.
 Hence before the output stage, it is necessary to bring such a high d.c. voltage level to zero
volts with respect to ground.
 The level shifter stage brings the d.c. level down to ground potential, when no signal is applied
at the input terminals.
 Then the signal is given to the last stage which is the output stage.
 The buffer is usually an emitter follower whose input impedance is very high. This prevents
loading of the high gain stage.
1.2.4 Output Stage:
 The basic requirements of an output stage are low output impedance, large a.c. output voltage
swing and high current sourcing and sinking capability.
 The push-pull complementary amplifier meets all these requirements and hence used as an
output stage.
 This stage increases the output voltage swing and keeps the voltage swing symmetrical with
respect to ground.
 The stage raises the current supplying capability of the op-amp. In short, the overall block
diagram can be shown as in the Fig.

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1.2.5 Currents and Impedances:
 Practically an input stage is a transistorised differential amplifier stage using the two
transistors.
 The base terminals of these two transistors are the two input terminals of the op-amp.
 Some small d.c. base current is necessary to maintain the operating state of the transistors.
 These two base currents are the input bias currents of the op-amp. Typically the d.c. input
current is of the order of 500 nA or less.
 The input impedance Zin is very high of the order of 1 MΩ or greater.
 To increase the input impedance field effect transistors (FETs) are used instead of bipolar
junction transistors (BJTs).
 In such a case, gates of the two FETs are the input terminals of the op-amp.
 The output stage is an emitter follower having very low output impedance.
 The output impedance Z0 is usually 75 Ω and the maximum output current is of the order of 25
mA.
1.3 IDEAL OP-AMP CHARACTERISTICS:
2. Explain various characteristics of ideal op-amp. Distinguish between ideal and practical
characteristics. (12)

The Fig. shows an ideal op-amp. It has two input signals V1 and V2 applied to non-inverting
and inverting terminals, respectively.

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 The following things can be observed for the ideal op-amp:
i. An ideal op-amp draws no current at both the input terminals i.e. I 1 = I2 = 0. Thus its
input impedance is infinite. Any source can drive it and there is no loading on the
driver stage.
ii. The gain of an ideal op-amp is infinite (∞), hence the differential output Vd = V1 – V2
is essentially zero for the finite output voltage V0.
iii. The output voltage V0 is independent of the current drawn from the output terminals.
Thus its output impedance is zero and hence output can drive an infinite number of
other circuits.
These properties are expressed generally as the characteristics of an ideal op-amp. The various
characteristics of an ideal op-amp are:
1. Infinite voltage gain : (AOL = ∞)
It is denoted as AOL. It is the differential open loop gain and is infinite for an ideal op-
amp.
2. Infinite input impedance : (Rin = ∞)
The input impedance is denoted as Rin and is infinite for an ideal op-amp. This ensures
that no current can flow into an ideal op-amp.
3. Zero output impedance : (R0 = 0)
The output impedance is denoted as R0 and is zero for an ideal op-amp. This ensures
that the output voltage of the op-amp remains same, irrespective of the value of the load resistance
connected.
4. Zero offset voltage : (Vios = 0)
The presence of the small output voltage though V1= V2 = 0 is called an offset voltage.
It is zero for an ideal op-amp. This ensures zero output for zero input signal voltage.
5. Infinite bandwidth :
 The range of frequency over which the amplifier performance is satisfactory is called its
bandwidth.
 The bandwidth of an ideal op-amp is infinite.
 This means the operating frequency range is from 0 to ∞. This ensures that the gain of the op-
amp will be constant over the frequency range from d.c. (zero frequency) to infinite frequency.
 So op-amp can amplify d.c. as well as a.c. signals.
6. Infinite CMRR : (ρ = ∞)
The ratio of differential gain and common mode gain is defined as CMRR. Thus infinite
CMRR of an ideal op-amp ensures zero common mode gain. Due to this common mode noise output
voltage is zero for an ideal op-amp.
7. Infinite slew rate : (S = ∞)
 This ensures that the changes in the output voltage occur simultaneously with the changes in
the input voltage.
 The slew rate is important parameter of op-amp. When the input voltage applied is step type
which changes instantaneously then the output also must change rapidly as input changes.
 If output does not change with the same rate as input then there occurs distortion in the output.
 Such a distortion is not desirable.
 Infinite slew rate indicates that output changes simultaneously with the changes in the
input voltage.

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  The parameter slew rate is actually defined as the maximum rate of change of output voltage
with time and expressed in V /µs.
𝑑𝑉0
𝑆𝑙𝑒𝑤 𝑟𝑎𝑡𝑒 = 𝑆 = |
𝑑𝑡 𝑚𝑎𝑥
It’s ideal value is infinite for the op-amp.
8. No effect of temperature:
The characteristics of op-amp do not change with temperature.
9. Power Supply Rejection Ratio: (PSRR = 0)
 he power supply rejection ratio is defined as the ratio of the change in input offset voltage due
to the change in supply voltage producing it, keeping other power supply voltage constant.
 It is also called power supply sensitivity.
 So if VEE is constant and due to change in VCC, there is change in input offset voltage then
PSRR is expressed as,
∆𝑉𝑖𝑜𝑠
𝑃𝑆𝑅𝑅 = | 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐶𝐶 𝑉𝐸𝐸
For a fixed VCC, if there is change in V EE causing change in input offset voltage then,
∆𝑉𝑖𝑜𝑠
𝑃𝑆𝑅𝑅 = | 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
∆𝑉𝐸𝐸 𝑉𝐸𝐸
It is expressed in mV/V or µV/V and its ideal value is zero.
These ideal characteristics of op-amp are summarized as follows:
Characteristics Symbol Values
Open loop voltage gain AOL ∞
Input Impedance Rin ∞
Output Impedance R0 0
Offset Voltage Voo 0
Bandwidth B.W. ∞
C.M.R.R Ρ ∞
Slew Rate S ∞
Power Supply Rejection Ratio PSRR 0
1.4 PRACTICAL OP-AMP CHARACTERISTICS:
 The characteristics of an ideal op-amp can be approximated closely enough, for many practical
op-amps.
 But basically the practical op-amp characteristics are little bit different than the ideal op-amp
characteristics.
 The important d.c. characteristics of op-amp are, 1. Input bias current (Ib), 2. Input offset
current (Iios) 3. Input offset voltage (Vios ), 4. Thermal drift
 The various characteristics of a practical op-amp can be described as below.
a) Open loop gain:
 It is the voltage gain of the op-amp when no feedback is applied practically it is several
thousands.
b) Input impedance:
 It is finite and typically greater than 1 MΩ. But using FETs to; the input stage, it can be
increased till several hundred MΩ.

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c) Output impedance:
 It is typically few hundred ohms. With the help of negative feedback, it can be reduced to a
very small value like 1 or 2 ohms.
d) Bandwidth:
 The bandwidth of practical op-amp in open loop configuration is very small. By application
of negative feedback, it can be increased to a desired value.
e) Input offset voltage:
 Whenever both the input terminals of the op-amp are grounded, ideally, the output voltage
should be zero.
 However, in this condition, the practical op-amp shows a small non zero output voltage.
 To make this output voltage zero, a small voltage in millivolts is required to be applied to
one of the input terminals.
 Such a voltage makes the output exactly zero. This d.c. voltage, which makes the output
voltage zero, when the other terminal is grounded is called input offset voltage denoted as
Vios.
 The input offset voltage depends on the temperature. The concept of input offset voltage is
shown in the Fig.

 The Vios can be positive or negative hence absolute value of the Vios is mentioned in the
data sheet.
 The smaller the value of Vios better is the matching of the input terminals. The input offset
voltage depends on the temperature.
 Much time voltage to one of the input terminals is applied with the proper polarity so as to
null the output, keeping other input terminal grounded. For ideal op-amp, Vios is zero, hence
practical Op-amp model is generally shown as in the Fig. with the indication of the input
offset voltage. For op-amp 741 IC the input offset voltage is 6 mV.

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 f) Input bias current:
 The average value of the two currents flowing into the op-amp input terminals is called input
bias current and denoted as Ib. It is shown in the Fig.

Mathematically it is expressed as,

|𝐼𝑏1 | + |𝐼𝑏2 |
𝐼𝑏 =
2
Ideally it should be zero while for op-amp 741 IC, maximum value of Ib is 500 nA.
Key Point: Both Iios and Ib are temperature dependent.
g) Input offset current:
 It is seen that the input stage of the op-amp is the dual input differential amplifier and the input
terminals are the base terminals of the two transistors as shown in the Fig.
 Hence the input currents of op-amp are the base currents of the two transistors Q1 and Q2 used
in the input stage. Ideally, Q1 and Q2must be perfectly matched and two base currents must be
equal.
 But practically the two input base currents differ by small amount.

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  The algebraic difference between the currents flowing into the two input terminals of the op-
amp is called input offset current and denoted as Iios.
 Mathematically it is expressed as,
𝐼𝑖𝑜𝑠 = |𝐼𝑏1 | − |𝐼𝑏2 |
Where Ib1 = Current entering into non-inverting input terminal
Ib2 = Current entering into inverting input terminal
 Ideally Iios is zero while for op-amp 741 IC; maximum value of Iios is 200 nA.
 This current is responsible to produce the output though input terminals are grounded.

2. D.C. CHARACTERISTICS OF OP-AMP

3. Explain the following terms in an OP-AMP. (Nov-17)

 Bias current (4)
 Input offset current (4)
 Input offset voltage (4)
 Thermal drift (4)
Or
Explain various DC and AC characteristics of an op-amp. Distinguish between ideal
and practical characteristics. (12)
Or
Discuss in detail about the d.c. characteristics of an op-amp. (Dec – 14) (Nov/ Dec 2019)
(13)

2. D. C. CHARACTERISTICS OF OP-AMP:
 The important d. c. characteristics of op-amp are,
i. Input bias current (Ib)
ii. Input offset current (Iios)
iii. Input offset voltage (Vios)
iv. Thermal drift
2.1 Input bias current:
 The average value of the two currents flowing into the op-amp input terminals is called input
bias current and denoted as Ib. It is shown in the Fig.

 Mathematically it is expressed as,

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 |𝐼𝑏1 | + |𝐼𝑏2 |
𝐼𝑏 =
2
 Ideally it should be zero while for op-amp 741 IC, maximum value of Ib is 500 nA.
 Key Point: Both Iios and Ib are temperature dependent.
 The effect of these parameters is to add the error to the expected d. c. output voltage. These
parameters produce output offset voltage Voos.

2.2 Input offset current:

 It is seen that the input stage of the op-amp is the dual input differential amplifier and the input
terminals are the base terminals of the two transistors as shown in the Fig.
 Hence the input currents of op-amp are the base currents of the two transistors Q1 and Q2 used
in the input stage.
 Ideally, Q1 and Q2 must be perfectly matched and two base currents must be equal. But
practically the two input base currents differ by small amount.

 The algebraic difference between the currents flowing into the two input terminals of the op-
amp is called input offset current and denoted as Iios.
 Mathematically it is expressed as,
𝐼𝑖𝑜𝑠 = |𝐼𝑏1 | − |𝐼𝑏2 |
Where Ib1 = Current entering into non-inverting input terminal
Ib2 = Current entering into inverting input terminal
 Ideally Iios is zero while for op-amp 741 IC, maximum value of Iios is 200 nA. This current is
responsible to produce the output though input terminals are grounded.
2.3 Input offset voltage:
 Whenever both the input terminals of the op-amp are grounded, ideally, the output voltage
should be zero.
 However, in this condition, the practical op-amp shows a small non zero output voltage.
 To make this output voltage zero, a small voltage in millivolts is required to be applied to one
of the input terminals.
 Such a voltage makes the output exactly zero.
 This d.c. voltage, which makes the output voltage zero, when the other terminal is grounded is
called input offset voltage denoted as Vios.
 The input offset voltage depends on the temperature. The concept of input offset voltage is
shown in the Fig.

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 The Vios can be positive or negative hence absolute value of the V ios is mentioned in the data
sheet.
 The smaller the value of Vios better is the matching of the input terminals.
 The input offset voltage depends on the temperature.
 Much time voltage to one of the input terminals is applied with the proper polarity so as to null
the output, keeping other input terminal grounded.
 For ideal op-amp, Vios is zero, hence practical Op-amp model is generally shown as in the Fig.
with the indication of the input offset voltage. For op-amp 741 IC the input offset voltage is 6
mV.

2.4 Thermal Drift:

 The op-amp parameters input offset voltage Vios, input bias current Ib and input offset current
Iios are not constants but vary with the factors:
 Temperature
 Supply voltage changes
 Time
 The effect of change in temperature on the parameters is most severe.
2.5 Effect on Input Offset Voltage:
 The effect of change in temperature on the input offset voltage is defined by a factor called
thermal voltage drift. It is also called as input offset voltage drift.
 The thermal voltage drift is defined as average rate of change of input offset voltage per unit
change in temperature. Mathematically it is given by,
∆Vios
Input offset voltage drift =
∆T
Where, ∆Vios = change in input offset voltage
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 ∆T = change in temperature
 It is expressed in µV/°C. The drift is not constant and it is not uniform over specified operating
temperature range.
 The value of the input offset voltage may increase or decrease with the increasing temperature.
 The Fig. shows the graph of normalized values of input offset voltage versus temperature, for
MC 741 op-amp.

 The input offset voltage is zero at room temperature of 25°C. Referring to the graph shown in
the Fig. the thermal voltage drift values can be obtained.
2.6 Effect on Input Offset and Bias Currents:
 Similar to the input offset voltage, input bias current and input offset current are not constants
but vary with temperature.
 The effect of temperature on input bias current is defined by a factor called input bias current
drift while effect on input offset current is defined by a factor called input offset current
drift.
 The average rate of change of input bias current per unit change in temperature is called input
bias current drift.
 The average rate of input offset current per unit change in temperature is called input offset
current drift.
 Mathematically these drifts are given by,
∆𝐼𝑏
Thermal drift in input bias current = ∆𝑇
∆𝐼𝑖𝑜𝑠
Thermal drift in input offset current = ∆𝑇
 Both the drifts are measured in nA/ C or pA/ C. These parameters vary randomly with
0 0

temperature i.e. they may be positive in one temperature range and negative in another.
 The Fig. shows the graph of normalized values of input bias current and input offset current
versus temperature, for MC1741 op-amp.
 These curves are different for different types of op-amps and are generally provided by the
manufacturers.

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  The input offset current is assumed to be zero at room temperature of 25 0C.
 Practically no information is available about the change in input bias current versus
temperature.
 Infact when compensating resistance Rcomp is used, there is no need to consider the change in
input bias current as a function of change in temperature.

3. A.C. CHARACTERISTICS OF OP-AMP:

 The important a. c. characteristics of op-amp are,

i. Slew Rate
ii. Frequency Response
3.1.Slew Rate:
4. What is slew rate? List the causes of slew rate and explain its significance in applications.
(Nov-15)
 The slew rate is defined as the maximum rate of change of output voltage with time. The slew
rate is specified in V/µsec. Thus,
𝑑𝑉0
𝑆𝑙𝑒𝑤 𝑅𝑎𝑡𝑒 = 𝑆 = |
𝑑𝑡 𝑚𝑎𝑥
 The slew rate is caused due to limited charging rate of the compensating capacitor and current
limiting and saturation of the internal stages of an op-amp, when a high frequency, large
amplitude signal is applied.
𝑑𝑉 1
 The internal capacitor voltage cannot change instantaneously. It is given by 𝑑𝑡𝑐 = 𝐶 . For large
charging rate, the capacitor should be small or charging current should be large.
 Hence the slew rate for the op-amp whose maximum internal capacitor charging current is
known, can be obtained as
𝐼𝑚𝑎𝑥
𝑆=
𝐶
3.1.1 Effect of Slew Rate:
 Consider a circuit using op-amp having unity gain. Thus output is same as input. If the input is
square wave, output has to be square wave.
 But this is observed for certain frequency of input. Due to slew rate of an op-amp, for a
particular input frequency, output gets distorted as shown in the Fig.

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  Then observing such a distorted waveform on CRO the slew rate can be obtained as,
∆𝑉0
𝑆 = 𝑉/𝜇𝑠𝑒𝑐
∆𝑡
 The typical value of S for IC 741 op-amp is 0.5106 V / sec i.e. 0.5 V/µsec. ideally, it should be
infinite.
 Key Point: Higher the value of S better is the performance of op-amp.
3.1.2 Slew Rate Equation:
 Consider unity gain op-amp circuit with purely sinusoidal input. The output must be same as
input.
𝑉𝑠 = 𝑉𝑚 sin 𝜔𝑡
𝑉𝑜 = 𝑉𝑚 sin 𝜔𝑡
𝑑𝑉𝑜
∴ = 𝑉𝑚 (𝜔𝑐𝑜 𝑠 𝜔𝑡)
𝑑𝑡
But
𝑑𝑉0
𝑆𝑙𝑒𝑤 𝑅𝑎𝑡𝑒 = 𝑆 = |
𝑑𝑡 𝑚𝑎𝑥
The third equation has maximum value when cosωt = 1.
∴ 𝑆 = 𝑉𝑚 𝜔 = 2𝜋𝑓𝑉𝑚
∴ 𝑆 = 2𝜋𝑓𝑉𝑚 𝑉/𝜇𝑠𝑒𝑐
This is the slew rate equation.
 For distortion free output, the maximum allowable input frequency fm can be obtained as,
𝑆
∴ 𝑓𝑚 = 𝐻𝑧
2𝜋𝑉𝑚
 This is also called full power bandwidth of the op-amp. The Vm is peak of output waveform.
3.2. Frequency Response of Op-amp:
 Ideally, an op-amp should have an infinite bandwidth. This means the gain of op-amp must
remain same for all the frequencies from zero to infinite.
 Till now we have assumed gain of the op-amp as constant but practically op-amp gain
decreases at higher frequencies. Such a gain reduction with respect to frequency is called roll
off.
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 This happens because gain of the op-amp depends on the frequency and hence mathematically
it is a complex number.
 Its magnitude and the phase angle changes with the frequency.
 The plot showing the variations in magnitude and phase angle of the gain due to the change in
frequency is called frequency response of the op-amp.
 In such plots, to accommodate large range of frequency, it is plotted on a logarithmic scale.
 The gain magnitude can be plotted as a numerical value or may be expressed in decibels. When
the gain in decibels, phase angle in degrees is plotted against logarithmic scale of frequency,
the plot is called Bode plot.
 The manner in which the gain of the op-amp changes with variation in frequency is known as
the magnitude plot and the manner in which the phase shift changes with variation in
frequency is known as the phase angle plot.
 Generally magnitude plot is supplied by the manufacturers. The dependence of gain of the op-
amp on frequency is basically because of presence of capacitive component in the equivalent
circuit of the op-amp.
 As Op-amp uses BJT and FET, which have the junction capacitances which is very small, but
at high frequency, these offer decreased reactance.
 Not only the BJT and FET, but the construction of op-amp also contributes to the presence of
capacitance.
 All the resistors and transistors in op-amp are fabricated on the material called substrate which
acts as an insulator.
 Similarly there are conducting material wires, connecting the various components. The two
conductors separated by an insulator produce capacitive effect.
 Hence overall there exists a capacitive effect in the op-amp. To obtain the frequency response,
consider the high frequency model of the op-amp with a capacitor C at the output, taking into
account the capacitive effect present. It is shown in the Fig.

 Let – jXC be the capacitive reactance due to the capacitor C. From the above Fig. using voltage
divider rule,
𝐴𝑂𝐿 𝑉𝑑
𝑉𝑜 = −𝑗𝑋𝐶 [ ]
𝑅𝑂 −𝑗𝑋𝐶
1 1
Now, −𝑗 = and 𝑋𝐶 =
𝑗 2𝜋𝑓𝐶

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 1
𝑗2𝜋𝑓𝐶
𝑉𝑜 = 1
(𝐴𝑂𝐿 𝑉𝑑 )
𝑅𝑂 + 𝑗2𝜋𝑓𝐶
𝐴𝑂𝐿 𝑉𝑑
∴ 𝑉𝑜 =
1 + 𝑗2𝜋𝑓𝐶𝑅𝑂
 Hence the open loop voltage gain as a function of frequency is,
𝑉𝑜 𝐴𝑂𝐿
𝐴𝑂𝐿 (𝑓) = =
𝑉𝑑 1 + 𝑗2𝜋𝑓𝐶𝑅𝑂
1
Let, 𝑓0 =
2𝜋𝑅𝑂 𝐶
𝐴𝑂𝐿
𝐴𝑂𝐿 (𝑓) = 𝑓
1 + 𝑗 (𝑓 )
0
Where, 𝐴𝑂𝐿 (𝑓) = Open loop gain as a function of frequency
𝐴𝑂𝐿 = Gain of op-amp at 0 Hz i.e. d.c.
f = Operating frequency
f0 = Break frequency or cut off frequency of op-amp
 For a given op-amp and selected value of C, the frequency f0 is constant. The above equation
can be written in polar form as,
𝐴𝑂𝐿
|𝐴𝑂𝐿 (𝑓)| =
2
√1 + ( 𝑓 )
𝑓 0
𝑓
< 𝐴𝑂𝐿 (𝑓) = ∅ (𝑓) = − tan−1 ( )
𝑓0
At f = 0 Hz, the magnitude is AOL, while ∅ (𝑓) = 0 .
0

 For IC 741 op-amp, f0 = 5 Hz and the open loop gain 200,000, we can calculate gain and phase
shifts at various frequencies as given below:
Frequency, f (Hz) 𝑨𝑶𝑳 𝒇
|𝑨𝑶𝑳 (𝒇)| = 20 log (dB) ∅ (𝒇) = − 𝐭𝐚𝐧−𝟏 ( ) (degrees)
𝟐 𝒇𝟎
√𝟏+ ( 𝒇 )
𝒇𝟎

0 106.02 dB 00
5 103.01dB - 450
10 99.03dB - 63.430
100 79.98dB -87.130
1000 60.00dB -89.710
10010 3 20.00dB -89.990
1106 0dB -89.9990
 As the frequency increases till f0, the gain is almost constant but after f0, the gain reduces with
a rate of -20 dB/ decade.
 The maximum possible phase shift is -90°.Hence the frequency response is shown as in the Fig.

24
  The following observations can be made from the frequency response of an op-amp:
i) The open loop gain AOL is almost constant from 0 Hz to the break frequency f0.
ii) At f = f0, the gain is 3 dB down from its value at 0 Hz. Hence the frequency f0 is also
called as -3 dB frequency. It is also known as corner frequency.
iii) After f = f0, the gain AOL (f) decreases at a rate of 20 dB / decade or 6 dB / octave. A
decade is 10 times change in frequency while octave is 2 times change in frequency. As gain
decreases, slope of the magnitude plot is -20 dB/ decade or -6 dB/ octave, after f = f0.
iv) At a certain frequency, the gain reduces to 0 dB. This means 20 log |AOL (f)| is 0 dB
i.e. |AOL (f)| = 1. Such a frequency is called gain cross-over frequency or unity gain bandwidth
(UGB). It is also called closed loop bandwidth. UGB is the gain bandwidth product only if an op-
amp has a single break frequency, before AOL (f) dB is zero.
 For an op-amp with single break frequency f0, after f0 the gain bandwidth product is equal to
UGB.
UGB = AOL f0
 The op-amp for which there is only one change in the slope of the magnitude plot is called as
single break frequency op-amp.
 For a single break frequency, we can write,
UGB = Afff
Where, Af = Closed loop voltage gain
ff = Bandwidth with feedback
v) The phase angle of an op-amp with a single break frequency varies between 00 and
900. The maximum possible phase shift is -900, i.e. output voltage lags input voltage by 900 when
phase shift is maximum.
vi) At a corner frequency f = f0, the phase shift is -450.

25
 4. DIFFERENTIAL AMPLIFIER
5. Draw the circuit of differential amplifier and derive the expression for output voltage in
it. (8)
4. DIFFERENTIAL AMPLIFIER:
 The differential amplifier amplifies the difference between two input voltage signals. Hence it
is also called difference amplifier. Consider an ideal differential amplifier shown in the Fig.

 V1 and V2 are the two input signals while V0 is the single ended output. Each signal is
measured with respect to the ground.
 In an ideal differential amplifier, the output voltage V0 is proportional to the difference
between the two input signals. Hence we can write,
𝑉0 ∝ (𝑉1 − 𝑉2 )
4.1 Features of Differential Amplifier:
The various features of a differential amplifier are:
1. High differential voltage gain
2. Low common mode gain
3. High CMRR
4. Two input terminals
5. High input impedance
6. Large bandwidth
7. Low offset voltages and currents
8. Low output impedance
4.2 Transistorised Differential Amplifier:
 The transistorised differential amplifier basically uses the emitter biased circuits which are
identical in characteristics.
 Such two identical emitter biased circuits are shown in the Fig.The two transistors Q1 and Q2
have exactly matched characteristics.
 The two collector resistances RC1 and RC2 are equal while the two emitter resistances R E1 and
RE2 are also equal. Thus, RC1 = RC2 and RE1 = RE2
 The magnitudes of + VCC and – VEE are also same. The differential amplifier can be obtained
by using such two emitter biased circuits. This is achieved by connecting emitter E1 of Q1 to
the emitter E2 of Q2.
 Due to this, RE1 appears in parallel with RE2 and the combination can be replaced by a single
resistance denoted as RE.
 The base Bl of Q1 is connected to the input 1 which is VS1 while the base B2 of Q2 is connected
to the input 2 which is VS2.
26
 The supply voltages are measured with respect to ground. The balanced output is taken
between the collector C1 of Q1 and the collector C2 of Q2.
 Such an amplifier is called emitter coupled differential amplifier. The two collector resistances
are same hence can be denoted as RC.
 The output can be taken between two collectors or in between one of the two collectors and the
ground.
 When the output is taken between the two collectors, none of them is grounded then it is called
balanced output, double ended output or floating output.
 When the output is taken between any of the collectors and the ground, it is called unbalanced
output or single ended output.
 The complete circuit diagram of such a basic dual input, balanced output differential amplifier
is shown in the Fig.

 As the output is taken between two output terminals, none of them is grounded, it is called
balanced output differential amplifier.
 Let us study the circuit operation in the two modes namely:
 Differential mode operation
 Common mode operation.

27
4.3 Modes of operation:
4.3.1 Differential Mode Operation:
 In the differential mode, the two input signals are different from each other.
 Consider the two input signals which are same in magnitude but 180° out of phase.
 These signals, with opposite phase can be obtained from the center tap transformer.
 The circuit used in differential mode operation is shown in the Fig.
 Assume that the sine wave on the base of Q1 is positive going while on the base of Q2 it is
negative going.
 With a positive going signal on the base of Q1, an amplified negative going signal develops on
the collector of Q1.
 Due to positive going signal, current through RE also increases and hence a positive going wave
is developed across RE.

 Due to negative going signal on the base of Q2, an amplified positive going signal develops on
the collector of Q2.
 And a negative going signal develops across RE, because 0f emitter follower action of Q2.
 So signal voltages across RE, due to the effect of Q1 and Q2 are equal in magnitude and 180°
out of phase, due to matched pair of transistors.
 Hence these two signals cancel each other and there is no signal across the emitter resistance.
 Hence there is no a.c. signal current flowing through the emitter resistance. Hence RE in this
case does not introduce negative feedback.
 While V0 is the output taken across collector of Q1 and collector of Q2, the two outputs on
collector 1 and 2 are equal in magnitude but opposite in polarity.
 And V0 is the difference between these two signals, e.g. +10 - (-10) = + 20.
Key Point: Hence the difference output V0 is twice as large as the signal voltage from either collector
to ground.
4.3.2 Common Mode Operation:
 In this mode, the signals applied to the base of Q1 and Q2 are derived from the same source.

28
  So the two signals are equal in magnitude as well as in phase. The circuit diagram is shown in
the Fig.
 In-phase signal voltages at the bases of Q1 and Q2 causes an in-phase signal voltage to appear
across RE, which are added together.
 Hence RE carries a signal current and provides a negative feedback. This feedback reduces the
common mode gain of differential amplifier.

 While the two signals causes in phase signal voltages of equal magnitude to appear across the
two collectors of Q1 and Q2, the output voltage is the difference between the two collector
voltages, which are equal and also same in phase, e.g. (10) – (10) = 0.
 Thus the difference output V0 is almost zero, negligibly small. Ideally it should be zero.

4.4 D.C. ANALYSIS OF DIFFERENTIAL AMPLIFIER:

6. Draw the circuit of a symmetrical emitter coupled differential amplifier and derive for
CMRR. (Nov-17) (16)
(or)
Explain the working principles of emitter coupled differential amplifier. (May-18) (7)

 The d.c. analysis means to obtain the operating point values i.e. I CQ and VCEQ for the transistors
used.
 The supply voltages are d.c. while the input signals are a.c., so d.c. equivalent circuit can be
obtained simply by reducing the input a.c. signals to zero.
 The d.c. equivalent circuit thus obtained is shown in the figure below.
 Assuming RS1 = RS2, the source resistance is simply denoted by R S.
 The transistors Q1 and Q2 are matched transistors and hence for such a matched pair we can
assume:
 Both the transistors have the same characteristics.
 RE1 = RE2 hence RE = RE1║ RE2.
 RC1 = RC2 hence denoted as RC.
 │VCC│ = │VEE| and both are measured with respect to ground.

29
  As the two transistors are matched and circuit is symmetrical, it is enough to find out operating
point ICQ and VCEQ, for any one of the two transistors.
 The same is applicable for the other transistor.
 Applying KVL to base-emitter loop of the transistor Q1,
−𝐼𝐵 𝑅𝑆 − 𝑉𝐵𝐸 − 2𝐼𝐸 𝑅𝐸 + 𝑉𝐸𝐸 = 0 (1)
But, IC = βIB and IC ≈ IE
𝐼𝐸
∴ 𝐼𝐵 = (2)
𝛽
Substituting I equation (1), we get,
−𝐼𝐸 𝑅𝑆
− 𝑉𝐵𝐸 − 2𝐼𝐸 𝑅𝐸 + 𝑉𝐸𝐸 = 0 (3)
𝛽
−𝑅𝑆
∴ 𝐼𝐸 [ − 2𝑅𝐸 ] + 𝑉𝐸𝐸 − 𝑉𝐵𝐸 = 0 (4)
𝛽
𝑉𝐸𝐸 − 𝑉𝐵𝐸
∴ 𝐼𝐸 = 𝑅𝑆 (5)
+ 2𝑅 𝐸
𝛽
where, VBE = 0.6 to 0.7 V for silicon
= 0.2 V for germanium
 In practice, generally RS / β << 2RE
𝑉𝐸𝐸 − 𝑉𝐵𝐸
∴ 𝐼𝐸 = (6)
2𝑅𝐸
 From the equation (6), we can observe that,
 RE determines the emitter current of Q1 and Q2 for the known value of VEE.
 The emitter current through Q1 and Q2 is independent of collector resistance RC.
 Now let us determine VCE. As IE is known and IE ≈ IC, we can determine the collector voltage
of Q1 as
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 (7)
 Neglecting the drop across RS, we can say that the voltage at the emitter of Q1 is approximately
equal to -VBE. Hence the collector to emitter voltage is
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 − (−𝑉𝐵𝐸 )

30
 𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 + 𝑉𝐵𝐸 (8)
 Hence IE = IC = ICQ while VCE = VCEQ for given values of VCC and VEE.
 In the equation (6), the sign of VEE is already considered to be negative, while deriving it.
 Hence while using this equation to solve the problem, only the magnitude of V EE should be
used and negative sign of VEE should not be used again.
 Thus for both the transistors, we can determine operating point values, using equations (6) and
(8).

4.5 A.C. ANALYSIS USING h-PARAMETERS:

 In the A.C. analysis, we will calculate the differential gain Ad, common mode gain Ac, of the
differential amplifier circuit, using the h-parameters.
4.5.1 Differential mode Gain (Ad):
 The a.c. equivalent circuit of a differential amplifier is given as follows:

From the figure, 𝑣01 = −𝑖𝐶 𝑅𝐶 = −ℎ𝑓𝑒 𝑖𝑏 𝑅𝐶

𝑣𝑑
And = 𝑖𝑏 ℎ𝑖𝑒
2
Therefore, the differential mode gain, ADM is given by
𝑣01 1 ℎ𝑓𝑒
𝐴𝑑 = =− 𝑅 (𝑆𝑖𝑛𝑔𝑙𝑒 𝑒𝑛𝑑𝑒𝑑 𝑜𝑢𝑡𝑝𝑢𝑡)
𝑣𝑑 2 ℎ𝑖𝑒 𝐶
Similarly, we may write,
𝑣02 1 ℎ𝑓𝑒
𝐴𝑑 = = 𝑅 (𝑆𝑖𝑛𝑔𝑙𝑒 𝑒𝑛𝑑𝑒𝑑 𝑜𝑢𝑡𝑝𝑢𝑡)
𝑣𝑑 2 ℎ𝑖𝑒 𝐶
The output is taken differentially between the two collectors, then
𝑣01 − 𝑣02 ℎ𝑓𝑒
𝐴𝑑 = =− 𝑅 (𝑑𝑖𝑓𝑓𝑒𝑟𝑒𝑛𝑡𝑖𝑎𝑙 𝑜𝑢𝑡𝑝𝑢𝑡)
𝑣𝑑 ℎ𝑖𝑒 𝐶
In the above analysis, the source resistance RS has not been taken into account.
4.5.2 Common mode Gain (Ac):
 Now consider the case when v1 and v2 both are increased by an incremental voltage vc.
 The differential signal vd now is zero and common-mode signal is vc.Both the collector currents
iC1 and iC2 will increase by an incremental current iC.
 The current through RE now increases by 2iC.

31
  The voltage, VE at emitter node is now 2iCRE and no longer constant. In order to draw the
common mode half circuit, replace resistance RE by 2RE as shown in figure above.
 The common mode gain, Ac, using h-parameter model can be easily computed as,
𝑣01 −ℎ𝑓𝑒 𝑅𝐶
𝐴𝑐 = =
𝑣𝑐 ℎ𝑖𝑒 + 2(1 + ℎ𝑓𝑒 )𝑅𝐸

 It can be seen that, if the output is taken differentially, then the output voltage v01−v02 will be
zero and the common mode gain will be zero.
 However, if the output is taken single ended, the common mode gain will be finite.

4.5.3 CMRR:

7. How the CMRR increased using constant current source? (May-18) (6)
 CMRR means Common Mode Rejection Ratio.
 The ability of the differential amplifier to reject common mode signals is expressed by the ratio
of differential gain to common mode gain which is called its Common Mode Rejection Ratio
(CMRR).
 It is defined as the ratio of differential voltage gain Ad to common mode voltage gain Ac.
𝐴𝑑
𝐶𝑀𝑅𝑅 = 𝜌 = | |
𝐴𝑐
 Ideally the common mode voltage gain is zero and hence the ideal value of CMRR is infinite.
 For a differential input, differential output, we get,
ℎ
− ℎ𝑓𝑒 𝑅𝐶
𝑖𝑒
𝐶𝑀𝑅𝑅 ≅ −ℎ𝑓𝑒 𝑅𝐶
ℎ𝑖𝑒 +2(1+ℎ𝑓𝑒 )𝑅𝐸

ℎ𝑖𝑒 + 2(1 + ℎ𝑓𝑒 )𝑅𝐸

𝐶𝑀𝑅𝑅 =
ℎ𝑖𝑒
2(1 + ℎ𝑓𝑒 )𝑅𝐸
𝐶𝑀𝑅𝑅 = 1 +
ℎ𝑖𝑒
2(1 + ℎ𝑓𝑒 )𝑅𝐸
𝐶𝑀𝑅𝑅 ≅
ℎ𝑖𝑒

32
 5. FREQUENCY COMPENSATION:
8. Explain the frequency compensation techniques of OP-AMP. (Dec – 12) (16)
(or)
Explain in detail about various methods of frequency compensation used in operational
amplifiers. (May-15, 17) (Dec-15) (8)

 In order to obtain larger bandwidth and low voltage gain, compensation is required. There are
mainly two compensations required namely:
 External Compensation
 Internal Compensation
5.1 External Compensation Technique:
 As mentioned earlier, the compensating network is connected to the system externally to alter
the response as per the requirement.
 There are three such external compensation techniques used in practice.
1) Dominant pole compensation
2) Pole-Zero compensation
3) Feed-forward compensation
5.1.1 Dominant Pole Compensation:
 Consider an op-amp with three break frequencies and its loop gain is say A.
𝐴𝑂𝐿
𝐴= 𝑓 𝑓 𝑓
(1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 )
1 2 3

 In this loop gain, the dominant pole is introduced by adding a compensating network. Such a
network is nothing but a simple R-C network as shown in the Fig.

 The dominant pole means the pole with magnitude much smaller than the existing poles.
 Hence the break frequency of the compensating network is the smallest compared to the
existing break frequencies.
 The transfer function of the compensating network can be obtained as:
A1 = Transfer function of compensating network
𝑉𝑜
𝐴1 = ′
𝑉𝑜
By the voltage divider rule applied to the network,
𝑉𝑜 −𝑗𝑋𝐶
𝐴1 = ′ =
𝑉𝑜 𝑅 − 𝑗𝑋𝐶

33
 𝑗
− 2𝜋𝑓𝐶 1
= 𝑗
= 𝑅
𝑅 − 2𝜋𝑓𝐶 𝑗 +1
(− )
2𝜋𝑓𝐶
1
As = 𝑗, we can write
−𝑗
1
∴ 𝐴1 = 𝑓
1 + 𝑗 (𝑓 )
𝑑
Where, fd = break frequency of the compensating network
 Hence the compensated transfer function becomes,
𝐴′ = 𝐴𝐴1
𝐴𝑂𝐿
𝐴′ = 𝑓 𝑓 𝑓 𝑓
(1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 )
𝑑 1 2 3
Where, fd< f1 < f2 < f3.
 The compensated and uncompensated magnitude plots are shown in Fig.

 It can be observed from the plot that 3 dB down bandwidth for non-compensated system is
BW1 while for compensated it becomes BW2. There is drastic reduction in the bandwidth.
Advantages:
 As the noise frequency components are outside the smaller bandwidth, the noise immunity of
the system improves.
 Adjusting value of fd, adequate phase margin and the stability of the system is assured.
Disadvantage:
 The only disadvantage of the method is that the bandwidth reduces drastically, as mentioned
earlier.
5.1.2 Pole Zero Compensation:
 Consider the same op-amp described by the open loop gain A with three break frequencies as
𝐴𝑂𝐿
𝐴= 𝑓 𝑓 𝑓
(1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 )
1 2 3

 In this method, the transfer function A is modified by adding a pole and a zero with the help of
compensating network.

34
 The zero added is at higher frequency while a pole is at lower frequency. Such a compensating
network is shown in the Fig.

Let the transfer function of the compensating network be A1:

𝑉𝑜
𝐴1 = ′
𝑉𝑜
By the voltage divider rule,
𝑍2
𝐴1 =
𝑍1 + 𝑍2
Now, 𝑍2 = 𝑅2 − 𝑗𝑋𝐶2 and 𝑍1 = 𝑅1
𝑅2
𝑗 +1
𝑅2 − 𝑗𝑋𝐶2 𝑅2 − 2𝜋𝑓𝐶 [
−𝑗
]
2 2𝜋𝑓𝐶2
∴ 𝐴1 = = 𝑗
= 𝑅1 +𝑅2
𝑅1 + 𝑅2 − 𝑗𝑋𝐶2 𝑅1 + 𝑅2 − 2𝜋𝑓𝐶 −𝑗 +1
2 [ ]
2𝜋𝑓𝐶2
1
Now, −𝑗 = 𝑗
1 + 𝑗2𝜋𝑓𝑅2 𝐶2
∴ 𝐴1 =
1 + 𝑗2𝜋𝑓(𝑅1 + 𝑅2 )𝐶2
1 1
Now let𝑓1 = and 𝑓0 =
𝑗2𝜋𝑅2 𝐶2 𝑗2𝜋(𝑅1 +𝑅2 )𝐶2
𝑓
1 + 𝑗 (𝑓 )
1
∴ 𝐴1 = 𝑓
1+𝑗( )
𝑓0
 The values of R1, R2 and C2 are so selected that the break frequency for the zero matches with
the first corner frequency f1 of the uncompensated system.
 While the pole of the compensating network at fo is selected in such a way that the
compensated transfer function A' passes through 0 dB at the second corner frequency f2 of the
uncompensated system.
 The resultant loop gain becomes,
𝐴′ = 𝐴𝐴1
𝑓
𝐴𝑂𝐿 (1 + 𝑗 𝑓 )
1
𝐴1 = 𝑓 𝑓 𝑓 𝑓
(1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 ) (1 + 𝑗 𝑓 )
0 1 2 3
Where, 0 <f0 < f1 < f2 < f3.
 As compared to the dominant pole compensation there is improvement in the bandwidth, equal
to f2 - f1. This is the additional advantage of pole-zero compensation technique.

35
  The value of compensation capacitor is generally very large.
 Hence it is not possible to build such capacitor into standard integrated circuits.
 Generally the connections are brought out from IC to connect the compensation elements
externally.
5.2 Internal Compensation Technique:
 Recently in op-amps like IC 741, the compensation is provided internally, which is generally
built in lag compensation.
 A capacitor ranging from 10 to 30 pF is fabricated between input and output stage to achieve
the necessary compensation.
 This type of compensation is called Miller effect compensation. Such op-amps are called
compensated op-amps.
5.2.1 Miller Effect Compensation:
 The main drawback of dominant pole compensation is the reduction in the bandwidth.
 Similarly the value of capacitance required in this method is very large and fabricating such
large capacitance on the chip is not practicable.
 These drawbacks are avoided by using Miller effect compensation, using the Miller effect.
 In dominant pole compensation, a capacitor is connected to ground from the output terminal
but in Miller effect compensation it is connected in the feedback path of the Darlington pair
used in the output stage of op-amp.
 This is shown in the Fig.

 The CC is the compensating capacitor, Ri is the input resistance and R0 is the output resistance
of the Darlington stage. The gain of the Darlington stage is given by,
36
 𝑎2 = −𝐺𝑚𝑐 𝑅0
Where Gmc = Trans-conductance of the stage
 Looking through the input terminal CC appears as the Miller capacitance CM and from the
results of Miller effect we can write,
𝑍𝐶𝐶
𝑍𝐶𝑀 =
1 + 𝑎2
1 1
Where 𝑍𝐶𝑀 = 𝑗𝜔𝐶 and 𝑍𝐶𝐶 =
𝑀 𝑗𝜔𝐶𝐶
1
1 𝑗𝜔𝐶𝐶
∴ =
𝑗𝜔𝐶𝑀 1 + 𝑎2
∴ 𝐶𝑀 = (1 + 𝑎2 )𝐶𝐶
 Thus effectively CC gets multiplied by (1 + a2) where a2 is the gain of the stage which is large,
as viewed through the input terminals.
 Thus practically small CC values can be used, which is helpful from monolithic fabrication
point of view.
 This Miller equivalent capacitance CM forms a low pass RC section with input resistance Ri
whose corner frequency is given by,
1
𝑓𝑑 =
2𝜋𝐶𝑀 𝑅𝑖
 The uncompensated and compensated magnitude plots are shown in the Fig.

 In addition to the multiplying the capacitance, Miller effect has another advantage. It causes
rearrangement of original poles and cause Pole splitting.
 This means due to Miller effect compensation, f1 gets lowered while f2 gets raised. Thus poles
get diverged.
 This increases the bandwidth compared to dominant pole compensation.
 Such compensated op-amps usually have single break frequency and are inherently stable in
nature irrespective of value of closed loop gain.
 External compensating network is not required for such op-amps.
 Some internally compensated op-amps are Fairchild’s µA 741, National semiconductor’s LM
107, LM 741, LM 112 and Motorola’s MC 1858.

37
 6. BASIC APPLICATIONS OF OP-AMP
6.1 INVERTING AND NON- INVERTING AMPLIFIERS

9. Explain the Significance of virtual ground in basic inverting OPAMP. How would you explain
its existence?
(or)
Draw the inverting amplifier circuit of an op- amp in closed loop configuration. Obtain the
expression for closed loop gain. (May-18) (7)
(or)
Explain with neat circuit expression about the working of inverting Amplifier. [Apr/May 2019]
(or)
Illustrate with neat diagram, the working of inverting and Non- inverting amplifiers by using
OP- AMPs. Develop the expressions for output voltages. (Nov/Dec 2019)

6.1.1 INVERTING AMPLIFIER:

 This is perhaps the most widely used of all the op-amp circuits. The circuit is shown in Fig.

 The output voltage v0 is fed back to the inverting input terminal through the Rf– R1 network
where Rf is the feedback resistor.
 Input signal vi is applied to the inverting input terminal through R1 and non-inverting input
terminal of op-amp is grounded.
 Analysis: For simplicity, assume an ideal op-amp. As vd = 0, node ‘a’ is at ground potential
and the current i1 through R1 is
𝑣𝑖
𝑖1 =  (1)
𝑅1
 Also since op-amp draws no current, all the current flowing through R1 must flow through Rf.
The output voltage,
𝑅𝑓
𝑣0 = −𝑖1 𝑅𝑓 = −𝑣𝑖  (2)
𝑅1
 Hence, the gain of the inverting amplifier (also referred as closed loop gain) is,
𝑣0 𝑅𝑓
𝐴𝐶𝐿 = = −  (3)
𝑣𝑖 𝑅1
 Alternatively, the nodal equation at the node ‘a’ in Fig. is
𝑣𝑎 − 𝑣𝑖 𝑣𝑎 − 𝑣0
+ = 0
𝑅1 𝑅𝑓
38
 Where va is the voltage at node ‘a’.
 Since node ‘a’ is at virtual ground va = 0. Therefore, we get,
𝑣0 𝑅𝑓
𝐴𝐶𝐿 = = −
𝑣𝑖 𝑅1
 The negative sign indicates a phase shift of 1800 between vi and v0. Also since inverting
terminal is at virtual ground, the effective input impedance is R1.
 The value of R1 should be kept fairly large to avoid loading effect.
 This however, limits the gain that can be obtained from this circuit.
 A load resistor RL is usually put at the output in actual practice otherwise, the input impedance
of the measuring device such as oscilloscope or DVM acts as the load.
 If, however, resistances R1 and Rf in Fig. are replaced by impedances Z1 and Zf respectively,
then the voltage gain, ACL will be
𝑍𝑓
𝐴𝐶𝐿 =  (4)
𝑍𝑖
 This expression for the voltage gain will be used in op-amp application, such as integrator,
differentiator etc.
6.1.1.1 Practical Inverting Amplifier:
 The gain of the inverting amplifier given above is valid only if the op-amp is an ideal one.
 For a practical op-amp, the expression for the closed loop voltage gain should be calculated
using the low frequency model of the followingFig.

 The equivalent circuit of a practical inverting amplifier is shown in Fig. below,

 This circuit can be simplified by replacing the signal source vi and resistors R1 and Ri by
Thevenin’s equivalent as shown in Fig. below, which is analysed to calculate the exact
expression for closed loop gain, AOL and input impedance Rif.

39
  The input impedance Ri of an op-amp is usually much greater than R1, so one may assume, veq≈
vi and Req≈ R1.
From the output loop in Fig
𝑣0 = 𝑖𝑅0 + 𝐴𝑂𝐿 𝑣𝑑  (5)
Also
𝑣𝑑 + 𝑖𝑅𝑓 + 𝑣0 = 0  (6)
 Putting the value of vd from equation (5) to equation (6) and simplifying,
𝑣0 (1 + 𝐴𝑂𝐿 ) = 𝑖(𝑅0 − 𝐴𝑂𝐿 𝑅𝑓 )  (7)
 Also the KVL loop equation gives,
𝑣𝑖 = 𝑖(𝑅1 + 𝑅𝑓 ) + 𝑣0  (8)
 Putting the value of I from equation (7) in equation (8) and solving for closed loop gain 𝐴𝐶𝐿 =
𝑣0
, gives
𝑣 𝑖
𝑣0 𝑅0 − 𝐴𝑂𝐿 𝑅𝑓
𝐴𝐶𝐿 = =  (9)
𝑣𝑖 𝑅0 + 𝑅𝑓 + 𝑅1 (1 + 𝐴𝑂𝐿 )
 It can be seen from equation (9) that if AOL>> 1 and AOL R1>> R0 + Rf
𝑅𝑓
𝐴𝐶𝐿 ≈
𝑅1
6.1.2 NON- INVERTING AMPLIFIER:
 If the signal is applied to the non-inverting input terminal and feedback is given as shown in
Fig., the circuit amplifies without inverting the input signal.
 Such a circuit is called non-inverting amplifier.
 It may be noted that it is also a negative feed-back system as output is being fed back to the
inverting input terminal.

40
  As the differential voltage vd at the input terminal of op-amp is zero, the voltage at node ‘a’ in
Fig. is vi, same as the input voltage applied to non-inverting input terminal.
 Now Rf and R1 forms a potential divider. Hence
𝑣0
𝑣𝑖 = ∙ 𝑅  (1)
𝑅1 + 𝑅𝑓 1
 As no current flows into the op-amp,
𝑣0 𝑅1 + 𝑅𝑓 𝑅𝑓
= = 1 +  (2)
𝑣𝑖 𝑅1 𝑅1
 Thus, for a non- inverting amplifier, the voltage gain is,
𝑣0 𝑅𝑓
𝐴𝐶𝐿 = = 1 +  (3)
𝑣𝑖 𝑅1
 The gain can be adjusted to unity or more, by proper selection of resistors R f and R1.
 Compared to the inverting amplifier, the input resistance of the non-inverting amplifier is
extremely large (= ∞) as the op-amp draws negligible current from the signal source.
6.1.2.1 Practical Non-Inverting Amplifier:

 The analysis of a practical non-inverting amplifier can be performed by using the equivalent
circuit shown in Fig. Writing KCL at the input node,
(𝑣𝑖 − 𝑣𝑑 )𝑌1 + 𝑣𝑑 𝑌𝑖 + (𝑣𝑖 − 𝑣𝑑 − 𝑣0 )𝑌𝑓 = 0
or
−(𝑌1 + 𝑌𝑖 + 𝑌𝑓 )𝑣𝑑 + (𝑌1 + 𝑌𝑓 )𝑣𝑖 = 𝑌𝑓 𝑣0  (4)
 Similarly at output node, KCL gives
(𝑣𝑖 − 𝑣𝑑 − 𝑣0 )𝑌𝑓 + (𝐴𝑂𝐿 𝑣𝑑 − 𝑣0 )𝑌0 = 0
∴ −(𝑌𝑓 − 𝐴𝑂𝐿 𝑌0 )𝑣𝑑 + 𝑌𝑓 𝑣𝑖 = (𝑌𝑓 + 𝑌0 )𝑣0  (5)
 Now solving equations (4) and (5) for v0 / vi, we get
𝑣0 𝐴𝑂𝐿 𝑌0 (𝑌1 + 𝑌𝑓 ) + 𝑌𝑖 𝑌𝑓
𝐴𝐶𝐿 = =  (6)
𝑣𝑖 (𝐴𝑂𝐿 + 1)𝑌0 𝑌𝑓 + (𝑌1 + 𝑌𝑖 )(𝑌𝑓 + 𝑌0 )
Where, all the admittances have been taken for simplicity.
 If AOL ∞, equation(6) reduces to
𝐴𝑂𝐿 𝑌0 (𝑌1 + 𝑌𝑓 ) (𝑌1 + 𝑌𝑓 ) 𝑌1
𝐴𝐶𝐿 = = = 1+
𝐴𝑂𝐿 𝑌0 𝑌𝑓 𝑌𝑓 𝑌𝑓

41
 𝑅1
∴ 𝐴𝐶𝐿 = 1 +
𝑅𝑓
Which is, the same expression as in equation (3).
PROBLEM:
10. For a given non-inverting amplifier shown in figure below. Determine (i) Av (ii) V0 (iii) IL (iv)
I0 [Apr/May 2019]

(i) IL = Vi / R
= 0.6/10KΩ
= 0.6 / 10 * 103 Ω
=0.00006A

(ii) I0= Vi / RL
= 0.6/2KΩ
= 0.0003A

(iii) V0=(i+Rf/R1) . Vin

= (1+20 KΩ/10 KΩ). 0.6V
=(1+2).0.6V
= 3(0.6)
=1.8V

(iv) Av = V0 / Vin
=1.8V/0.6V
=3V

42
11. For a non- inverting amplifier shown in fig, R1= 1KΩ, Rf= 10 KΩ. Calculate i) the maximum
output offset voltage (Vos= 10mv) and bias current (IB= 300nA) and offset current Ios = 50nA. ii)
Calcuate the value of Rcomp need to reduce the effect of IB. iii) Calculate the maximum output
offset voltage if Rcomp is connected in the circuit. Nov/Dec 2019.

Solution:
Given Data:
R1= 1KΩ
Rf= 10 KΩ
Output offset voltage (Vos= 10mv)
Bias current (IB= 300nA)
Offset current Ios = 50nA
(i) If Rcomp is connected,
Max. Output offset voltage VOT = (1+( Rf/ R1)) Vos + Rf. Ios
VOT = 511 µV
(ii) Rcomp = R1 || Rf = (R1 x Rf) / (R1 + Rf)
= (1x 10) MΩ / (1+ 10) KΩ
= 10000000/ 11000
= 10000/ 11
= 0.9 KΩ

(iii) If Rcomp is not connected,

VOT = (1+( Rf/ R1)) Vios + Rf. IB
= (1+ 10 KΩ).10mV + (10 KΩ. 300nA)
= 101 + 3000 µV
= 3101 µV

6.2 SUMMERS

12. With the help of circuit diagram show how an OP-AMP is used as a summer. (8)
6.2 SUMMING AMPLIFIER:
 Op-amp may be used to design a circuit whose output is the sum of several input signals. Such
a circuit is called a summing amplifier or a summer.
6.2.1 Inverting Summing Amplifier:
 A typical summing amplifier with three input voltages V1, V2 and V3, three input resistors R1,
R2, R3 and a feedback resistor Rf is shown in Fig.
43
  The following analysis is carried out assuming that the op-amp is an ideal one, that is, AOL = ∞
and Ri = ∞.
 Since the input bias current is assumed to be zero, there is no voltage drop across the resistor
Rcomp and hence the non-inverting input terminal is at ground potential.
 The voltage at node ‘a’ is zero as the non-inverting input terminal is grounded. The nodal
equation by KCL at node ‘a’ is,
𝑉1 𝑉2 𝑉3 𝑉0
+ + + =0
𝑅1 𝑅2 𝑅3 𝑅𝑓
or
𝑅𝑓 𝑅𝑓 𝑅𝑓
𝑉0 = 𝑉1 + 𝑉2 + 𝑉3
𝑅1 𝑅2 𝑅3
 Thus the output is an inverted, weighted sum of the inputs. In the special case, when R 1 = R2 =
R3 =Rf, we have
 In which case, the output V0 is the inverted sum of the input signals. We may also set, R1 = R2
= R3 = 3Rf, in which case,
𝑉1 + 𝑉2 + 𝑉3
𝑉0 = − ( )
3
 Thus the output is the average of the input signals (inverted). In a practical circuit, input bias
current compensating resistor Rcomp should be provided. To find Rcomp, make all inputs V1 = V2
= V3 = 0.
 So the effective input resistance Ri= R1║R2║R3. Therefore, Rcomp= Ri║Rf = R1║R2║R3 ║Rf.
6.2.2 Non-Inverting Summing Amplifier:
 A summer that gives a non-inverted sum is the non-inverting summing amplifier as shown in
Fig.

44
  Let the voltage at the (–) input terminal be Va. The voltage at (+) input terminal will also be Va.
The nodal equation at node ‘a’ is given by,
𝑉1 − 𝑉𝑎 𝑉2 − 𝑉𝑎 𝑉3 − 𝑉𝑎
+ + =0
𝑅1 𝑅2 𝑅3
𝑉1 𝑉 𝑉
+ 𝑅2 + 𝑅3
𝑅1 2 3
𝑉𝑎 = 1 1 1
+𝑅 +𝑅
𝑅1 2 3

 The op-amp and two resistors Rf and R constitute a non-inverting amplifier with,
𝑅𝑓
𝑉0 = (1 + ) ∙ 𝑉𝑎
𝑅1
 Therefore, the output voltage is,
1 𝑉 𝑉 𝑉
𝑅𝑓 + 𝑅2 + 𝑅3
𝑅1 2 3
𝑉0 = (1 + ) ∙ ( 1 1 1)
𝑅1 + + 𝑅1 𝑅2 𝑅3
 Which, is a non-inverted weighted sum of inputs.
Let, R1 = R2 = R3 = Rf/2, then,
𝑉0 = 𝑉1 + 𝑉2 + 𝑉3 .

6.3 DIFFERENTIATOR

13. With neat circuit diagram explain the operation of a OP-AMP differentiator and derive and
expression for the output of a practical differentiator. (16)
Or
Explain the functions of op-amp as a differentiator. Draw the waveforms. (Dec – 14) (4)
(or)
What are the limitations of ordinary op-amp differentiator? Draw the circuit of practical
amplifier which eliminates the limitations. (Nov-15) (8)
6.3 DIFFERENTIATOR:
 One of the simplest of the op-amp circuits that contain capacitor is the differentiating amplifier,
or differentiator.
 As the name suggests, the circuit performs the mathematical operation of differentiation, that
is, the output waveform is the derivative of input waveform.
 A differentiator circuit is shown in Fig.

6.3.1 Analysis:
 The node N is at virtual ground potential i.e., vn = 0. The current iC through the capacitor is,

45
 𝑑 𝑑𝑣
𝑖𝐶 = 𝐶1 (𝑣𝑖 − 𝑣𝑁 ) = 𝐶1 𝑖  (1)
𝑑𝑡 𝑑𝑡
 The current if through the feedback resistor is v0 /Rf and there is no current into the op-amp.
Therefore, the nodal equation at node N is,
𝑑𝑣𝑖 𝑣0
𝐶1 + =0
𝑑𝑡 𝑅𝑓
 From which we have,
𝑑𝑣𝑖
𝑣0 = −𝑅𝑓 𝐶1  (2)
𝑑𝑡
 Thus the output voltage v0 is a constant (–RfCl) times the derivative of the input voltage vi and
the circuit is a differentiator.
 The minus sign indicates a 180° phase shift of the output waveform v0, with respect to the input
signal.
 The phasor equivalent of equation (2) is, V0 (s) = –RfC1 s Vi(s) where V0, and Vi is the phasor
representation of v0, and vi. In steady state, put s = jω.
 We may now write the magnitude of gain A of the differentiator as,
𝑉
|𝐴| = | 0 | = |−𝑗𝜔𝑅𝑓 𝐶1 | = 𝜔𝑅𝑓 𝐶1  (3)
𝑉𝑖
 From equation (3), one can draw the frequency response of the op-amp differentiator. Equation
(3) may be rewritten as
𝑓
|𝐴 | =
𝑓𝑎
where,
1
𝑓𝑎 =  (4)
2𝜋𝑅𝑓 𝐶1
 At f = fa, │A│= 1, i.e., 0 dB, and the gain increases at a rate of +20 dB/decade.
 Thus at high frequency, a differentiator may become unstable and break into oscillation.
 There is one more problem in the differentiator of Fig.
 The input impedance (i.e., l/ωCl) decreases with increase in frequency, thereby making the
circuit sensitive to high frequency noise.
6.3.2 Practical Differentiator:
 A practical differentiator of the type shown in Fig. eliminates the problem of stability and high
frequency noise.

 The transfer function for the circuit in Fig. is given by,

46
 𝑉0 (𝑠) 𝑍𝑓 𝑠𝑅𝑓 𝐶1
= − = −  (5)
𝑉𝑖 (𝑠) 𝑍𝑖 (1 + 𝑠𝑅𝑓 𝐶𝑓 )(1 + 𝑠𝑅1 𝐶1 )
For RfCf = R1C1, we get,
𝑉0 (𝑠) 𝑠𝑅𝑓 𝐶1 𝑠𝑅𝑓 𝐶1
= − = −  (6)
𝑉𝑖 (𝑠) (1 + 𝑠𝑅1 𝐶1 ) 2 𝑓 2
(1 + 𝑗 𝑓 )
𝑏
where,
1
𝑓𝑏 =  (7)
2𝜋𝑅1 𝐶1
 From equation (6)it is evident that the gain increases at +20 dB/decade for frequency f < fb and
decreases at –20 dB/decade for f> fb as shown by dashed lines in Fig.

 This 40 dB/decade change in gain is caused by R1C1 and RfCf factors.

 For the basic differentiator of Fig. the frequency response would have increased continuously
at the rate of +20 dB/decade even beyond fb, causing stability problem at high frequency.
 Thus the gain at high frequency is reduced significantly, thereby avoiding the high frequency
noise and stability problems.
 The value of fb should be selected such that,
fa<fb< fc
where fc is the unity gain bandwidth of the op-amp in open loop configuration.
 For good differentiation, one must ensure that the time period T of the input signal is larger
than or equal to RfCl, that is,
T ≥RfCl (8)
 It may be noted that for RfC1 much greater than R1Cl or RfCf, equation (5) is reduced to, V0/Vi
= –sRfCl, that is, the expression of the output voltage remains the same as in the case of an
ideal differentiator as
𝑑𝑣𝑖
𝑣0 = −𝑅𝑓 𝐶1  (9)
𝑑𝑡
 A resistance Rcomp (= R1║Rf) is normally connected to the (+) input terminal to compensate for
the input bias circuit.
 The output waveform for a practical differentiator with a sinusoidal input is given by,

47
  A good differentiator may be designed as per the following steps:
 Choose fa equal to the highest frequency of the input signal. Assume a practical value of C1
(<lµF) and then calculate Rf.
 Choose fb =10fa (say). Now calculate the values of R1 and Cf so that R1C1 =RfCf.

6.4 INTEGRATOR

14. With neat diagram explain the working of an OP-AMP based integrator. (8) [APR/MAY
2019]
Or
With the help of circuit diagram show how an OP-AMP is used as an integrator and explain its
operation. (8)
Or
With circuit and waveforms explain the application of OP-AMP as an Integrator. (8)
Or
Explain the functions of op-amp as an integrator. Draw the waveforms. (Dec – 14) (4)

6.4 INTEGRATOR:
 If we interchange the resistor and capacitor of the differentiator we have the circuit of Fig.
which as we will see, is an integrator.

48
 The nodal equation at node N is,
𝑣𝑖 𝑑𝑣0
+ 𝐶𝑓 =0  (1)
𝑅1 𝑑𝑡
or
𝑑𝑣0 1
=− 𝑣
𝑑𝑡 𝑅1 𝐶𝑓 𝑖
 Integrating both sides, we get,
𝑡 𝑡
1
∫ 𝑑𝑣0 = − ∫ 𝑣𝑖 ∙ 𝑑𝑡
0 𝑅1 𝐶𝑓 0
𝑡
1
𝑣0 (𝑡) = − ∫ 𝑣 (𝑡) ∙ 𝑑𝑡 + 𝑣0 (0) (2)
𝑅1 𝐶𝑓 0 𝑖
Where v0 (0) is the initial output voltage.
 The circuit, thus provides an output voltage which is proportional to the time integral of the
input and RlCf is the time constant of the integrator.
 It may be noted that there is a negative sign in the output voltage, and therefore, this integrator
is also known as an inverting integrator.
 A resistance, Rcomp = R is usually connected to the (+) input terminal to minimize the effect of
input bias current.
 A simple low pass RC circuit can also work as an integrator when time constant is very large.
 This requires very large values of R and C. The components R and C cannot be made infinitely
large because of practical limitations.
 However, in the op-amp integrator of Fig. by Miller’s theorem, the effective input capacitance
becomes Cf (1 – AV) where AV is the gain of the op-amp.
 The gain AV is infinite for an ideal op-amp, so the effective time constant of the op-amp
integrator becomes very large which results in perfect integration.

49
  The operation of the integrator can also be studied in the frequency domain. In phasor notation,
equation (2) can be written as
1
𝑉0 (𝑠) = − 𝑉 (𝑠)  (3)
𝑠𝑅1 𝐶𝑓 𝑖
 In steady state, put s = jω and we get,
1
𝑉0 (𝑗𝜔) = − 𝑉 (𝑗𝜔)  (4)
𝑗𝜔𝑅1 𝐶𝑓 𝑖
 So, the magnitude of the gain or integrator transfer function is,
𝑉 (𝑗𝜔) 1 1
|𝐴 | = | 0 | = |− |=  (5)
𝑉𝑖 (𝑗𝜔) 𝑗𝜔𝑅1 𝐶𝑓 𝜔𝑅1 𝐶𝑓
 The frequency response or Bode Plot of this basic integrator is shown in Fig.
 The Bode plot is a straight line of slope – 6B/octave (or equivalently 20dB/decade).
 The frequency fb in Fig. is the frequency at which the gain of the integrator is 0 dB and is given
by,
1
𝑓𝑏 =
2𝜋𝑅1 𝐶𝑓
 It can further be seen from equation (5) that at ω = 0, the magnitude of the integrator transfer
function is infinite.
 At dc, the capacitor Cf behaves as an Open circuit and there is no negative feedback.
 The op-amp thus operates in open loop, resulting in an infinite gain.
 In practice, of course, output never becomes infinite, rather the output of the amplifier saturates
at a voltage close to the op-amp positive or negative power supply depending on the polarity of
the input dc signal.
 As the gain of the integrator decreases with increasing frequency, the integrator circuit does not
have any frequency problem as faced in a differentiator.
 However, at low frequencies such as at dc (ω ≈ 0), the gain becomes infinite (or saturates). The
solution to this problem is discussed in the following.
6.4.1 Practical Integrator Circuit: (Lossy Integrator)
 The gain of an integrator at low frequency (dc) can be limited to avoid the saturation problem if
the feedback capacitor is shunted by a resistance R f as shown in Fig.

50
  The parallel combination of Rf and Cf behaves like a practical capacitor which dissipates power
unlike an ideal capacitor.
 For this reason, this circuit is also called a lossy integrator.
 The resistor Rf limits the low frequency gain to –Rf/R1 (generally Rf = 10 R1) and thus provides
dc stabilization.
6.4.2 Analysis:
 The nodal equation at the inverting input terminal of the op-amp of Fig. is,
𝑉𝑖 (𝑠) 𝑉0 (𝑠)
+ 𝑠 𝐶𝑓 𝑉0 + =0  (6)
𝑅1 𝑅𝑓
 from which we have,
1
𝑉0 (𝑠) = − 𝑅 ∙ 𝑉𝑖 (𝑠)  (7)
𝑠𝑅1 𝐶𝑓 + 𝑅1
𝑓

 If Rfis large, the lossy integrator approximates the ideal integrator. For s = jω, magnitude of the
gain of lossy integrator is given by,
𝑅𝑓
𝑉0 1 ⁄𝑅
|𝐴| = | | = = 1
 (8)
𝑉𝑖 2 2
2 2 𝑅 √1 + (𝜔𝑅𝑓 𝐶𝑓 )
√𝜔 2 𝑅1 𝐶𝑓 + 1⁄𝑅2
𝑓

 The Bode plot of the lossy integrator is also shown in Fig. At low frequencies gain is constant
at Rf / Rl. The break frequency, (f = fa) at which the gain is 0.707 (Rf/R1) (or –3dB below its
value of Rf/Rl) is calculated from equation (8)as,
2
√1 + (𝜔𝑅𝑓 𝐶𝑓 ) = √2
 Solving for f = fa, we get,
1
𝑓𝑎 =
2𝜋𝑅𝑓 𝐶𝑓
 This is a very important frequency. It tells us where the useful integration range starts.
 If the input frequency is lower than fa the circuit acts like a simple inverting amplifier and no
integration results.
 As input frequency equals fa, 50% accuracy results. The practical thumb rule is that if the input
frequency is 10 times fa, then 99% accuracy can result.
 For a sinusoidal input, the output waveform in an integrator is given as follows:

51
 6.5 V-I AND I-V CONVERTERS

15. Write a note on V-I and I-V converter. (8)

(or)
Explain voltage to current converter using operational amplifier. (May-15, 17) (8, 5)
6.5.1 V-I CONVERTER: (Trans-conductance Amplifier)
 In many applications, one may have to convert a voltage signal to a proportional output current.
For this, there are two types of circuits possible.
 V-I Converter with floating load
 V-I Converter with grounded load

 Figure shows a voltage to current converter in which load ZL is floating. Since voltage at node
‘a’ is vi, therefore,
𝑣𝑖 = 𝑖𝐿 𝑅1 (𝑎𝑠 𝐼𝐵− = 0)
or
𝑣𝑖
𝑖𝐿 =
𝑅1
 That is the input voltage vi is converted into an output current of vi/R1. It may be seen that the
same current flows through the signal source and load and, therefore, signal source should be
capable of providing this load current.
 A voltage-to-current converter with grounded load is shown in Fig. Let v1 be the voltage at
node ‘a’. Writing KVL, we get,
𝑖1 + 𝑖2 = 𝑖𝐿
52
 or
𝑣𝑖 − 𝑣1 𝑣0 − 𝑣1
+ = 𝑖𝐿
𝑅 𝑅
or
𝑣𝑖 + 𝑣0 − 2𝑣1 = 𝑖𝐿 𝑅
Therefore,
𝑣𝑖 + 𝑣0 − 𝑖𝐿 𝑅
𝑣1 =
2
 Since the op-amp is used in non-inverting mode, the gain of the circuit is 1+R/R = 2. The
output voltage is,
𝑣0 = 2𝑣1 = 𝑣𝑖 + 𝑣0 − 𝑖𝐿 𝑅
(i.e.)
𝑣𝑖 = 𝑖𝐿 𝑅
or
𝑣𝑖
𝑖𝐿 =
𝑅
 As the input impedance of a non-inverting amplifier is very high, this circuit has the advantage
of drawing very little current from the source.
 A voltage to current converter is used for low voltage dc and ac voltmeter, LED and zener
diode tester.

6.5.2 I-V CONVERTER: (Trans-resistance Amplifier)

16. Draw and explain the operation of current to voltage converter. (Nov-15) (8)
 Photocell, photodiode and photovoltaic cell give an output current that is proportional to an
incident radiant energy or light.
 The current through these devices can be converted to voltage by using a current-to-voltage
converter and thereby the amount of light or radiant energy incident on the photo-device can be
measured.

 Figure shows an op-amp used as I to V converter. Since the (–) input terminal is at virtual
ground, no current flows through RS and current is flows through the feedback resistor Rf.
 Thus the output voltage v0 =–iSRf. It may be pointed out that the lowest current that this circuit
can measure will depend upon the bias current IB of the op-amp.
 This means that µA741 (IB = 3 nA) can be used to detect lower currents.
 The resistor Rf is sometimes shunted with a capacitor Cf to reduce high frequency noise and the
possibility of oscillations.

53
 UNIT – III
APPLICATIONS OF OP-AMP
Part – B – 16Mark Questions

1. INSTRUMENTATION AMPLIFIER AND ITS APPLICATIONS OF TRANSDUCER

BRIDGE
1. Draw the circuit of instrumentation amplifier and derive the expression for output voltage for
in it. Also write the advantages of instrumentation amplifier. (16)
(or)
Explain the working of instrumentation amplifier. (May-15) (8)
1. INSTRUMENTATION AMPLIFIER:
 In a number of industrial and consumer applications, one is required to measure and control
physical quantities.
 Some typical examples are measurement and control of temperature, humidity, light intensity,
water flow etc.
 These physical quantities are usually measured with the help of transducers.
 The output of transducer has to be amplified so that it can drive the indicator or display system.
 This function is performed by an instrumentation amplifier.
 The important features of an instrumentation amplifier are:
 High gain accuracy
 High CMRR
 High gain stability with low temperature coefficient
 Low d.c. offset
 Low output impedance
 Consider the basic differential amplifier shown in Fig. 1.

Fig. 3.1 Differential amplifier using single op-amp

 It can be easily seen that the output voltage V0 is given by,
𝑅2 1 𝑅2
𝑉0 = − 𝑉2 + 𝑅 𝑉1 (1 + )
𝑅1 1+ 3 𝑅1
𝑅4
or

11
 𝑅2 1 𝑅1
𝑉0 = − [𝑉2 − 𝑅 ( + 1) 𝑉1 ]
𝑅1 1 + 3 𝑅2
𝑅4
 For R1/R2 = R3/R4, we obtain
𝑅2
𝑉0 = (𝑉 − 𝑉2 )
𝑅1 1
 In the circuit of Fig. 1, source V1 sees an input impedance = R3 + R4(101 kΩ) and the
impedance seen by source V2 is only R1 (1 kΩ).
 This low impedance may load the signal source heavily. Therefore, high resistance buffer is
used after each input to avoid this loading effect as shown in Fig. 2.

Fig. 3.2An improved Instrumentation amplifier

 The op-amps A1 and A2 have differential input voltage as zero. For V1 = V2, that is, under
common mode condition, the voltage across R will be zero.
 As no current flows through R and R' the non-inverting amplifier A1 acts as voltage follower so
its output V2'= V2.
 Similarly op-amp A2 acts as voltage follower having output V1'=V1.
 However, if V1≠ V2, current flows in R and R', and (V2' – V1') > (V2– V1).
 Therefore, this circuit has differential gain and CMRR more compared to the single op-amp
circuit of Fig. 1.
 The output voltage V0 can be calculated as follows:
 The voltage at the (+) input terminal of op-amp A3 is,
𝑅2 𝑉1′
𝑅1 + 𝑅2
 Using superposition theorem, we have,
𝑅2 ′ 𝑅2 𝑅2 𝑉1′
𝑉0 = − 𝑉2 + (1 + ) ( )
𝑅1 𝑅1 𝑅1 + 𝑅2
𝑅2 ′
𝑉0 = (𝑉 − 𝑉2′ )
𝑅1 1
 Since, no current flows into op-amp, the current I flowing (upwards) in R is,
I=(V1–V2)/R
and passes through the resistor R'.
𝑅′
𝑉1′ = 𝑅′ 𝐼 + 𝑉1 = (𝑉1 − 𝑉2 ) + 𝑉1
𝑅
12
 and
𝑅′
𝑉2′ = −𝑅′ 𝐼 + 𝑉2 = − (𝑉 − 𝑉2 ) + 𝑉2
𝑅 1
 Putting the values of V1 ' and V2' in V0 equation, we get,
𝑅2 𝑅′ 𝑅′
𝑉0 = ( 𝑉 − 𝑉2 + 𝑉1 − (− (𝑉1 − 𝑉2 ) + 𝑉2 ))
( )
𝑅1 𝑅 1 𝑅
𝑅2 2𝑅′
[
𝑉0 = (𝑉 − 𝑉2 ) + (𝑉1 − 𝑉2 )]
𝑅1 𝑅 1
or
𝑅2 2𝑅′
𝑉0 = (1 + ) (𝑉1 − 𝑉2 )
𝑅1 𝑅
 The difference gain of this instrumentation amplifier can be varied by using a variable
resistance R.

Fig. 3.3 Instrumentation amplifier using Transducer Bridge

 Fig. 3 shows a differential instrumentation amplifier using Transducer Bridge.
 The circuit uses a resistive transducer whose resistance changes as a function of the physical
quantity to be measured.
 The bridge is initially balanced by a d.c. supply voltage Vdc so that V1 = V2.
 As the physical quantity changes, the resistance R T of the transducer also changes, causing an
unbalance in the bridge (Vl≠ V2).
 This differential voltage now gets amplified by the three op-amp differential instrumentation
amplifier.
PROBLEM:
2. Find the following for the given op- amp differential amplifier: (i) the gain of the amplifier (ii) the
input resistance (iii) output voltage. When the input are 1sin (2000t)V, 1.2 sin(2000t)V and
R1=R3=1.2KΩ, R2=R4= 22KΩ. (Apr/May 2019) 13 marks

13
Solution:
Given Parameters:
V1 = 1sin(2000t) V; V2= 1.2sin(2000t)
R1= R3= 1.2 KΩ
R2=R4= 22 KΩ
(i) Output voltage
V0 = (R2/ R1) (V1- V2)
= (22 KΩ/ 1.2 KΩ) (1.2-1)
V0 = 3.67 V
Vin= V1+ V2 = (1+ 1.2)
= 2.2V
(ii) Gain of the amplifier
AV = V0/Vin
= 3.67/2.2
=1.67 V
(iii) Input resistance
For V1
Input resistance Vi = R1 = 1.2 KΩ
For V2
Input resistance Vi = R3 + R4 = (1.2 + 22)
= 23.2 KΩ

2. LOG AND ANTILOG AMPLIFIERS

3. With circuit diagram explain the working of log and anti-log amplifiers. (Dec –14)
2. LOG AND ANTILOG AMPLIFIER:
 There are several applications of log and antilog amplifiers.
 Antilog computation may require functions such as lnx, log x or sinh x.
 These can be performed continuously with log-amps.
 One would like to have direct dB display on digital voltmeter and spectrum analyser.
 Log-amp can easily perform this function. Log-amp can also be used to compress the dynamic
range of a signal.
2.1 Log Amplifier:
 The fundamental log-amp circuit is shown in Fig. 4 where a grounded base transistor is placed
in the feedback path.
 Since the collector is held at virtual ground and the base is also grounded the transistor’s
voltage-current relationship becomes that of a diode and is given by,
𝐼𝐸 = 𝐼𝑆 (𝑒 𝑞𝑉𝐸 ⁄𝑘𝑇 − 1)
 Since, IC = IE for a grounded base transistor,
𝐼𝐶 = 𝐼𝑆 (𝑒 𝑞𝑉𝐸 ⁄𝑘𝑇 − 1)
𝐼𝑆 = 𝑒𝑚𝑖𝑡𝑡𝑒𝑟 𝑠𝑎𝑡𝑢𝑟𝑎𝑡𝑖𝑜𝑛 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 ≈ 10−13 𝐴
𝑘 = 𝐵𝑜𝑙𝑡𝑧𝑚𝑎𝑛𝑛′ 𝑠 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝑇 = 𝑎𝑏𝑠𝑜𝑙𝑢𝑡𝑒 𝑡𝑒𝑚𝑝𝑒𝑟𝑎𝑡𝑢𝑟𝑒 (𝑖𝑛 0𝐾 )
Therefore,
14
 𝐼𝐶
= (𝑒 𝑞𝑉𝐸 ⁄𝑘𝑇 − 1)
𝐼𝑆
or
𝐼𝐶
𝑒 𝑞𝑉𝐸 ⁄𝑘𝑇 = + 1
𝐼𝑆
𝐼𝐶
≈
𝐼𝑆
as Is≈ 10-13 A, IC>> IS
 Taking natural log on both sides, we get
𝑘𝑇 𝐼𝐶
𝑉𝐸 = ln ( )
𝑞 𝐼𝑆

Fig. 3.4 Fundamental log-amp circuit

Also in Fig. 3.4,
𝑉𝑖
𝐼𝐶 =
𝑅1
𝑉𝐸 = −𝑉0
so,
𝑘𝑇 𝑉𝑖 𝑘𝑇 𝑉𝑖
𝑉0 = − ln ( ) = − 𝑙𝑛 ( )
𝑞 𝑅1 𝐼𝑆 𝑞 𝑉𝑟𝑒𝑓
where,
𝑉𝑟𝑒𝑓 = 𝑅1 𝐼𝑆
 The output voltage is thus proportional to the logarithm of input voltage.
 Although the circuit gives natural log (ln), one can find log 10 by proper scaling.
log10 X = 0.4343 ln X
 The circuit, however, has one problem. The emitter saturation current I S varies from transistor
to transistor and with temperature.
 Thus a stable reference voltage Vref cannot be obtained. This is eliminated by the circuit given
in Fig. 5.

15
 Fig. 3.5 Log-amp with saturation current and temperature compensation
 The input is applied to one log-amp, while a reference voltage is applied to another log-amp.
 The two transistors are integrated close together in the same silicon wafer.
 This provides a close match of saturation currents and ensures good thermal tracking.
Assume, IS1 = IS2 = IS
and then,
𝑘𝑇 𝑉𝑖
𝑉1 = − ln ( )
𝑞 𝑅1 𝐼𝑆
and
𝑘𝑇 𝑉𝑟𝑒𝑓
𝑉2 = − ln ( )
𝑞 𝑅1 𝐼𝑆
Now,
𝑘𝑇 𝑉𝑖 𝑉𝑟𝑒𝑓
𝑉0 = 𝑉2 − 𝑉1 = [𝑙𝑛 ( ) − ln ( )]
𝑞 𝑅1 𝐼𝑆 𝑅1 𝐼𝑆
or
𝑘𝑇 𝑉𝑖
𝑉0 = ln ( )
𝑞 𝑉𝑟𝑒𝑓
 Thus reference level is now set with a single external voltage source. Its dependence on device
and temperature has been removed.
 The voltage V0 is still dependent upon temperature and is directly proportional to T.
 This is compensated by the last op-amp stage A4 which provides a non-inverting gain of (1 +
R2/RTC).
 Now, the output voltage is,
𝑅2 𝑘𝑇 𝑉𝑖
𝑉0 𝑐𝑜𝑚𝑝 = (1 + ) ln ( )
𝑅𝑇𝐶 𝑞 𝑉𝑟𝑒𝑓
 where, RTC is a temperature sensitive resistance with a positive co-efficient of temperature
(sensistor) so that the slope of the equation becomes constant as the temperature changes.
 The circuit in Fig.3.5 requires four op-amps, and becomes expensive if FET op-amps are used
for precision.
 The same output (with an inversion) can be obtained by the circuit of Fig. 6 using two op-amps
only.

16
 Fig. 3.6 Log-amp using two op-amps only
2.2 Antilog Amplifier:
 The circuit is shown in Fig.3.7.

Fig. 3.7 Antilog amplifier

 The input Vi for the antilog-amp is fed into the temperature compensating voltage divider R2
and RTC and then to the base of Q2.
 The output V0 of the antilog-amp is fed back to the inverting input of A1 through the resistor
R1.
 The base to emitter voltage of transistors Q1 and Q2 can be written as
𝑘𝑇 𝑉0
𝑉𝑄1 𝐵−𝐸 = 𝑙𝑛 ( )
𝑞 𝑅1 𝐼𝑆
and
𝑘𝑇 𝑉𝑟𝑒𝑓
𝑉𝑄2 𝐵−𝐸 = 𝑙𝑛 ( )
𝑞 𝑅1 𝐼𝑆
 Since the base of Q1 is tied to ground, we get,
17
 𝑘𝑇 𝑉0
𝑉𝐴 = −𝑉𝑄1 𝐵−𝐸 = − 𝑙𝑛 ( )
𝑞 𝑅1 𝐼𝑆
 The base voltage VB of Q2 is,
𝑅𝑇𝐶
𝑉𝐵 = ( )𝑉
𝑅2 + 𝑅𝑇𝐶 𝑖
 The voltage at the emitter of Q2 is,
𝑉𝑄2 𝐸 = 𝑉𝐵 + 𝑉𝑄2 𝐸−𝐵
or
𝑅𝑇𝐶 𝑘𝑇 𝑉𝑟𝑒𝑓
𝑉𝑄2 𝐸 = ( ) 𝑉𝑖 − 𝑙𝑛 ( )
𝑅2 + 𝑅𝑇𝐶 𝑞 𝑅1 𝐼𝑆
 But the emitter voltage of Q2 is VA, that is,
𝑉𝐴 = 𝑉𝑄2 𝐸
or
𝑘𝑇 𝑉0 𝑅𝑇𝐶 𝑘𝑇 𝑉𝑟𝑒𝑓
− 𝑙𝑛 ( )=( ) 𝑉𝑖 − 𝑙𝑛 ( )
𝑞 𝑅1 𝐼𝑆 𝑅2 + 𝑅𝑇𝐶 𝑞 𝑅1 𝐼𝑆
or
𝑅𝑇𝐶 𝑘𝑇 𝑉0 𝑉𝑟𝑒𝑓
( ) 𝑉𝑖 = − (𝑙𝑛 ( ) − 𝑙𝑛 ( ))
𝑅2 + 𝑅𝑇𝐶 𝑞 𝑅1 𝐼𝑆 𝑅1 𝐼𝑆
or
𝑞 𝑅𝑇𝐶 𝑉0
− ( ) 𝑉𝑖 = 𝑙𝑛 ( )
𝑘𝑇 𝑅2 + 𝑅𝑇𝐶 𝑉𝑟𝑒𝑓
 Changing natural log to log10 we get,
𝑞 𝑅𝑇𝐶 𝑉0
−0.4343 ( ) ( ) 𝑉𝑖 = 0.4343 × 𝑙𝑛 ( )
𝑘𝑇 𝑅2 + 𝑅𝑇𝐶 𝑉𝑟𝑒𝑓
or
𝑉0
−𝐾 ′ 𝑉𝑖 = log10 ( )
𝑉𝑟𝑒𝑓
or
𝑉0 ′
= 10−𝐾 𝑉𝑖
𝑉𝑟𝑒𝑓
or
′
𝑉0 = 𝑉𝑟𝑒𝑓 (10−𝐾 𝑉𝑖 )
𝑞 𝑅𝑇𝐶
where, 𝐾 ′ = 0.4343 (𝑘𝑇 ) (𝑅 )
2 +𝑅𝑇𝐶

 Hence an increase of input by one volt causes the output to decrease by a decade.

4. ANALOG MULTIPLIER AND VOLTAGE DIVIDER

4.1 ANALOG MULTIPLIER
4. Explain the op-amp application as analog multiplier circuit.

 A multiplier is a circuit which produces output that is the product of two inputs applied.
 A circuit which performs multiplication of two analog voltages is called as analog multiplier.
 If V1 and V2 were the two input analog voltages applied, then the output voltage
V0 is given as,
18
 V0 = k V1 V2
Where, k – scaling factor
 The use of a scaling factor k is to avoid the saturating output.
 This is because; the product of two input voltages with moderate value could cause the output to
reach saturation.
 In such a situation, it may become impossible to measure the desired product output V 0.
 The above expression for V0 is the ideal output voltage. They are
(i) Input signal offset (φ1& φ2)
(ii) Error in scaling factor k (e)
(iii) Output signal offset (φ0)
With all these parameters, the output of a practical multiplier is given as V 0 defined by,
(𝑉1 + 𝜑1 )(𝑉2 + 𝜑2 )
𝑉0 = + 𝜑0
10𝑋 (1 + 𝑒)
Note that x can be any integer or fractional value.

4.2 Voltage Divider

5. Explain the op-amp application as voltage divider circuit.
 Voltage divider can be implemented by connecting a multiplier in the feedback loop of an op-
amp as shown here in figure below.
 Vnum is the numerator voltage and Vden is the denominator voltage.
 Note that node ‘a’ is at virtual ground and other end of R c is physically grounded.
 From the diagram,
𝑉𝑛𝑢𝑚 𝑉𝑜𝑚
i1 + i2 = 0 and substituting 𝑖1 = ; 𝑖2 =
𝑅 𝑅
𝑉𝑛𝑢𝑚 𝑉𝑜𝑚
+ =0
𝑅 𝑅
&Vom = k VOAVden = -Vnum
[Where Vom is output of multiplier with two inputs VOA and Vden]
−𝑉𝑛𝑢𝑚
𝑉𝑂𝐴 =
𝐾𝑉𝑑𝑒𝑛
 K is the scale factor. Thus output VOA from op-amp is the divided voltage.

19
 5. 1ST AND 2ND ORDER ACTIVE FILTERS
6. Draw the circuit of a first order Butterworth low pass filter and derive its transfer function.
5.1 FIRST ORDER LOW PASS BUTTER-WORTH FILTER:
 The first order low pass Butterworth filter is realised by R-C circuit used along with an op-
amp, used in the non-inverting configuration.
 The circuit diagram is shown in Fig. 8.

Fig. 3.8 First Order Low Pass Butterworth Filter

 This is also called one pole low pass Butterworth filter.
 The resistances Rf and R1 decide the gain of the filter in the pass band.
5.1.1 Analysis of the Filter Circuit:
 The impedance of the capacitor C is –jXC where XC is the capacitive reactance given by,
1
𝑋𝐶 =
2𝜋𝑓𝐶
 By the potential divider rule, the voltage at the non-inverting input terminal A which is the
voltage across capacitor C is given by,
−𝑗𝑋𝐶
𝑉𝐴 = ∙𝑉
𝑅 − 𝑗𝑋𝐶 𝑖𝑛
1
−𝑗 (2𝜋𝑓𝐶 ) −𝑗 𝑉𝑖𝑛
∴ 𝑉𝐴 = 1
∙ 𝑉𝑖𝑛 = ∙ 𝑉𝑖𝑛 = 2𝜋𝑓𝑅𝐶
𝑅 − 𝑗 (2𝜋𝑓𝐶 ) 2𝜋𝑓𝑅𝐶 − 𝑗 1− 𝑗
but – j = 1 / j and – 1 / j = j
𝑉𝑖𝑛
∴ 𝑉𝐴 =
1 + 𝑗2𝜋𝑓𝑅𝐶
 As the op-amp is in the non-inverting configuration,
𝑅𝑓
𝑉0 = (1 + ) 𝑉𝐴
𝑅1
𝑅𝑓 𝑉𝑖𝑛
𝑉0 = (1 + ) ∙
𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶
i.e.
𝑉0 𝐴𝐹
=
𝑉𝑖𝑛 1 + 𝑗 ( 𝑓 )
𝑓𝐻
𝑅𝑓
where, 𝐴𝐹 = (1 + 𝑅 ) = 𝐺𝑎𝑖𝑛 𝑜𝑓 𝑓𝑖𝑙𝑡𝑒𝑟 𝑖𝑛 𝑝𝑎𝑠𝑠 𝑏𝑎𝑛𝑑
1
1
𝑓𝐻 = = 𝐻𝑖𝑔ℎ 𝑐𝑢𝑡 − 𝑜𝑓𝑓 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑜𝑓 𝑓𝑖𝑙𝑡𝑒𝑟
2𝜋𝑓𝐶
and
20
 𝑓 = 𝑂𝑝𝑒𝑟𝑎𝑡𝑖𝑛𝑔 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
 The V0 / Vin is the transfer function of the filter and can be expressed in the polar form as,
𝑉0 𝑉0
=| |<𝜑
𝑉𝑖𝑛 𝑉𝑖𝑛
𝑉0 𝐴𝐹
where, | |=
𝑉𝑖𝑛 2
√1+( 𝑓 )
𝑓𝐻

𝑓
and 𝜑 = − tan−1 (𝑓 )
𝐻

The phase angle  is in degrees.

 The transfer function equation describes the behaviour of the low pass filter.
 At very low frequencies, f <fH
𝑉0
| | = 𝐴𝐹 𝑖. 𝑒. 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝑉𝑖𝑛
 At f = fH,
𝑉0 𝐴𝐹
| |= = 0.707𝐴𝐹 𝑖. 𝑒. 3 𝑑𝐵 𝑑𝑜𝑤𝑛 𝑡𝑜 𝑡ℎ𝑒 𝑙𝑒𝑣𝑒𝑙 𝑜𝑓 𝐴𝐹
𝑉𝑖𝑛 √2
 At f >fH
𝑉0
| | < 𝐴𝐹
𝑉𝑖𝑛
 Thus for the range of frequencies, 0 < f <fH, the gain is almost constant equal to fH which is
high cut-off frequencies.
 At f = fH, gain reduces to 0.707 AF i.e. 3 dB down from AF and as the frequency increases than
fH, the gain decreases at a rate of 20 dB / decade.
 The rate 20 dB / decade mean decrease of 20 dB in gain per 10 times change in frequency.
 The same rate can be expressed as 6 dB / octave i.e. decrease of 6 dB per two times change in
the frequency.
 The frequency fH is called cut off frequency, break frequency, -3 dB frequency or corner
frequency.
 The frequency response is shown in the Fig. 9.

Fig. 3.9 Frequency Response

5.1.2 Design steps:
The design steps for the first order low pass Butterworth filter are,
 Choose the cut-off frequency, fH.

21
  Choose the capacitance C usually between 0.001 and 1µF. Generally, it is selected as
1µF or less than that. For better performance, Mylar or Tantalum capacitors are
selected.
1
 Now, for the RC circuit, 𝑓𝐻 =
2𝜋𝑓𝐶
 Hence, as fH and C are known, calculate the value of R.
 The resistance Rf and R1 can be selected depending on the required gain in the pass
𝑅
band. 𝐴𝐹 = (1 + 𝑅𝑓 )
1

5.2 SECOND ORDER LOW PASS BUTTERWORTH FILTER:

7. Draw the circuit of a second order Butterworth low pass filter and derive its transfer
function. (Nov-17) (16, 13)
(or)
Design a second order butter worth low pass filter having upper cut-off frequency of 1 kHz.
(Nov-15) (12)

 The practical response of the filter must be very close to an ideal one.
 In case of low pass filter, it is always desirable that the gain rolls off very fast after the cut off
frequency, in the stop band.
 In case of first order filter, the gain rolls off at a rate of 40 dB / decade.
 Thus, the slope of the frequency response after f = fH is – 40 dB / decade, for a second order
low pass filter.
 A first order filter can be converted to second order type using an additional RC network as
shown in the fig.3.10.

Fig. 3.10 Second Order Low Pass Butterworth Filter

 The cut off frequency fH for the filter is now decided by R2, C2, R3, and C3.
 The gain of the filter is as usual decided by op-amp i.e. the resistance R1 and Rf.
5.2.1 Analysis of the Filter circuit:
 For deriving the expression for the cut off frequency, let us use the Laplace transform method.
 The input RC network can be represented in the Laplace domain as shown in Fig. 3.11
Now,
𝐼1 = 𝐼2 + 𝐼3 → (1)
i.e.

22
 𝑉𝑖𝑛 − 𝑉1 𝑉1 − 𝑉0 𝑉1 − 𝑉𝐴
= 1
+ → (2)
𝑅2 (𝑠𝐶 ) 𝑅3
2

Fig. 3.11 Laplace domain of RC Network

 Using potential divider rule, we can write,
1
𝑠𝐶3
𝑉𝐴 = 𝑉1 [ 1 ] → (3)
𝑅3 + 𝑠𝐶
3
𝑉1
𝑉𝐴 =
1 + 𝑠𝑅3 𝐶3
∴ 𝑉1 = 𝑉𝐴 (1 + 𝑠𝑅3 𝐶3 ) → (4)
 Substituting in equation (2) and solving for VA, we get,
𝑉𝑖𝑛 − 𝑉𝐴 (1 + 𝑠𝑅3 𝐶3 ) 𝑉𝐴 (1 + 𝑠𝑅3 𝐶3 ) − 𝑉0 𝑉𝐴 (1 + 𝑠𝑅3 𝐶3 ) − 𝑉𝐴
= 1
+
𝑅2 ( ) 𝑅3
𝑠𝐶2
𝑉𝑖𝑛 (1 + 𝑠𝑅3 𝐶3 ) (1 + 𝑠𝑅3 𝐶3 ) 1
+ 𝑉0 (𝑠𝐶2 ) = 𝑉𝐴 [ + 𝑠𝐶2 (1 + 𝑠𝑅3 𝐶3 ) + − ]
𝑅2 𝑅2 𝑅3 𝑅3
𝑉𝑖𝑛 ( )
𝑅3 (1 + 𝑠𝑅3 𝐶3 ) + 𝑅2 𝑅3 𝑠𝐶2 1 + 𝑠𝑅3 𝐶3 + 𝑅2 (1 + 𝑠𝑅3 𝐶3 ) − 𝑅2
∴ + 𝑉0 (𝑠𝐶2 ) = 𝑉𝐴 [ ]
𝑅2 𝑅2 𝑅3
∴ (𝑅3 𝑉𝑖𝑛 + 𝑉0 𝑠𝑅2 𝑅3 𝐶2 ) = 𝑉𝐴 [(1 + 𝑠𝑅3 𝐶3 )(𝑅3 + 𝑅2 𝑅3 𝑠𝐶2 + 𝑅2 ) − 𝑅2 ]
𝑅3 𝑉𝑖𝑛 + 𝑉0 𝑠𝑅2 𝑅3 𝐶2
𝑉𝐴 = ) → (5)
[(1 + 𝑠𝑅3 𝐶3 )(𝑅3 + 𝑅2 𝑅3 𝑠𝐶2 + 𝑅2 ) − 𝑅2 ]
 Now, for op-amp in non-inverting configuration,
𝑉0 = 𝐴𝐹 𝑉𝐴
where,
𝑅𝑓
𝐴𝐹 = 1 + → (6)
𝑅1
and 𝑉𝐴 = 𝑇ℎ𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑎𝑡 𝑡ℎ𝑒 𝑛𝑜𝑛 − 𝑖𝑛𝑣𝑒𝑟𝑡𝑖𝑛𝑔 𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑙
𝑅3 𝑉𝑖𝑛 + 𝑉0 𝑠𝑅2 𝑅3 𝐶2
𝑉0 = 𝐴𝐹 [ ]
[(1 + 𝑠𝑅3 𝐶3 )(𝑅3 + 𝑅2 𝑅3 𝑠𝐶2 + 𝑅2 ) − 𝑅2 ]
𝐴𝐹 𝑅3 𝑉𝑖𝑛 𝑠𝑅2 𝑅3 𝐶2
∴ = 𝑉0 [1 − ]
[(1 + 𝑠𝑅3 𝐶3 )(𝑅3 + 𝑅2 𝑅3 𝑠𝐶2 + 𝑅2 ) − 𝑅2 ] [(1 + 𝑠𝑅3 𝐶3 )(𝑅3 + 𝑅2 𝑅3 𝑠𝐶2 + 𝑅2 ) − 𝑅2 ]
∴ 𝐴𝐹 𝑅3 𝑉𝑖𝑛 = 𝑉0 [(1 + 𝑠𝑅3 𝐶3 )(𝑅3 + 𝑅2 𝑅3 𝑠𝐶2 + 𝑅2 ) − 𝑅2 ] − 𝑠𝑅2 𝑅3 𝐶2
𝑉0 𝐴𝐹
∴ = → (7)
𝑉𝑖𝑛 𝑠 2 + 3 3 2 3 2 2 −𝐴𝐹 𝑅2 𝐶2 )𝑠 +
(𝑅 𝐶 +𝑅 𝐶 +𝑅 𝐶 1
𝑅2 𝑅3 𝐶2 𝐶3 𝑅2 𝑅3 𝐶2 𝐶3
 As the order of s in the gain expression is two, the filter is called second order filter.

23
  The standard form of the transfer function of any second order system is,
𝑉0 𝐴
= 2 → (8)
𝑉𝑖𝑛 𝑠 + 2𝜉𝜔𝑛 𝑠 + 𝜔𝑛2
where, A = Overall gain
ξ = Damping of system
ωn = Natural frequency of oscillations
 Comparing equation (7) and (8), we can say that,
1
𝜔𝑛2 = → (9)
𝑅2 𝑅3 𝐶2 𝐶3
 In case of filters, this frequency is nothing but the cut-off frequency, ωH
2
1
∴ 𝜔𝐻 =
𝑅2 𝑅3 𝐶2 𝐶3
1
∴ (2𝜋𝑓𝐻 )2 =
𝑅2 𝑅3 𝐶2 𝐶3
1
∴ 𝑓𝐻 = → (10)
2𝜋√𝑅2 𝑅3 𝐶2 𝐶3
This is the required cut-off frequency.
 Replacing s by jω, the transfer function can be written in the frequency domain and hence,
finally, can be expressed in the polar form as,
𝑉0 𝑉0
=| |<𝜑
𝑉𝑖𝑛 𝑉𝑖𝑛
where,
𝑉0 𝐴𝐹
| |= → (11)
𝑉𝑖𝑛 𝑓 4
√1 + ( )
𝐻 𝑓
where, AF = Gain of filter in pass band
f = Input frequency in Hz
fH = High cut-off frequency in Hz
 The frequency response is shown in fig.3.12.

Fig. 3.12 Frequency Response

 At the cut-off frequency, fH, the gain is 0.707 AF i.e. 3 dB down from its 0 Hz level.
 After, fH (f >fH), the gain rolls off at a rate of 40 dB / decade.
 Hence, the slope of the response after fH is – 40 dB / decade.

24
5.2.2 Design steps:
 The design steps for second order low pass Butterworth filter are:
 Choose the cut-off frequency fH.
 The design can be simplified by selecting R2 = R3 = R andC2 = C3 = C and choose a value
of C less than or equal to 1 µF.
 Calculate the value of R from the equation,
1 1
 𝑓𝐻 = 2𝜋√𝑅 = 2𝜋𝑅𝐶
2 𝑅3 𝐶2 𝐶3

 As R2 = R3 = R and C2 = C3 = C, the pass band voltage gain AF = (1 + Rf/R1) of the second

order low pass filter has to be equal to 1.586.
 Note: For R2 = R3 = R and C2 = C3 = C, the transfer function takes the form,
𝑉0 (𝑠) 𝐴𝐹
= 3−𝐴 1 → (12)
𝑉𝑖𝑛 (𝑠) 𝑠 2 + 𝐹
𝑠+
𝑅𝐶 𝑅2 𝐶 2
 From this we can write that,
ξ = Damping factor = (3 – AF)/2 →(13)
 Now, for second order Butterworth filter, the middle term required is √2 = 1.414, from the
normalised Butterworth polynomial.
∴ 3 − 𝐴𝐹 = √2 = 1.414
∴ 𝐴𝐹 = 1.5862 → (14)
 Thus, to ensure the Butterworth response, it is necessary that the gain A F is 1.586.
𝑅𝑓
∴ 1.586 = 1 +
𝑅1
∴ 𝑅𝑓 = 0.586𝑅1 → (15)
 Hence, choose a value of R1 ≤ 100 kΩ and calculate the corresponding value of R f.

5.3 FIRST ORDER HIGH PASS BUTTERWORTH FILTER:

8. Discuss the second order high pass filter with its frequency response.

 A high pass filter is a circuit that attenuates all the signals below a specified cut-off frequency
denoted as fL.
 Thus, a high pass filter performs the opposite function to that of a low pass filter.
 Hence, the high pass filter circuit can be obtained by interchanging the frequency determining
resistances and capacitors in low pass filter circuit.
 The first order high pass filter can be obtained by interchanging the elements R and C in the
first order low pass filter circuit as shown in Fig. 3.13.
 The frequency at which the gain is 0.707 times the gain of filter in pass band is called low cut-
off frequency and denoted as fL.
 So, all the frequencies greater than fL is allowed to pass but the maximum frequency which is
allowed to pass is determined by the closed loop band-width of the op-amp.

25
 Fig. 3.13 First Order High Pass Butterworth Filter
5.3.1 Analysis of the Filter Circuit:
 The impedance of the capacitor is, – j XC, where,
1
𝑋𝐶 =
2𝜋𝑓𝐶
 By the potential divider rule, the voltage at the non-inverting input terminal A which is the
voltage across capacitor C is given by,
𝑅
𝑉𝐴 = [ ]𝑉
𝑅 − 𝑗𝑋𝐶 𝑖𝑛
𝑅 2𝜋𝑓𝐶 𝑗2𝜋𝑓𝐶
∴ 𝑉𝐴 = 1
∙ 𝑉𝑖𝑛 = ∙ 𝑉𝑖𝑛 = 𝑉𝑖𝑛 [2𝜋𝑓𝑅𝐶 ]
𝑅 − 𝑗 (2𝜋𝑓𝐶 ) 2𝜋𝑓𝑅𝐶 − 𝑗 +1 −𝑗
but – j = 1 / j and – 1 / j = j
𝑗2𝜋𝑓𝐶
∴ 𝑉𝐴 = 𝑉𝑖𝑛 [ ]
𝑗2𝜋𝑓𝑅𝐶 + 1
 This can be represented as,
𝑓
𝑗 (𝑓 )
𝐿
𝑉𝐴 = 𝑉𝑖𝑛 [ 𝑓
]
1 + 𝑗 (𝑓 )
𝐿
where,
1
𝑓𝐿 == 𝐿𝑜𝑤 𝑐𝑢𝑡 − 𝑜𝑓𝑓 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
2𝜋𝑓𝐶
 Now, for the op-amp in the non-inverting configuration,
𝑉0 = 𝐴𝐹 𝑉𝐴
where, VA = voltage at the non-inverting input
𝑅𝑓
and AF = (1 + 𝑅 ) = gain of op-amp in pass band
1
𝑓
𝑗 (𝑓 )
𝐿
∴ 𝑉0 = 𝐴𝐹 𝑉𝑖𝑛 [ 𝑓
]
1 + 𝑗 (𝑓 )
𝐿
i.e.
𝑓
𝑉0 𝑗( )
𝑓𝐿
= 𝐴𝐹 [ 𝑓
]
𝑉𝑖𝑛 1+𝑗( )
𝑓𝐿

 This is the transfer function of the filter and can be expressed in the polar form as,

26
 𝑉0 𝑉0
=| |<𝜑
𝑉𝑖𝑛 𝑉𝑖𝑛
where,
𝑓
𝑉0 𝐴𝐹 ( 𝑓 )
𝐿
| |=
𝑉𝑖𝑛 2
√1 + ( 𝑓 )
𝑓𝐿
 The above equation describes the behaviour of the high pass filter.
 At very low frequencies, f <fL
𝑉
 |𝑉 0 | < 𝐴𝐹
𝑖𝑛
 At f = fL,
𝑉
 |𝑉 0 | = 0.707𝐴𝐹 𝑖. 𝑒. 3 𝑑𝐵 𝑑𝑜𝑤𝑛 𝑓𝑟𝑜𝑚 𝑡ℎ𝑒 𝑙𝑒𝑣𝑒𝑙 𝑜𝑓 𝐴𝐹
𝑖𝑛
 At f >fL, i.e. high frequencies, 1 can be neglected as compared to (f/fL) from
denominator.
𝑉0
∴ | | ≅ 𝐴𝐹 𝑖. 𝑒. 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝑉𝑖𝑛
 Thus the circuit acts as high pass filter with a pass band gain as AF.
 For the frequencies f <fL, the gain increases till f = fL at a rate of + 20 dB / decade.
 Hence, the slope of the frequency response in stop band is + 20 dB / decade for first order high
pass filter.
 The frequency response is shown in the Fig.3.14.

Fig. 3.14 Frequency Response

5.3.2 Design steps:
 The design steps for the first order high pass Butterworth filter are,
 Choose the cut-off frequency, fL.
 Choose the capacitance C usually between 0.001 and 1µF. Generally, it is selected as
1µF or less than that. For better performance, Mylar or Tantalum capacitors are
selected.
 Now, for the RC circuit,
1
𝑓𝐿 =
2𝜋𝑓𝐶
Hence, as fH and C are known, calculate the value of R.
 The resistance Rf and R1 can be selected depending on the required gain in the pass
𝑅
band. 𝐴𝐹 = (1 + 𝑅𝑓 )
1

27
5.4 SECOND ORDER HIGH PASS BUTTERWORTH FILTER:
9. Discuss the second order high pass filter with its frequency response and design the circuit
with cut-off frequency of 5 KHZ. (May-15) (8)
 The second order high pass Butterworth produces a gain roll off at the rate of + 40 dB / decade
in the stop band.
 This filter can also be realised by interchanging the positions of resistors and capacitors in a
second order low pass Butterworth filter.
 The Fig. 3.15 shows the second order high pass Butterworth filter.

Fig. 3.15 Second Order High Pass Butterworth Filter

 The analysis, design and the scaling produces for this filter is exactly the same as that of second
order low pass Butterworth filter.
 The voltage magnitude equation for the second order high pass filter is,
𝑉0 𝐴𝐹
| |=
𝑉𝑖𝑛 4
√1 + ( 𝑓 )
𝑓 𝐻

where, f = input frequency in Hz

1
𝑓𝐿 = 𝑙𝑜𝑤𝑒𝑟 𝑐𝑢𝑡 − 𝑜𝑓𝑓 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑖𝑛 𝐻𝑧 = 2𝜋√𝑅
2 𝑅3 𝐶2 𝐶3

 For, R2 = R3 = R and C2 = C3 = C,
fL = 1/2πRC
AF=Pass band gain=1.586 to ensure second order Butterworth response
and Rf = 0.586 R1
 The frequency response of this filter is shown in the Fig.3.16.

Fig. 3.16 Frequency Response

28
 6. COMPARATORS
10. Explain in detail of comparator circuit.
6.1 COMPARATOR:
 A comparator is a circuit which compares a signal voltage applied at one input of an op-amp
with a known reference voltage at the other input.
 It is basically an open-loop op-amp with output Vsat (= VCC) as shown in the ideal transfer
characteristics of Fig.3.17 (a).
 However, a commercial op-amp has the transfer characteristics of Fig. 17 (b).

Fig. 3.17 Transfer Characteristics (a) Ideal Comparator (b) Practical Comparator
 It may be seen that the change in the output state takes place with an increment in input V i of
only 2 mV.
 This is the uncertainty region where output cannot be directly defined.

 There are basically two types of comparators:

 Non-inverting comparator
 Inverting comparator
 The circuit of Fig.3.18 is called a non-inverting comparator.

Fig. 3.18 Non-inverting comparator

 A fixed reference voltage Vref is applied to (–) input and a time varying signal Vi, is applied to
(+) input. The output voltage is at –Vsat, for Vi < Vref and V0 goes to + Vsat for Vi>Vref.
 The output waveforms for a sinusoidal input signal applied to the (+) input is shown in
Fig.3.19for positive and negative Vref respectively.

29
 Fig. 3.19 Input and output waveforms for (a) Vref positive (b) Vref negative
 In a practical circuit Vref is obtained by using a 10 kΩ potentiometer which forms a voltage
divider with the supply voltages V+ and V–with the wiper connected to (–) input terminal as
shown in Fig.3.20.

Fig. 3.20 Practical Non-inverting comparator

 Thus a Vrefof desired amplitude and polarity can be obtained by simply adjusting the 10 kΩ
potentiometer.
 Fig.3.21 shows a practical inverting comparator in which the reference voltage Vref is applied to
the (+) input and Vi, is applied to (–) input.

Fig. 3.21 Inverting Comparator

 For a sinusoidal input signal, the output waveform is shown in Fig.3.22 for Vref positive and
negative respectively.

30
 Fig. 3.22 Input and output waveforms for (a) Vref positive (b) Vref negative
 Output voltage levels independent of power supply voltages can also be obtained by using a
resistor R and two back to back zener diodes at the output of op-amp as shown in Fig.3.23.

Fig. 3.23 Comparator with zener diode at the output

 The value of resistance R is chosen so the zener diode operates at the recommended current.
 It can be seen that the limiting voltages of V0 are (Vz1 + VD) and – (VZ2 + VD) where VD (~ 0.7
V) is the diode forward voltage.
 In the waveforms of Fig.3.19 and 3.22, the output transitions are shown as taking place
instantaneously.
 Practical circuits, however, take a certain amount of time to switch from one voltage level to
another.
 The actual waveform will therefore exhibit slanted edges as well as delays at the points of input
threshold crossing.
 These effects are more noticeable at high frequencies where the output switching times are
comparable or even longer than the input period itself.
 Thus there is an upper limit to the operating frequency of any comparator.
6.2 Applications of Comparator:
 Some important applications of comparator are:
 Zero crossing detector
 Window detector
 Time marker generator
 Phase meter
6.2.1 Zero Crossing Detector:
 The basic comparators of Fig.3.18 and 3.21 can be used as a zero crossing detector provided
that Vref is set to zero.

31
  An inverting zero-crossing detector is shown in Fig. 24 (a) and the output waveform for a
Sinusoidal input signal is shown in Fig. 24 (b)

Fig. 3.24 (a) Zero crossing detector (b) Input and Output Waveforms
 The circuit is also called a sine to square wave generator.
6.2.2 Window Detector:
 Sometimes one may like to mark the instant at which an unknown input is between two
threshold levels.
 This can be achieved by a circuit called window detector.
 Fig. 3.25 shows a three level detector with indicator circuit.

Fig. 3.25 Three level comparator with LED indicator

 There are three indicators: Yellow (LED 3) for input too low (<3V), Green (LED 2) for safe
input (3 – 6V) and Red (LED 1) for high input (> 6V). They are turned on and off as indicated
in Table 3.1.

32
 Table 3.1 Three level comparator specifications
Input (V) Yellow LED 3 Green LED 2 Red LED 1
Less than 3 V On Off Off
Between 3 V and 6 V Off On Off
Greater than 6 V Off Off On

6.3 REGENERATIVE COMPARATOR (SCHMITT TRIGGER)

11. Explain the operation of Schmitt trigger. (Dec – 14)
(or)
With the neat circuit diagram explain the working of Schmitt trigger using op-amp. (May-15) (8)

 If positive feedback is added to the comparator circuit, gain can be increased greatly.
 Consequently, the transfer curve of comparator becomes more close to ideal curve.
 Theoretically, if the loop gain –βAOL is adjusted to unity, then the gain with feedback, AVf
becomes infinite.
 This results in an abrupt (zero rise time) transition between the extreme values of output
voltage.
 In practical circuits, however, it may not be possible to maintain loop-gain exactly equal to
unity for a long time because of supply voltage and temperature variations.
 So a value greater than unity is chosen. This also gives an output waveform virtually
discontinuous at the comparison voltage.
 This circuit, however, now exhibits a phenomenon called hysteresis or backlash.
 Fig. 3.26 shows such a regenerative comparator. The circuit is also known as Schmitt Trigger.

Fig. 3.26 An inverting Schmitt trigger

 The input voltage is applied to the (–) input terminal and feedback voltage to the (+) input
terminal.
 The input voltage Vi triggers the output V0 every time it exceeds certain voltage levels.
 These voltage levels are called upper threshold voltage (VUT) and lower threshold voltage
(VLT).
 The hysteresis width is the difference between these two threshold voltages i.e. V UT– VLT.
 These threshold voltages are calculated as follows.
 Suppose the output V0 = + Vsat, then the voltage at (+) input terminal will be
𝑅2
𝑉𝑟𝑒𝑓 + (𝑉 − 𝑉𝑟𝑒𝑓 ) = 𝑉𝑈𝑇
𝑅1 − 𝑅2 𝑠𝑎𝑡
 This voltage is called upper threshold voltage VUT.
33
 As long as Viis less than VUT, the output V0 remains constant at + Vsat.
 When Vi is just greater than V UT, the output regeneratively switches to – Vsat and remains at
this level as long as Vi> VUT as shown in Fig.3.27 (a).
 For V0 = – Vsat, the voltage at the (+) input terminal is
𝑅2
𝑉𝑟𝑒𝑓 − (𝑉 + 𝑉𝑟𝑒𝑓 ) = 𝑉𝐿𝑇
𝑅1 − 𝑅2 𝑠𝑎𝑡
 This voltage is referred to as lower threshold voltage VLT.
 The input voltage Vi must become lesser than VLT in order to cause V0 to switch from – Vsat to
+Vsat.
 A regenerative transition takes place as shown in Fig.3.27 (b) and the output V0 returns from –
Vsat to +Vsat almost instantaneously.
 The complete transfer characteristics are shown in Fig.3.27 (c).

Fig. 3.27 (a, b) Transfer characteristics for vi increasing and vi decreasing

(c) Composite input-output curve
 Note that VLT< VUT and the difference between these two voltages is the hysteresis width V H
and can be written as
2𝑅2 𝑉𝑠𝑎𝑡
𝑉𝐻 = 𝑉𝑈𝑇 − 𝑉𝐿𝑇 =
𝑅1 + 𝑅2
 Because of the hysteresis, the circuit triggers at a higher voltage for increasing signals than for
decreasing ones.
 Further, note that if peak-to-peak input signal Vi were smaller than VH then the Schmitt trigger
circuit, having responded at a threshold voltage by a transition in one direction would never
reset itself, that is, once the output has jumped to, say, +V sat it would remain at this level and
never return to – Vsat.
 It may be seen from the equation of VH that hysteresis width VHis independent of Vref.
 The resistor R3 in Fig. 3.26 is chosen equal to R1 ║ R2 to compensate for the input bias current.

34
 A non-inverting Schmitt trigger is obtained if Vi and Vref are interchanged in Fig.3.26.
 The most important application of Schmitt trigger circuit is to convert a very slowly varying
input voltage into a square wave output as shown in Fig.3.28.

Fig. 3.28 Schmitt trigger used as a squarer

 If in the circuit of Fig. 3.26, Vref is chosen as zero volt, so we can write,
𝑅2 𝑉𝑠𝑎𝑡
𝑉𝑈𝑇 = −𝑉𝐿𝑇 =
𝑅1 + 𝑅2
 If an input sinusoid of frequency f = 1/T is applied to such a comparator, a symmetrical square
wave is obtained at the output.
 The vertical edge of the output waveform however will not occur at the time the sine wave
passes through zero but is shifted in phase by θ where sin θ = VUT/Vm and Vmis the peak
sinusoidal voltage as shown in Fig. 3.29.

Fig. 3.29 Shift θ in the output waveform for VUT = – VLT

35
 7. MULTIVIBRATORS

7.1 ASTABLE MULTIVIBRATOR: (SQUARE WAVE GENERATOR)

12. Draw the circuits of Astable multivibrator and obtain expression for pulse width T.

 A simple op-amp square wave generator is shown in Fig. 3.30.

 Also called a free running oscillator, the principle of generation of square wave output is to
force an op-amp to operate in the saturation region.
 In Fig.3.30 fraction β = R2/(R1 + R2) of the output is fed back to the (+) input terminal.

Fig. 3.30 Simple op-amp square wave generator

 Thus the reference voltage Vref is βV0 and may take values as + βVsator – βVsat.
 The output is also fed back to the (–) input terminal after integrating by means of a low-pass
RC combination.
 Whenever input at the (–) input terminal just exceeds Vref, switching takes place resulting in a
square wave output.
 In an astable multivibrator, both the states are quasi stable.
 Consider an instant of time when the output is at +Vm.
 The capacitor now starts charging towards +Vsat through resistance R, as shown in Fig.3.31.

Fig. 3.31 Waveforms

 The voltage at the (+) input terminal is held at + βVsat by R1 and R2 combination.

36
  This condition continues as the charge on C rises, until it has just exceeded + βVsat, the
reference voltage.
 When the voltage at the (–) input terminal becomes just greater than this reference voltage, the
output is driven to –Vsat. At this instant, the voltage on the capacitor is + βVsat.
 It begins to discharge through R, that is, charges toward–Vsat.
 When the output voltage switches to –Vsat, the capacitor charges more and more negatively
until its voltage just exceeds – βVsat.
 The output switches back to + Vsat. The cycle repeats itself as shown in Fig. 31.
 The frequency is determined by the time it takes the capacitor to charge from –βVsat to + βVsat
and vice versa.
 The voltage across the capacitor as a function of time is given by,
𝑣𝑐 (𝑡) = 𝑉𝑓 + (𝑉𝑖 − 𝑉𝑓 )𝑒 −𝑡⁄𝑅𝐶
where, the final value, Vf = + Vsat
and the initial value, Vi = –βVsat
Therefore,
𝑣𝑐 (𝑡) = 𝑉𝑠𝑎𝑡 + (−𝛽𝑉𝑠𝑎𝑡 − 𝑉𝑠𝑎𝑡 )𝑒 −𝑡 ⁄𝑅𝐶
or
𝑣𝑐 (𝑡) = 𝑉𝑠𝑎𝑡 − 𝑉𝑠𝑎𝑡 (1 + 𝛽 )𝑒 −𝑡 ⁄𝑅𝐶
 At t = T1, voltage across the capacitor reaches βV sat and switching takes place. Therefore,
𝑣𝑐 (𝑇1 ) = 𝛽𝑉𝑠𝑎𝑡 = 𝑉𝑠𝑎𝑡 − 𝑉𝑠𝑎𝑡 (1 + 𝛽 )𝑒 −𝑡 ⁄𝑅𝐶
 After algebraic manipulation, we get,
1+𝛽
𝑇1 = 𝑅𝐶 ln
1−𝛽
 This gives only one half of the period.
 Total time period is given as,
1+𝛽
𝑇 = 2𝑇1 = 2𝑅𝐶 𝑙𝑛
1−𝛽
as the output waveform is symmetrical.
 If R1 = R2, then β = 0.5, and T = 2RC ln 3. And for R1 = 1.16R2, it can be seen that,
T = 2RC
or
1
𝑓0 =
2𝑅𝐶
 The output swings from + Vsat to – Vsat, so,
V0 (peak-to-peak) = 2Vsat
 The peak to peak output amplitude can be varied by varying the power supply voltage.
 However, a better technique is to use back to back zener diodes as shown in Fig. 32.
 The output voltage is regulated to  (VZ + VD) by the zener diodes.
V0 (peak-to-peak) = 2(VZ + VD)
 Resistor RSC limits the currents drawn from the op-amp to,
𝑉𝑠𝑎𝑡 − 𝑉𝑍
𝐼𝑆𝐶 =
𝑅𝑆𝐶
 This circuit works reasonably well at audio frequencies. At higher frequencies, however, slew-
rate of the op-amp limits the slope of the output square wave.
37
 Fig. 3.32 Use of back to back zener diodes
 If an asymmetric square wave is desired, then zener diodes with different break down voltages
VZ1 and VZ2 may be used.
 Then the output is either V01 or V02, where V01 = VZ1 + VD and V02 = VZ2 + VD.
 It can be easily shown that the positive section is given by,
1 + 𝛽 𝑉01 ⁄𝑉02
𝑇1 = 𝑅𝐶 𝑙𝑛
1−𝛽
 The duration of negative section T2 will be the same as T1 with V01 and V02 interchanged.
 An alternative method to get asymmetric square wave output is to add a d.c. voltage source V
in series R2 as shown in Fig.3.33.

Fig. 3.33 Asymmetric Square Wave Generator

 Now the capacitor C swings between the voltage levels (βV sat + V) and (–βVsat + V).
 If the voltage source V is made variable, voltage to frequency conversion can be achieved,
though the variation will not be linear.
7.2. MONOSTABLE MULTIVIBRATOR:
13. Draw the circuits of Mono stable multivibrator and obtain expression for pulse width T.
 Mono stable multivibrator has one stable state and the other is quasi stable state.
 The circuit is useful for generating single output pulse of adjustable time duration in response
to a triggering signal.

38
 The width of the output pulse depends only on external components connected to the op-amp.
 The circuit shown in Fig. 3.34 is a modified form of an astable multivibrator.

Fig. 3.34 Mono stable multivibrator

 A diode D1 clamps the capacitor voltage to 0.7 V when the output is at + V sat.
 A negative going pulse signal of magnitude V1 passing through the differentiator R4C4 and
diode D2 produces a negative going triggering impulse and is applied to the (+) input terminal.
 To analyse the circuit, let us assume that in the stable state, the output V 0 is at + Vsat.
 The diode D1 conducts and vC the voltage across the capacitor C gets clamped to + 0.7V.
 The voltage at the (+) input terminal through R1R2 potentiometric divider is + βVsat.
 Now, if a negative trigger of magnitude V1 is applied to the (+) input terminal so that the
effective signal at this terminal is less than 0.7V i.e. ([βVsat + (–V1)] < 0.7 V), the output of the
op-amp will switch from + Vsat to–Vsat.
 The diode will now get reverse biased and the capacitor starts charging exponentially to –Vsat
through the resistance R.
 The voltage at the (+) input terminal Is now– βVsat.
 When the capacitor voltage vC becomes just slightly more negative than– βVsat, the output of
the op-amp switches back to + Vsat.
 The capacitor C now starts charging to + Vsat through R until vC is 0.7V as capacitor C gets
clamped to the voltage.
 Various waveforms are shown in Fig.3.35 (a, b, c)

39
 Fig. 3.35 (a) Negative going Trigger Signal (b) Capacitor Waveform
(c) Output Voltage Waveform
 The pulse width T of mono stable multivibrator is calculated as follows:
 The general solution for a single time constant low pass RC circuit with V i, and Vf as initial
and final values is,
𝑉0 = 𝑉𝑓 + (𝑉𝑖 − 𝑉𝑓 )𝑒 −𝑡 ⁄𝑅𝐶
 For the circuit, Vf = –Vsat and Vi = VD (diode forward voltage).
 The output vC is,
𝑣𝐶 = −𝑉𝑠𝑎𝑡 + (𝑉𝐷 + 𝑉𝑠𝑎𝑡 )𝑒 −𝑡 ⁄𝑅𝐶
At t = T,
𝑣𝐶 = −𝛽𝑉𝑠𝑎𝑡
Therefore,
−𝛽𝑉𝑠𝑎𝑡 = −𝑉𝑠𝑎𝑡 + (𝑉𝐷 + 𝑉𝑠𝑎𝑡 )𝑒 −𝑡 ⁄𝑅𝐶
 After simplification, pulse width T is obtained as,
(1 + 𝑉𝐷 ⁄𝑉𝑠𝑎𝑡 )
𝑇 = 𝑅𝐶 ln
1−𝛽
where, β = R2/(R1+R2)
 If, Vsat>>VD and R1 = R2 so that β = 0.5, then,
𝑇 = 0.69𝑅𝐶
 For a mono stable operation, the trigger pulse width T p should be much less than T, the pulse
width of the mono stable multivibrator.
 The diode D2 is used to avoid malfunctioning by blocking the positive noise spikes that may be
present at the differentiated trigger input.
 It may be noted from Fig.3.35 (a) that capacitor voltage vC reaches its quiescent value VD at T'
> T.
 Therefore, it is essential that a recovery time T'–T be allowed to elapse before the next
triggering signal is applied.
 The circuit of Fig. 3.34 can be modified to achieve voltage to time delay conversion as in the
case of square wave generator.
 The mono stable multivibrator circuit is also referred to as time delay circuit as it generates a
fast transition at a predetermined time T after the application of input trigger.
 It is also called a gating circuit as it generates a rectangular waveform at a definite time and
thus could be used to gate parts of a system.

8. WAVEFORM GENERATORS

8.1. SQUARE WAVE GENERATOR:

 Same as an Astable Multivibrator. Also Schmitt Trigger.
8.2. TRIANGULAR WAVE GENERATOR:
14. With diagram explain the following op- amp applications of triangular wave generation.
(May-17, 18) (13)
 A triangular wave can be simply obtained by integrating a square wave as shown in Fig.3.36.

40
 Fig. 3.36 Triangular Waveform Generator
 It is obvious that the frequency of the square wave and triangular wave is the same as shown in
Fig.3.37.

Fig. 3.37 Output Waveform

 Although the amplitude of the square wave is constant at Vsat, the amplitude of the triangular
wave will decrease as the frequency increases.
 This is because the reactance of the capacitor C2 in the feedback circuit decreases at high
frequencies.
 A resistance R4 is connected across C2 to avoid the saturation problem at low frequencies as in
the case of practical integrator.
 Another triangular wave generator using lesser number of components is shown in Fig.3.38.

Fig. 3.38 Triangular Wave Generator Using Lesser Components

 It basically consists of a two level comparator followed by an integrator.
 The output of the comparator A1 is a square wave of amplitude Vsat and is applied to the (–)
input terminal of the integrator A2 producing a triangular wave.
41
 This triangular wave is fed back as input to the comparator Al through a voltage divider R2R3.
 Initially, let us consider that the output of comparator A1 is at + Vsat.
 The output of the integrator A2 will be a negative going ramp as shown in Fig.3.39.

Fig. 3.39 Output Waveforms

 Thus one end of the voltage divider R2R3 is at a voltage + Vsat and the other at the negative
going ramp of A2.
 At a time t = t1, when the negative going ramp attains a value of – Vramp, the effective voltage at
point P becomes slightly less than 0V.
 This switches the output of A1 from positive saturation to negative saturation level –Vsat.
 During the time when the output of A1 is at – Vsat, the output of A2 increases in the positive
direction.
 And at the instant t = t2, the voltage at point P becomes just above 0V, thereby switching the
output of A1 from –Vsatto + Vsat.
 The cycle repeats and generates a triangular waveform. It can be seen that the frequency of the
square wave and triangular wave will be the same.
 However, the amplitude of the triangular wave depends upon the RC value of the integrator A2,
and the output voltage level of A1.
 The output voltage of A1 can be set to desired level by using appropriate zener diodes.
 The frequency of the triangular waveform can be calculated as follows:
 The effective voltage at point P during the time when output of A1 is at +Vsat level is given by,
𝑅2
−𝑉𝑟𝑎𝑚𝑝 + [+𝑉𝑠𝑎𝑡 − (−𝑉𝑟𝑎𝑚𝑝 )]
𝑅2 + 𝑅3
 At t = t1, the voltage at point P becomes equal to zero. Therefore, from the above equation,
𝑅2
−𝑉𝑟𝑎𝑚𝑝 = − (+𝑉𝑠𝑎𝑡 )
𝑅3
 Similarly, at t = t2, when the output of A1 switches from – Vsatto + Vsat,
−𝑅2
𝑉𝑟𝑎𝑚𝑝 = (−𝑉𝑠𝑎𝑡 )
𝑅3
𝑅2
𝑉𝑟𝑎𝑚𝑝 = (𝑉 )
𝑅3 𝑠𝑎𝑡
 Therefore, peak to peak amplitude of the triangular wave is,
𝑣0 (𝑝𝑝) = +𝑉𝑟𝑎𝑚𝑝 − (−𝑉𝑟𝑎𝑚𝑝 )

42
 𝑅2
𝑣0 (𝑝𝑝) = 2 𝑉
𝑅3 𝑠𝑎𝑡
 The output switches from – Vramp to + Vramp in half the time period T/2. Putting the values in
1
the basic integration equation, (𝑣0 = − 𝑅𝐶 ∫ 𝑣𝑖 𝑑𝑡)
𝑇 ⁄2
1
𝑣0 (𝑝𝑝) = − ∫ −𝑉𝑠𝑎𝑡 𝑑𝑡
𝑅1 𝐶1 0
𝑉𝑠𝑎𝑡 𝑇
𝑣0 (𝑝𝑝) = ( )
𝑅1 𝐶1 2
or
𝑣0 (𝑝𝑝)
𝑇 = 2𝑅1 𝐶1
𝑉𝑠𝑎𝑡
 Putting the value of v0(pp) in the above equation,
4𝑅1 𝐶1 𝑅2
𝑇=
𝑅3
 Hence the frequency of oscillation f0 is,
1 𝑅3
𝑓0 = =
𝑇 4𝑅1 𝐶1 𝑅2
8.3. SINE WAVE GENERATOR:
15. With diagram explain the following op- amp applications of sine wave generation. (Dec – 12)
(16)
 As oscillator is basically a feedback circuit where a fraction vf of the output voltage v0 of an
amplifier is fed back to the input in the same phase.
 The block diagram of an oscillator is shown in Fig.3.40.

Fig. 3.40 Block diagram of a feedback oscillator

 For sustained oscillation, AVβ = 1.
 That is, magnitude condition │AVβ│ = 1 and the phase condition, angle AVβ = 0° or 360° must
be simultaneously satisfied in the circuit.
 There are different types of sine-wave oscillators available according to the range of frequency,
namely RC oscillators for audio frequency and LC oscillators for radio frequency range.
 Here we will discuss only two types of audio frequency RC oscillators.

43
16. Explain the working principle of RC phase shift sine wave generator using OPAMP and
derive the expression for ‘f’. (Dec – 14) (16)
8.3.1 Phase Shift Oscillator:

Fig. 3.41 Phase Shift Oscillator

 Figure shows a phase shift oscillator. The op-amp provides a phase shift of 180° as it is used in
the inverting mode.
 An additional phase shift of 180° is provided by the feedback RC network.
 The transfer function of the RC network can be easily calculated as,
𝑣𝑓 1
𝛽= =
𝑣0 1 + 6⁄𝑠𝑅𝐶 + 5⁄𝑠 𝑅2 𝐶 2 + 1⁄𝑠 3 𝑅2 𝐶 3
2

Let s = jω,
1
𝛽=
1 − 5(𝑓1 ⁄𝑓) − 𝑗[6(𝑓1 ⁄𝑓) − (𝑓1 ⁄𝑓)3 ]
2
1
where, 𝑓1 = 2𝜋𝑅𝐶
 For AVβ = 1, β should be real. So the imaginary term must be equal to zero, that is,
6(𝑓1 ⁄𝑓) − (𝑓1 ⁄𝑓)3 = 0
or
𝑓1 ⁄𝑓 = √6
 The frequency of the oscillation f0 is given by,
1
𝑓0 =
√6(2𝜋𝑅𝐶 )
Also, the loop gain AVβ = 1
or
𝐴𝑉
=1
1 − 5(𝑓1 ⁄𝑓0 )2
or
𝐴𝑉 ≥ −29
 That is the gain of the inverting op-amp should be atleast 29, or Rf = 29 R1.
 The gain AV is kept greater than 29 to ensure that variations in circuit parameters will not make
│AVβ│< 1, otherwise oscillations will die out.

44
  For low frequencies (<1 kHz), op-amp 741 may be used, however for high frequencies, LM
318 or LF 351 should be used.
8.3.2 Wien Bridge Oscillator:
 Another commonly used audio frequency oscillator is a Wien bridge oscillator.
 The circuit is shown in Fig.3.42.It may be noted that the feedback signal in this circuit is
connected to the (+) input terminal so that the op-amp is working as a non-inverting amplifier.

Fig. 3.42 Wien Bridge Oscillator

 Therefore, the feedback network need not provide any phase shift. The circuit can be viewed as
a Wien bridge with a series RC network in one arm and a parallel RC network in the adjoining
arm.
 Resistors R1 and Rf are connected in the remaining two arms. The condition of zero phase shifts
around the circuit is achieved by balancing the bridge.
 From the feedback network, the feedback factor β is,
𝑣𝑓 𝑅⁄(1 + 𝑗𝜔𝑅𝐶)
𝛽= =
𝑣0 [(𝑅 − 𝑗⁄𝜔𝐶 ) + 𝑅⁄(1 + 𝑗𝜔𝑅𝐶)]
𝑅
𝛽=
3𝑅 + 𝑗(𝜔𝑅2 𝐶 − 1⁄𝜔𝐶 )
For AVβ = 1, β must be real. That is the imaginary part is zero.
1
∴ 𝜔𝑅2 𝐶 − =0
𝜔𝐶
or
1
𝜔=
𝑅𝐶
The frequency of oscillation f0 is,
1
𝑓0 =
2𝜋𝑅𝐶
 At f0,β is equal to 1/3. Therefore, for sustained oscillation, the amplifier must have a gain of
precisely 3.
 However, from practical point of view, AV may be slightly less or greater than 3.
 For AV< 3, the oscillations will either die down or fail to start when power is first applied.
 And, for AV> 3, the oscillations will be growing. This problem is eliminated by a practical
Wien bridge oscillator with adaptive negative feedback as shown in Fig.3.43.

45
 Fig. 3.43 Practical Wien Bridge Oscillator with adaptive negative feedback
 In this circuit, resistor R4 is initially adjusted to give a gain so that oscillations start.
 The output signal grows in amplitude until the voltage across R3 approaches the cut-in voltage
of the diode.
 As the diodes begin to turn-on (one for the positive half cycle and the other for the negative
half cycle), the effective feedback resistance R f decreases because the diode is in parallel with
the resistance R3.
 This will reduce the gain of the amplifier which in turn lowers the output amplitude.
 Hence sustained oscillations can be obtained. Further, if the output signal falls, the diodes
would begin to turnoff thereby increasing R f which in turn increases gain.

9. CLIPPERS
17. Draw a circuit of a clipper which will clip the input signal below the reference voltage. (Dec –
14, 15) (May – 17) (8)
(or)
Elaborate with neat circuit diagram, and input/ output waveforms, the operation of positive
clipper. (Nov/Dec 2019) (6)

 A precision diode may also be used to clip-off a certain portion of the input signal to obtain a
desired output waveform.
 Fig. 44 shows a positive clipper. The clipping level is determined by the reference voltage V ref
and could be obtained from the positive supply voltage V+.

Fig. 3.44 Positive Clipper Circuit

46
 The input and output waveforms are, shown in Fig. 3.45 (a). It can be seen that the portion of
the output voltage for v0>Vref are clipped off.

Fig. 3.45 Input and output Waveforms for (a) positive Vref (b) Negative Vref
 For input voltage vi<Vref, diode D conducts. The op-amp works as a voltage follower and
output v0 follows input vi till vi≤Vref. When vi is greater than Vref, the output v0A of the op-amp
is large enough to drive D into cut-off.
 The op-amp operates in the open-loop and output voltage v0 = Vref.
 However, if Vref is made negative, then the entire output waveform above Vref will get clipped
off as shown in fig.3.45 (b).
 The positive clipper of Fig. 44 can be easily converted into a negative clipper by reversing
diode D and changing the polarity of the Vref, as shown in Fig. 3.46.

Fig. 3.46 Negative Clipper Circuit

 The negative clipper clips off the negative parts of the input signal below the reference voltage.
 The circuit diagram of a negative clipper and the expected waveforms for negative Vref, and
positive Vref, are shown in Fig.3.47 (a, b).

47
 Fig. 3.47 Input-output waveforms for negative and positive Vref

10. CLAMPERS

18. With circuit diagram explain the op- amp applications of clamper. (May – 14, Dec – 14, May
– 17)
(or)
Elaborate with neat circuit diagram, and input/ output waveforms, the operation of peak
clamper. (Nov/Dec 2019) (6)
 The clamper is also known as d.c. inserter or restorer. The circuit is used to add a desired d.c.
level to the output voltage.
 In other words, the output is clamped to a desired d.c. level. If the clamped d.c. level is
positive, it is called positive clamper.
 Similarly if the clamped d.c. level is negative, the clamper is called negative clamper.
 Fig. 48 shows a clamper with a variable positive d.c. voltage applied at the (+) input terminal.
 This circuit clamps the peaks of the input waveform and therefore is also called a peak
clamper.

Fig. 3.48 Peak Clamper Circuit

 The output voltage in the circuit is the net result of ac and dc input voltages applied to the (–)
and (+) input terminals respectively.
48
  Let us first see the effect of Vref applied at the (+) input terminal. For positive Vref, the voltage
v' is also positive, so that the diode D is forward biased.
 The circuit operates as a voltage follower and therefore output voltage v0 = + Vref.
 Now consider the ac input signal vi = Vm sin ωt applied at the (–) input terminal.
 During the negative half cycle of vi, diode D conducts. The capacitor C1 charges through diode
D to the negative peak voltage Vm.
 However, during the positive half cycle of vi, diode D is reverse biased. The capacitor retains
its previous voltage Vm.
 Since this voltage Vm is in series with the ac input signal, the output voltage now will be vi +
Vm.
 The total output voltage is, therefore, Vref+ vi + Vm.
 The input and output waveforms are shown in Fig.3.49 (a).

Fig. 3.49 (a) Waveforms for + Vref (b) Waveforms or – Vref

 It is possible to obtain negative peak clamping by reversing the diode D and using a negative
reference voltage –Vref.
 The expected waveforms are shown in Fig.3.49 (b). The resistor R is used for protecting the
op-amp against excessive discharge currents from capacitor C1 especially when the d.c. supply
voltages are switched off.
11. PEAK DETECTORS

19. Explain the following application of operational amplifier as a peak detector. (May – 14, Dec
– 14)
 The function of a peak detector is to compute the peak value of the input.
 The circuit follows the voltage peaks of a signal and stores the highest value (almost
indefinitely) on a capacitor.
 If a higher peak signal value comes along, this new value is stored.
 The highest peak value is stored until the capacitor is discharged.

49
 Fig. 3.50 Positive peak detector
 Consider the circuit of Fig.3.50. When input vi exceeds vC, the voltage across the capacitor, the
diode D is forward biased and the circuit becomes a voltage follower.
 Consequently, the output voltage v0 follows vi as long as vi exceeds vC.
 When vi drops below vC, the diode becomes reverse-biased and the capacitor holds the charge
till input voltage again attains a value greater than vC.
 Fig. 51 shows the voltage wave shape for the positive peak detector.

Fig. 3.51 Output v0 corresponding to arbitrary input vi

 It may be noted that the peak at time t' is missed, the reason is obvious.
 The circuit can be reset, that is, capacitor voltage can be made zero by connecting a lower
leakage MOSFET switch across the capacitor.
 The circuit can be modified to hold the lowest or most negative voltage of a signal by reversing
the diode.
 Peak detectors find application in test and measurement instrumentation as well as in amplitude
modulation (AM) communication.

12. S/H CIRCUIT

20. Draw sample and hold circuit and explain its operation. (Dec – 14, 15) (8)
 A sample and hold circuit samples an input signal and holds on to its last sampled value until
the input is sampled again.
 This type of circuit is very useful in digital interfacing and analog to digital and pulse code
modulation systems.
 One of the simplest practical sample and hold circuit configuration is shown in Fig.3.52.

50
 Fig. 3.52 Sample and Hold Circuit
 The n-channel E-MOSFET works as a switch and is controlled by the control voltage vC and
the capacitor C stores the charge.
 The analog signal vi to be sampled is applied to the drain of E-MOSFET and the control
voltage vC is applied to its gate.
 When vC is positive, the E-MOSFET turns on and the capacitor C charges to the instantaneous
value of input vi with a time constant [(R0 + rDS (on)] C.
 Here R0 is the output resistance of the voltage follower A1 and rDS (on) is the resistance of the
MOSFET when on.
 Thus the input voltage vi appears across the capacitor C and then at the output through the
voltage follower A2.
 The waveforms are as shown in Fig.3.53.

Fig. 3.53 Input and Output Waveforms

 During the time when control voltage vC is zero, the E-MOSFET is off.
 The capacitor C is now facing the high input impedance of the voltage follower A2 and hence
cannot discharge.
 The capacitor holds the voltage across it.
 The time period TS, the time during which voltage across the capacitor is equal to input voltage
is called sample period.

51
  The time period TH of vC during which the voltage across the capacitor is held constant is
called hold period.
 The frequency of the control voltage should be kept higher than (at least twice) the input so as
to retrieve the input from output waveform.
 A low leakage capacitor such as Polystyrene, Mylar, or Teflon should be used to retain the
stored charge.
 Specially designed sample and hold 108 of make Harris semiconductor HA2420, National
semiconductor such as LF198, LF398 are also available.

Fig. 3.54 Typical Connection Diagram

 A typical connection diagram of the LF398 is shown in Fig. 3.54. It may be noted that the
storage capacitor C is connected externally.

13. D/A CONVERTERS

21. With the circuit of neat diagram explain the operation of R/2R D/A converter. (May-15) (8)
( or )
With the circuit diagram explain the working principle of R-2R converter and binary weighted
converter. (Nov-17) (13)
(or)
Discuss the application of Op-amps, with necessary equivalent circuits and expressions for D/A
converters (Apr/May 2019)
 Digital to analog converters converts digital signals into analog signals.

Fig. 3.55 Schematic diagram of a DAC

 The output voltage of n-bit digital to analog converter is given by,
𝑉𝑜 = 𝑉𝑅 (𝑑1 2−1 + 𝑑2 2−2 + ⋯ … … … … … . + 𝑑𝑛 2−𝑛 )
where,
𝑉𝑅 = Reference voltage
𝑑1 , 𝑑2 , … … … , 𝑑𝑛 = n – bit binary word
𝑑1 = MSB with weight of 𝑉𝑅 ⁄2
52
 𝑑2 = LSB with weight of 𝑉𝑅 ⁄2𝑛

13.1 Types:
1. Binary weighted resistor DAC
2. R-2R ladder
3. Inverted R-2R ladder.
13.1.1 Binary Weighted Resistor DAC:

 The binary weighted resistor DAC uses operational amplifier to sum n binary weighted
currents derived from a reference voltage 𝑉𝑅 via current scaling resistors 2R, 4R, 8R … 2nR.

Fig. 3.56 A simple weighted resistor DAC

 The switch positions are controlled by digital inputs. When the digital input is one, the
corresponding switch is closed and digital input is zero.
 The operational amplifier is used as a summing amplifier. Due to the high input impedance of
op-amp, summing current will flow through feedback resistor Rf.
 The total current is,
𝐼𝑇 = 𝐼1 + 𝐼2 + 𝐼3 … … . +𝐼𝑛
 The output voltage is the voltage drop across 𝑅𝑓 and it is given as,
𝑉0 = −𝐼𝑇 𝑅𝑓
𝑉0 = −(𝐼1 + 𝐼2 + 𝐼3 … … . +𝐼𝑛 )𝑅𝑓
𝑉𝑅 𝑉𝑅 𝑉𝑅 𝑉𝑅
𝑉0 = −(𝑑1 + 𝑑2 + 𝑑3 … … . +𝑑𝑛 𝑛 )𝑅𝑓
2𝑅 4𝑅 8𝑅 2 𝑅
𝑉𝑅
𝑉0 = − (𝑑1 2−1 + 𝑑2 2−2 + ⋯ … … … … … . + 𝑑𝑛 2−𝑛 ) 𝑅𝑓
𝑅
When𝑅𝑓 = 𝑅, the output voltage becomes
𝑽𝒐 = −𝑽𝑹 (𝒅𝟏 𝟐−𝟏 + 𝒅𝟐 𝟐−𝟐 + ⋯ … … … … … . + 𝒅𝒏 𝟐−𝒏 )
 From this equation, analog output voltage is directly proportional to the input digital data.
 The analog output voltage is therefore positive staircase as shown in Fig. 57 for a 3-bit
weighted resistor DAC.
 It may be noted that,
 Although the op-amp in Fig. 3.56 is connected in inverting mode, it can also be
connected in non-inverting mode.
 The op-amp is simply working as a current to voltage converter.

53
  The polarity of the reference voltage is chosen in accordance with the type of
the switch used.
 The accuracy and stability of a DAC depends on the accuracy of the resistors and the tracking
of each other with temperature.

Fig. 3.57 Transfer characteristics of a 3-bit DAC

Disadvantages:
 Wide range of Resistor values is required.
 It is observed that for better resolution, the input binary word length has to be increased.
Thus, as the number of bit increases, the resistance value increases.
13.1.2 R-2R ladder DAC:
22. with neat diagram, explain the working principle of R-2R ladder type DAC. (May – 17) (8)
 R-2R ladder D/A converters use only two resistor values.
 This avoids resistance spread drawback of binary weighted D/A converter.
 Like binary resistor DAC, it also uses shunt resistors to generate n binary weighted currents; it
uses voltage scaling and identical resistors instead of resistor scaling and common voltage
reference used in binary weighted resistor DAC.
 Voltage scaling requires an additional set of voltage dropping series resistance between
adjacent nodes.

Fig. 3.58 R-2R ladder DAC

 Each bit of the binary word connects the corresponding switch either to ground or to the
inverting input terminal of the op-amp which is at the virtual ground.
 Both the positions of switches are at ground potential, the current flowing through resistance is
constant and it is independent of switch position.
54
 𝑉
𝐼1 = 𝑅⁄2𝑅
𝑉𝑅⁄
𝐼2 = 2 = 𝑉𝑅
2𝑅 4𝑅
𝑉𝑅⁄
𝐼3 = 4 = 𝑉𝑅
2𝑅 8𝑅
 The output voltage V0 is,
𝑉0 = −𝐼𝑇 𝑅𝑓
𝑉0 = −𝑅𝑓 (𝐼1 + 𝐼2 + 𝐼3 … … . +𝐼𝑛 )
𝑉𝑅 𝑉𝑅 𝑉𝑅 𝑉𝑅
𝑉0 = − [𝑑1 + 𝑑2 + 𝑑3 … … . +𝑑𝑛 𝑛 ]
2𝑅 4𝑅 8𝑅 2 𝑅
𝑅𝑓
𝑉0 = −𝑉𝑅 (𝑑 2−1 + 𝑑2 2−2 + ⋯ … … … … … . + 𝑑𝑛 2−𝑛 )
𝑅 1
 When Rf =R, the output voltage is,
𝑽𝒐 = −𝑽𝑹 (𝒅𝟏 𝟐−𝟏 + 𝒅𝟐 𝟐−𝟐 + ⋯ … … … … … . + 𝒅𝒏 𝟐−𝒏 )

14 A/D CONVERTERS USING OP-AMPS

23. Explain the successive approximation type ADC with its characteristics. (Dec – 12) (May-18)
(9)(Nov/Dec 2019) (8, 11)
(or)
Explain the principle of operation of A/D converter. (May – 11) (8)
(or)
Explain the basic operation of A/D converter utilizing D/A converter. (May – 15) (8)
(or)
Discuss the application of Op-amps, with necessary equivalent circuits and expressions for A/D
converters (Apr/May 2019)

 An electronic integrated circuit which transforms a signal from analog (continuous) to digital
(discrete) form is known as analog to digital converter.
14.1 Types of A/D Converters:
 Dual Slope A/D Converter.
 Successive Approximation A/D Converter.
 Flash A/D Converter.

14.1.1 Successive Approximation Type Analog to Digital Converter:

 An eight bit converter which requires 8 clock pulses to obtain digital output.
 It consists of successive approximation register (SAR), operational amplifier, and D/A
converter.
 SAR is used to find the required value of each bit by trial and error.

55
 Fig. 3.59 Functional diagram of Successive Approximation ADC
 When start command is received the SAR sets d1=1 for eight bit code and all other to zero.
 The output Vd from DAC is compared with analog input Va. If Va>Vd, then 10000000 is less
than correct digital representation.
 The MSB will remains at ‘1’ and next bit is made ‘1’ and further tested.
 When Va<Vd, zero is introduced to next LSB and process repeats. It repeats till it receives EOC
command.
CORRECT SIGNAL CONVERSION OUTPUT
11010100 10000000 1
11000000 1
11100000 0
11010000 1
11011000 0
11010100 1
11010110 0
11010100 0
11010100

Fig. 3.60 The D/A output voltage is seen to become successively closer to the actual analog input
voltage
14.1.1.1 Advantages:
 High resolution.
 It is very versatile.
 High Speed.
14.1.1.2 Application:

56
  Data acquisition systems.
14.1.2 Flash type ADC:
24. Explain the following application of operational amplifier as a Flash Type A/D Converter.(8)
(Dec – 16)

 It is the simplest, fastest and most expensive technique.

 It consists of resistive divider network, 8 comparators and a 8-line to 3-line encoder for a 3 –
bit A-D converter.
 If both inputs were of equal voltage a small amount of hysteresis is built into comparator.
 The main purpose is to compare the analog input voltage Va with each of the node voltage.
 The resistor voltage available at node is divided equally between V R and ground.

Fig. 3.62 Comparator and its truth table

Fig. 3.61 Flash type A/D Converter

 The truth table for the flash type A-D converter is shown in Fig.3.63.
57
  The conversion speed is high as the conversion takes place simultaneously rather than
sequentially.

Fig. 63 Truth table for Flash type A/D Converter

 In general, the number of comparators required is 2n – 1 where n is the desired number of bits.
14.1.2.1 Advantages:
 High speed operation conversion takes place.
 Conversion time is 100ns or less.
14.1.2.2 Disadvantages:
 Designing becomes complex for higher value.
 For each added bit, size of comparator is doubled.
14.1.2.3 Applications:
 High speed fiber optic communication, digital storage oscilloscope.
14.1.3 Stair case ramp type:
 A stair case ramp type converter consists of comparator, DAC, AND gate and a counter.
 The basic principle is that the input signal Va is compared with an internal stair case voltage Vd,
generated by a series circuit consisting of a pulse generator (clock), a counter counting the
pulses and a digital to analog converter, converting the counter output into a d.c. signal.
 As soon as Vd is equal to Va, the input comparator closes a gate between the clock and counter,
the counter stops and its output is shown on the display.

Fig. 3.64 Counter type A/D Converter

14.1.3.1 Operation:
 The clock generates pulses continuously. At the start of a measurement, the counter is reset at 0
so that the output of the digital to analog converter is also zero.
 If Va is not equal to zero, the input comparator applies an output voltage that opens the gate so
that the clock pulses are passed on to the counter through gate.

58
  The counter starts counting and the DAC starts to produce an output voltage increasing one
small step at each count of the counter.
 The result is a stair case voltage applied to the second input of the comparator.
 This process continues until the staircase voltage is equal to or slightly greater than the input
voltage Va.

Fig. 3.64 D/A output staircase waveform

 When Vd ≥ Va, the output voltage of the input comparator changes state or polarity, so that the
gate closes and counter is stopped.
 The display unit shows the result of the count.
14.1.4 Servo tracking ADC:

Fig. 3.65 A Tracking A/D Converter

 It has an up-down counter which counts in both directions.
 Analog output of DAC is 𝑉𝑑 which is compared with analog input 𝑉𝑎 .
 If 𝑉𝑎 > 𝑉𝑑 output of comparator becomes 1 and counter counts up for each incoming clock
pulse with increased output and the counter counts one up till the maximum value.
 If the maximum value is attained it starts to count one down till the LSB value.
 It repeats back forth for each increase in value as analog input changes slowly for rapid
increase in input, it cannot able to change and becomes error.

59
 Fig. 3.66 Waveforms associated with tracking A/D Converter
14.1.4.1 Advantage:
 The process is simple.
14.1.4.2 Disadvantage:
 It needs time.

14.1.5 Dual slope A/D conversion:

25. Explain the operation of dual slope ADC. (May – 14, Dec – 14)
 It is an indirect method.
 An analog voltage and a reference voltage are converted into time periods by an integrator and
then measured by a counter.
 The speed of this conversion is slow but the accuracy is high.
14.1.5.1 Construction:
 It consists of an integrator (ramp generator), comparator, binary counter, output latch and a
reference voltage.
 The ramp generator input is switched between the analog input voltage 𝑉𝑖 and a negative
reference voltage – VR.

Fig. 3.67 Functional diagram of Dual Slope ADC

 The analog switch is controlled by the MSB of the counter.
 When the MSB is logic 0, the voltage being measured is connected to the ramp generator input.
60
  When MSB is logic 1, the negative reference voltage is connected to the ramp generator.
 At time t=0, analog switch S is connected to the analog input voltage 𝑉𝑖 the analog input
voltage integration begins.
 The output voltage of the integrator is,
−1 𝑡 −𝑉𝑖 𝑡
𝑉𝑜𝑖 = ∫ 𝑉𝑖 𝑑𝑡 =
𝑅1 𝐶1 0 𝑅1 𝐶1
where 𝑅1 𝐶1 is the integrator time constant.
𝑉𝑖 is assumed constant over the integration time period.

Fig. 3.68 Integrated output waveform for the dual slope ADC
 At the end of 2n clock periods MSB of the counter goes high.
 As a result the output of the flip-flop goes high, which causes analog switch S to be switched
from Vi to – VR.
 At this very same time the binary counter which has gone through its entire count sequence is
reset.
 The negative input voltage −𝑉𝑅 connected to the input of integrator causes the integrator output
to ramp positive.
 When integrator output reaches zero, the comparator output voltage goes low, which disables
the clock AND gate.
 This stops the clock pulses reaching the counter, so that the counter will be stopped at a count
corresponding to the number of clock pulses in time 𝑡2 .
 The charge voltage is equal to discharge voltage,
𝑉𝑖 𝑡1 𝑉𝑅 𝑡2
=
𝑅1 𝐶1 𝑅1 𝐶1
𝑉𝑖 𝑡1 = 𝑉𝑅 𝑡2
𝑉𝑡
𝑡2 = ( 𝑖 1⁄𝑉 )
𝑅
𝑉𝑡
Digital output= (counts/second) t2 Digital output= (counts/ second) ( 𝑖 1⁄𝑉 )
𝑅
14.1.5.2Advantages:
 It is highly accurate, its cost is low.
 It is immune to temperature caused variations in R 1 and C1.
14.1.5.3 Disadvantage:
 Speed is low.

61