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Microprocessors and Microcontrollers

Assignment 10- Week 10
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15 M
______________________________________________________________________________

QUESTION 1:
THUMB instruction size is

a) 32 bit;

b) 64 bit;

c) 16 bit;

d) 128 bit

Correct Answer: C

Detailed Solution:

QUESTION 2:
Which of the following features are correctly mentioned with respect to an AVR AT90S2313
microcontroller?
a) 2K bytes of In-System Programmable Flash, 128 bytes SRAM;
b) 2K bytes of In-System Programmable Flash, 256 bytes SRAM;
c) 4K bytes of In-System Programmable Flash, 128 bytes SRAM;
d) 4K bytes of In-System Programmable Flash, 256 bytes SRAM
Correct Answer: a

Detailed Solution:

QUESTION 3:
How many general purpose registers are present in AT90S2313 micro controller?
a) 16;
b) 8;
c) 32;
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d) 64
Correct Answer: c

Detailed Solution:

QUESTION 4:
The encoded op-code 0x0CC8 corresponds to which of the following instructions in an
AT90S2313 microcontroller?
a) ADD R0, R10;
b) ADD R12, R6;
c) ADD R10, R0;
d) ADD R6, R8

Correct Answer: d

Detailed Solution:

0x0CC8 = 0000 1100 1100 1000

5 blue bits 00011 distinguish this as an add instruction
5 red bits 00110 indicates register 6, it is the first operand register.
The 5 green bits 01000 indicates register 8 is the second operand register.

QUESTION 5:
The widths of the Output Compare Registers in an AVR microcontroller for Timer 0 (OCR0)
and Timer 1 (OCR1), respectively are
a) OCR0: 8 bits, OCR1: 8 bits;
b) OCR0: 8 bits, OCR1: 16 bits;
c) OCR0: 16 bits, OCR1: 8 bits;
d) OCR0: 16 bits, OCR1: 16 bits
Correct Answer: b

Detailed Solution:

OCR0: 8 bits; Timer 0

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OCR1: 16 bits; Timer 1

QUESTION 6:
Which of the following combinations should be used for the best performance, with respect to an
ARM processor?

a) 16-bit memory and ARM instruction set;

b) 32-bit memory and ARM instruction set;
c) 16-bit memory with THUMB code;

d) 32-bit memory with THUMB code

Correct Answer: b

Detailed Solution:

QUESTION 7:
Which of the following registers can be accessed using THUMB instructions?

a) R0-R7;

b) R20-R27;

c) P0-P7;

d) P20-P27

Correct Answer: a

Detailed Solution:

THUMB instructions have unlimited access to registers R0-R7 and R13-R15

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QUESTION 8 :
Which of the following combination is best choice for achieving power efficiency and low cost
in ARM microcontrollers?

a) 32-bit memory and ARM instruction set;

b) 16-bit memory and ARM instruction set;

c) 16-bit memory and THUMB code;

d) None of the above

Correct Answer: c

Detailed Solution:
For best cost and power efficiency, use 16-bit memory with THUMB code.

QUESTION 9:
What is the ROM size of ATTint11 microcontroller?
a) 1k flash memory;
b) 2k flash memory;
c) 4k flash memory;
d) 8k flash memory

Correct Answer: a

Detailed Solution: Smallest microcontroller is the ATTiny11 with 1k flash ROM

QUESTION 10:
The Cortex-M3 processor, based on the _____________ architecture.
a) ARMv7-A;
b) ARMv7-R;
c) ARMv7-M;
d) ARMv7-C
Correct Answer: c

Detailed Solution:
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The Cortex-M3 processor is the first ARM processor based on the ARMv7-M architecture and
has been specifically designed to achieve high system performance in power- and cost-sensitive
embedded applications, such as microcontrollers, automotive body systems, industrial control
systems and wireless networking, while significantly simplifying programmability to make the
ARM architecture an option for even the simplest applications.

QUESTION 11:
PIC18F series microcontrollers has _______________.

a) 12-bit address bus for program memory;

b) 21-bit address bus for data memory;

c) 21-bit address bus for program memory;

d) 16-bit address bus for program memory

Correct Answer: c

Detailed Solution:

PIC18F series microcontrollers has 21-bit address bus for program memory and 12-bit address
bus for data memory

QUESTION 12:
Which of the following statements is true regarding BX and BLX instructions in ARM
architecture?

A. BX and BLX instructions are used for data transfer operations.;

B. BX and BLX instructions can only be used in ARM mode.;
C. BX instruction can be used to switch between ARM and THUMB instruction modes.;
D. BLX instruction can be used to switch between FIQ and IRQ modes.

Correct Answer: C

Detailed Solution:

BX and BLX are instructions in the ARM architecture that are used to change the program flow
by branching to a new address.
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The BX (Branch and Exchange) instruction changes the instruction set state by switching
between ARM and THUMB instruction modes. When used in ARM mode, the BX instruction is
used to branch to a new address and switch between ARM and THUMB instruction modes,
based on the LSB of the address. In THUMB mode, the BX instruction can be used to branch to
any address in the 16MB address space.

The BLX (Branch and Link Exchange) instruction is similar to BX, but also stores the address of
the next instruction in the link register (LR). This allows for a return to the instruction following
the BLX instruction, similar to a subroutine call. Like BX, BLX can also switch between ARM
and THUMB instruction modes.

Both BX and BLX instructions are particularly useful for implementing function calls and
returning from them, as well as for implementing interrupt handlers, as they allow switching
between different instruction modes and saving the return address in the LR register.

QUESTION 13:
How much In-system programmable flash memory is available in the AVR AT90S2313
microcontroller?
A. 1 KB;
B. 2 KB;
C. 4 KB;
D. 8 KB
Correct Answer: B

Detailed Solution:

QUESTION 14:
Smallest micro controller in AVR family is

a) ATMEGA128;
b) ATTiny11;
c) ATtiny22;

d) ATtiny24
Correct Answer: b
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Detailed Solution:

Smallest microconroller is the ATTiny11 with 1k flash ROM, no RAM and 6 I/O pins.

QUESTION 15:
In ARM7, what is the vector address of IRQ interrupt?
a) 0x00000004;
b) 0x00000008;
c) 0x0000000C;
d) 0x00000018
Correct Answer: D

Detailed Solution:
In ARM7 architecture, the vector address of the IRQ (Interrupt Request) interrupt is fixed at
address 0x00000018. This means that when an IRQ interrupt occurs, the processor looks for the
interrupt handler code at this address in the interrupt vector table.