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Full Adder

The document describes the implementation of a full adder using Verilog, which includes an OR gate and half adders. The full adder combines the outputs of two half adders and an OR gate to compute the sum and carry outputs. Additionally, a testbench is provided to simulate the full adder's functionality with various input combinations.

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akashbani86
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20 views2 pages

Full Adder

The document describes the implementation of a full adder using Verilog, which includes an OR gate and half adders. The full adder combines the outputs of two half adders and an OR gate to compute the sum and carry outputs. Additionally, a testbench is provided to simulate the full adder's functionality with various input combinations.

Uploaded by

akashbani86
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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or gate

module or_gate(
input a,
input b,
output y
);

assign y = a | b;

endmodule

Half adder
module ha(
input a,b,
output sum,carry
);

assign sum=a^b;
assign carry=a&b;
endmodule

full adder
// Code your design here
`include "or_gate.v"
`include "ha.v"

module fa(
input a,b,cin,
output sum,carry
);

wire w1,w2,w3;
ha u1(.a(a), .b(b),.sum(w1),.carry(w2));
ha u2(.a(w1), .b(cin),.sum(sum),.carry(w3));

or_gate u3(.a(w2), .b(w3),.y(carry));

endmodule

testbench
// Code your testbench here
// or browse Examples
module tb;
reg a,b,cin;
wire s,carry;

fa ut (
.a(a),.b(b),.cin(cin),.sum(s),.carry(carry)
);

initial begin
$dumpfile("fa.vcd");
$dumpvars(1);
end
initial begin
a=1 ; b=0; cin=1; #10;
a=0 ; b=1; cin=0; #10;
a=1 ; b=0; cin=1; #10;
a=0 ; b=1; cin=0; #10;
$finish;
end
endmodule

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