Module - I Part 2

Basic Processing Unit

Fundamental concepts
Instruction cycle
Execution of a complete instruction
Single bus and multiple bus organization
 Overview
• Instruction Set Processor (ISP) or Processor
• Central Processing Unit (CPU)
• A typical computing task consists of a series of steps specified by a sequence
of machine instructions that constitute a program.
• An instruction is executed by carrying out a sequence of more rudimentary
operations.
 Fundamental Concepts

• Processor fetches one instruction at a time and perform the

operation specified.
• Instructions are fetched from successive memory locations
until a branch or a jump instruction is encountered.
• Processor keeps track of the address of the memory location
containing the next instruction to be fetched using Program
Counter (PC).
• Instruction Register (IR)- Instructions fetched from memory
are kept in IR of CPU
 Executing an Instruction
❖ Fetch phase INSTRUCTION CYCLE
1. Fetch the contents of the memory location pointed to by the
PC. The contents of this location are loaded into the IR.
IR ← [[PC]]
2. Assuming that the memory is byte addressable, increment the
contents of the PC by 4.
PC ← [PC] + 4
❖ Execution phase
3. Carry out the actions specified by the instruction in the IR
 Internal Processor Organization

MDR HAS
TWO
INPUTS
AND TWO
OUTPUTS

Single-bus Organization Of The Datapath Inside A Processor

 Internal organization of the
processor

• ALU
• Registers for temporary storage
• Various digital circuits for executing different
micro operations. ( gates, MUX, decoders,
counters)
• Internal data path for movement of data between
ALU and registers.
Internal organization
PC: Program Counter
of the processor
❖ Keeps track of execution of a program
❖ Contains the memory address of the next instruction to be
fetched and executed.
MAR: Memory Address Register
❖ Holds the address of the location to be accessed.
❖ I/P of MAR is connected to Internal bus and an O/p to external
bus.
MDR: Memory Data Register
❖ Contains data to be written into or read out of the addressed
location.
❖ It has 2 inputs and 2 Outputs.
❖ Data can be loaded into MDR either from memory bus or from
internal processor bus.
The data and address lines are connected to the internal bus via MDR
and MAR
 Internal organization of the processor
Registers: The processor general purpose registers R0 to Rn-1 are
provided for use by programmer, vary considerably from one
processor to another.
❖ Special purpose registers - index & stack registers.
❖ Registers Y,Z &TEMP are temporary registers used by
processor during the execution of some instruction.
Multiplexer: Select either the output of the register Y or a
constant value 4 to be provided as input A of the ALU.
❖ Constant 4 is used by CPU to increment the contents of PC.
ALU: Used to perform arithmetic and logical operation.
Data Path:
❖ The registers, ALU and interconnecting bus are collectively
referred to as the data path.
An instruction can be executed by
performing one or more of the
following operations :
1) Transfer a word of data from one processor register to
another or to the ALU. eg : MOVE Ri, Rj
2) Perform an arithmetic or a logic operation and store the
result in a processor register. Eg : Add Ri, Rj, Rk
3) Fetch the contents of a given memory location and load
them into processor register. Eg : Move [Ri], Rj
4) Store a word of data from a processor register into a given
memory location.
eg: Move Ri,[Rj]
 An instruction can be executed by
performing one or more of the
following operations :

1) Transfer a word of data from one processor register to

another or to the ALU eg : MOVE R1, R4
 1.Register Transfers

MOVE R1, R4

1. R1out=1.
2. R4in=1
• The input and output gates for register Ri are controlled by
signals Rin and Rout .

• Riin Is set to 1 – data available on common bus are loaded into

Ri.

• Riout Is set to 1 – the contents of register Ri are placed on the

bus.

• Riout Is set to 0 – the bus can be used for transferring data

from other registers .
Data transfer between two registers:
Example
Transfer the contents of R1 to R4.
1. Enable output of register R1 by setting R1out=1. This
places the contents of R1 on the processor bus.
2. Enable input of register R4 by setting R4in=1. This
loads the data from the processor bus into register R4.

R1out=1.
R4in=1.
 Register Transfers
• All operations and data transfers are controlled by the processor clock.

Fig : Input and output gating for one register bit.

An instruction can be executed by
performing one or more of the
following operations :
1) Transfer a word of data from one processor register to
another or to the ALU. eg : MOVE Ri, Rj
2) Perform an arithmetic or a logic operation and store the
result in a processor register. Eg : Add Ri, Rj, Rk
3) Fetch the contents of a given memory location and load
them into processor register. Eg : Move [Ri], Rj
4) Store a word of data from a processor register into a given
memory location.
eg: Move Ri,[Rj]
2. Performing an Arithmetic or Logic
Operation
• The ALU is a combinational circuit that has no internal
storage.
• ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
• What is the sequence of operations needed to add the
contents of register R1 to those of R2 and store the
result in R3?
Add R1, R2, R3
 Sequence of Operations : Add R1, R2, R3

1. R1out,Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
 Sequence of Operations : Add R1, R2, R3
Step 1:
• Output of the register R1 and Input of the register Y are enabled, causing the contents of R1
to be transferred to Y.
Step 2:
• The multiplexer’s select signal is set to select Y, causing the multiplexer to gate the contents of
register Y to input A of the ALU.
• At the same time, the contents of register R2 are gated onto the bus and hence, to input B.
• The function performed by the ALU depends on the signals applied to its control lines.
• This sum is loaded into register Z.
Step 3: The contents of Z are transferred to the destination register R3.
An instruction can be executed by
performing one or more of the
following operations :
1) Transfer a word of data from one processor register to
another or to the ALU. eg : MOVE Ri, Rj
2) Perform an arithmetic or a logic operation and store the
result in a processor register. Eg : Add Ri, Rj, Rk
3) Fetch the contents of a given memory location and load
them into processor register. Eg : Move [Ri], Rj
4) Store a word of data from a processor register into a given
memory location.
eg: Move Ri,[Rj]
3. Fetching a Word from
Memory
3. Fetching a Word from Memory
• The response time of each memory access varies

• To accommodate this, the processor waits until it receives an

indication that the requested read operation has been completed

• (control signal -Memory-Function-Completed, MFC = 1).

 3. Fetching a Word from
Memory
• Example : Move (R1), R2

1. MAR ← [R1]
2. Start a Read operation on
the memory bus
3. Wait for the MFC response
from the memory
4. Load MDR from the
memory bus
5. R2 ← [MDR]
3. Fetching a Word from
Memory
An instruction can be executed by
performing one or more of the
following operations :
1) Transfer a word of data from one processor register to
another or to the ALU. Eg : MOVE Ri, Rj
2) Perform an arithmetic or a logic operation and store the
result in a processor register. Eg : Add Ri, Rj, Rk
3) Fetch the contents of a given memory location and load
them into processor register. Eg : Move [Ri], Rj
4) Store a word of data from a processor register into a given
memory location. Eg: Move Ri,[Rj]
4.Storing a word in memory
Example : Move R2,(R1)
1. The desired address is loaded into MAR
2. Data to be written are loaded into MDR and Write
command is issued.
***************************************
1. R1out,MARin
2. R2out,MDRin,Write
3. MDRoutE, , WMFC
 Execution of a Complete Instruction
Ex-1 : Add R1,R2,R3
Fetch Phase
1. Fetch the instruction from the memory and decode
2. Fetch the operands
3. Perform the addition Execute Phase
4. Load the result into R3
Execution of a Complete Instruction
Add R1,R2,R3

Step Action
Fetch Phase
1 PCout, MARin,Read,Select4,Add,Zin
2 Zout,PCin,Yin,WMFC
3 MDRout,IRin
4 R1out,Yin
5 R2out, SelectY, Add, Zin
6 Zout, R3in ,End

Execute Phase
 Execution of a Complete Instruction
Ex-2 : Add (R3), R1
1. Fetch the instruction
2. Fetch the first operand (the contents of the memory location pointed to by
R3)
3. Perform the addition
4. Load the result into R1
Control Sequence for the Execution of the
Instruction - Add (R3), R1
Instruction execution proceeds as follows.

• Step 1: The instruction fetch operation is initiated by

loading the contents of the PC into the MAR and
sending a Read request to the memory. The Select signal
is set to Select4, which causes the multiplexer MUX to
select the constant 4. This value is added to the operand
at input B, which is the contents of the PC, and the
result is stored in register Z.
• Step 2: The updated value is moved from register Z
back into the PC, while waiting for the memory to
respond.
• Step 3:The word fetched from the memory is loaded
into the IR.
(Steps 1 through 3 constitute the instruction fetch phase,
which is the same for all instructions.)
• Step 4: The instruction decoding circuit interprets the
contents of the IR. This enables the control circuitry to
activate the control signals for steps 4 through 7, which
constitute the execution phase. The contents of register
R3 are transferred to the MAR in step 4, and a memory
read operation is initiated.
• Step 5: the contents of R1 are transferred to register Y,
to prepare for the addition operation.
• Step 6: When the Read operation is completed, the
memory operand is available in register MDR, and the
addition operation is performed. The contents of MDR
are gated to the bus, and thus also to the B input of the
ALU, and register Y is selected as the second input to
the ALU by choosing SelectY.
Step 7: The sum is stored in register Z, and then transferred
to R1. The End signal causes a new instruction fetch cycle to
begin by returning to step 1.
********************************************************

• This discussion accounts for all control signals except Yin

in step 2. There is no need to copy the updated contents of
PC into register Y when executing the Add instruction.
But, in Branch instructions the updated value of the PC is
needed to compute the Branch target address.
• To speed up the execution of Branch instructions, this
value is copied into register Y in step 2. Since step 2 is part
of the fetch phase, the same action will be performed for
all instructions. This does not cause any harm because
register Y is not used for any other purpose at that time.
 Tutorial – Problem 1.7
• Add [R1],[R2]