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Timer Def

The document defines various timer control registers and their fields, including TIMER_CTRL0, TIMER_CTRL1, TIMER_CMP0, TIMER_CMP1, TIMER_VAL0, and TIMER_VAL1. Each register has specific identifiers, default values, bit positions, widths, and ranges. The configuration includes interrupt enablement and comparison values for two timers.

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Ankur Gupta
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3 views2 pages

Timer Def

The document defines various timer control registers and their fields, including TIMER_CTRL0, TIMER_CTRL1, TIMER_CMP0, TIMER_CMP1, TIMER_VAL0, and TIMER_VAL1. Each register has specific identifiers, default values, bit positions, widths, and ranges. The configuration includes interrupt enablement and comparison values for two timers.

Uploaded by

Ankur Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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`define TIMER_CTRL0 8'h8 // Register address 0x8

`define TIMER_CTRL0_INTERRUPT 1 // Field identifier


`define TIMER_CTRL0_INTERRUPT_DEFAULT 0 // Default value is 0
`define TIMER_CTRL0_INTERRUPT_B 1 // Bottom bit position
`define TIMER_CTRL0_INTERRUPT_T 1 // Top bit position
`define TIMER_CTRL0_INTERRUPT_W 1 // Width is 1 bit
`define TIMER_CTRL0_INTERRUPT_R 1:1 // Bit range [1:1]

`define TIMER_CTRL0_ENABLE 2 // Field identifier


`define TIMER_CTRL0_ENABLE_DEFAULT 0 // Default value is 0
`define TIMER_CTRL0_ENABLE_B 2 // Bottom bit position
`define TIMER_CTRL0_ENABLE_T 2 // Top bit position
`define TIMER_CTRL0_ENABLE_W 1 // Width is 1 bit
`define TIMER_CTRL0_ENABLE_R 2:2 // Bit range [2:2]

`define TIMER_CMP0 8'hc // Register address 0xC


`define TIMER_CMP0_VALUE_DEFAULT 0 // Default value 0
`define TIMER_CMP0_VALUE_B 0 // Bottom bit position
`define TIMER_CMP0_VALUE_T 31 // Top bit position
`define TIMER_CMP0_VALUE_W 32 // Width is 32 bits
`define TIMER_CMP0_VALUE_R 31:0 // Bit range [31:0]

`define TIMER_VAL0 8'h10 // Register address 0x10


`define TIMER_VAL0_CURRENT_DEFAULT 0 // Default value 0
`define TIMER_VAL0_CURRENT_B 0 // Bottom bit position
`define TIMER_VAL0_CURRENT_T 31 // Top bit position
`define TIMER_VAL0_CURRENT_W 32 // Width is 32 bits
`define TIMER_VAL0_CURRENT_R 31:0 // Bit range [31:0]

`define TIMER_CTRL1 8'h14

`define TIMER_CTRL1_INTERRUPT 1
`define TIMER_CTRL1_INTERRUPT_DEFAULT 0
`define TIMER_CTRL1_INTERRUPT_B 1
`define TIMER_CTRL1_INTERRUPT_T 1
`define TIMER_CTRL1_INTERRUPT_W 1
`define TIMER_CTRL1_INTERRUPT_R 1:1

`define TIMER_CTRL1_ENABLE 2
`define TIMER_CTRL1_ENABLE_DEFAULT 0
`define TIMER_CTRL1_ENABLE_B 2
`define TIMER_CTRL1_ENABLE_T 2
`define TIMER_CTRL1_ENABLE_W 1
`define TIMER_CTRL1_ENABLE_R 2:2

`define TIMER_CMP1 8'h18

`define TIMER_CMP1_VALUE_DEFAULT 0
`define TIMER_CMP1_VALUE_B 0
`define TIMER_CMP1_VALUE_T 31
`define TIMER_CMP1_VALUE_W 32
`define TIMER_CMP1_VALUE_R 31:0
`define TIMER_VAL1 8'h1c

`define TIMER_VAL1_CURRENT_DEFAULT 0
`define TIMER_VAL1_CURRENT_B 0
`define TIMER_VAL1_CURRENT_T 31
`define TIMER_VAL1_CURRENT_W 32
`define TIMER_VAL1_CURRENT_R 31:0

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