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VLSI Physical Design - Week 1 Questions

The document outlines the first week of assignments for a VLSI Physical Design course, including various questions related to data path design, logic design flow, and physical design steps. It specifies a due date for assignment submissions and provides a link for certification exam registration. The content includes multiple-choice questions aimed at assessing understanding of VLSI concepts.

Uploaded by

I.Vivek Anand ECE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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36 views4 pages

VLSI Physical Design - Week 1 Questions

The document outlines the first week of assignments for a VLSI Physical Design course, including various questions related to data path design, logic design flow, and physical design steps. It specifies a due date for assignment submissions and provides a link for certification exam registration. The content includes multiple-choice questions aimed at assessing understanding of VLSI concepts.

Uploaded by

I.Vivek Anand ECE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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1/18/25, 11:47 AM VLSI Physical Design - - Unit 4 - Week 1

[email protected]

(https://swayam.gov.in)
(https://swayam.gov.in/nc_details/NPTEL)

NPTEL (https://swayam.gov.in/explorer?ncCode=NPTEL) » VLSI Physical Design (course)

Announcements (announcements) About the Course (preview) Q&A (forum) Progress (student/home) Mentor (student/mentor)

Mentee List (student/mentee) Review Assignment (assignment_review) Course Recommendations (/course_recommendations)


Click to register for
Certification exam

Week 01: Assignment 01


(https://examform.nptel.ac.in/2025_01/exam_form/dashboard)

If already registered, click Assignment not submitted Due date: 2025-02-05, 23:59 IST.

to check your payment 1) Which of the following represents a data path design? 1 point
status
a. Arithmetic circuits, registers and their interconnections.
b. The truth table description of a combinational function.
c. The sum-of-products representation of a function.
Course outline
d. All of these.

About NPTEL ()
2) Which of the following is true for logic design in a typical VLSI design flow? 1 point

a. Specifies the functionality of the chip

https://onlinecourses.nptel.ac.in/noc25_cs73/unit?unit=17&assessment=243 1/4
1/18/25, 11:47 AM VLSI Physical Design - - Unit 4 - Week 1

How does an NPTEL b. Generates the final layout


online course work? () c. Generate a netlist of gates, flip-flops or standard cells
d. Generates netlist of RTL components
Week 0 ()
3) Consider a gate array fabrication facility, where the designs prepared by three customers X, Y and Z are sent for fabrication. The cost of
Week 1 () fabricating a generic mask is shared by all customers. X orders 1,000 units, Y orders 2,000 units and Z orders 3,000 units of chips. Assume
that the cost of fabricating the generic masks corresponding to a design is Rs. 50 lakhs, and the cost of customization is Rs. 10 lakhs for every
Lecture 1: Introduction 500 chips. The total cost of fabrication of all the 5,000 chips will be Rs. _____________ lakhs.
(unit?unit=17&lesson=18)

Lecture 2: Design
1 point
Representation (unit?
unit=17&lesson=19) 4) Which of the following statements is/are true for structural representation? 1 point

Lecture 3: VLSI Design


a. Specifies the circuit in terms of interconnected modules and components.
Styles (Part 1) (unit?
unit=17&lesson=20) b. Specifies the function in terms of Boolean equations.
c. Specifies how a design should respond to a set of inputs.
Lecture 4: VLSI Design
Styles (Part 2) (unit? d. None of these.
unit=17&lesson=21)
5) To achieve maximum possible design performance which of the following design styles is most preferable? 1 point
Lecture 5: VLSI Physical
Design Automation (Part
a. Standard cell
1) (unit?
unit=17&lesson=22) b. Gate array
c. FPGA
Lecture 6: VLSI Physical
Design Automation (Part d. Full custom
2) (unit?
unit=17&lesson=23) 6) Which of the following order is true for physical design? 1 point

Week 1 Lecture Material


a. 1. Floorplanning – 2. Routing – 3. Static timing analysis
(unit?unit=17&lesson=24)
b. 1. Routing – 2. Partitioning – 3. Crosstalk analysis
Lecture 1: Note (unit?
c. 1. Placement– 2. Routing – 3. Static timing analysis
unit=17&lesson=25)
d. 1. Crosstalk analysis - 2. Static timing analysis 3. Physical verification

https://onlinecourses.nptel.ac.in/noc25_cs73/unit?unit=17&assessment=243 2/4
1/18/25, 11:47 AM VLSI Physical Design - - Unit 4 - Week 1

Lecture 2: Note (unit? 7) In which step of physical design are the shapes and pin locations of flexible blocks get defined? 1 point
unit=17&lesson=26)
a. Floorplanning
Lecture 3: Note (unit?
b. Placement
unit=17&lesson=27)
c. Routing
Lecture 4: Note (unit?
d. None of these.
unit=17&lesson=28)

Lecture 5: Note (unit? 8) Which of the following is/are not true with respect to Gate Array design style? 1 point
unit=17&lesson=29)
a. The cell size is variable
Lecture 6: Note (unit?
unit=17&lesson=30) b. The cell type is fixed
c. The interconnects are variable
Quiz: Week 01:
Assignment 01 d. The design time is quick
(assessment?
name=243) 9) Which of the following steps in digital IC design flow does not correspond to physical design? 1 point

Week 1 Feedback Form


a. Logic synthesis
(unit?unit=17&lesson=31)
b. Routing
c. Logic simulation
d. Placement

10) For the function F = A’.B.C + B’.D, which of the following represents the correct bit pattern to be loaded into a 4-input LUT to 1 point
realize the function?

a. 0000 0011 0101 0000


b. 0101 0011 0101 0000
c. 0101 0011 0101 0011
d. 0101 0011 1111 0000

You may submit any number of times before the due date. The final submission will be considered for grading.
Submit Answers

https://onlinecourses.nptel.ac.in/noc25_cs73/unit?unit=17&assessment=243 3/4
1/18/25, 11:47 AM VLSI Physical Design - - Unit 4 - Week 1

https://onlinecourses.nptel.ac.in/noc25_cs73/unit?unit=17&assessment=243 4/4

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