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Week 10

The document contains a series of questions related to fault detection and testing in digital circuits, including concepts such as stuck-at faults, Boolean differences, and LFSR-based test data compaction. It also addresses specific scenarios involving scan path designs and BIST (Built-In Self-Test) methodologies. Each question tests knowledge on circuit testing principles and techniques.

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I.Vivek Anand ECE
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5 views2 pages

Week 10

The document contains a series of questions related to fault detection and testing in digital circuits, including concepts such as stuck-at faults, Boolean differences, and LFSR-based test data compaction. It also addresses specific scenarios involving scan path designs and BIST (Built-In Self-Test) methodologies. Each question tests knowledge on circuit testing principles and techniques.

Uploaded by

I.Vivek Anand ECE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Week 10: Assignment 10:

QUESTION 1:

To detect a stuck-at-0 fault on line X of a circuit, the required test vector T must satisfy
the following:

a. The fault-free value at line X must be 0.

b. The fault-free value at line X must be 1.

c. The fault-free and faulty logic values at the primary output(s) must be same.

d. The fault-free and faulty logic values at the primary output(s) must be different.

QUESTION 2:

Which of the following represents the Boolean difference of the function F = A’B + AC’ +
B with respect to variable C?

a. A’B

b. AB’

c. A’B+A

d. B

QUESTION 3:

Which of the following statements are true for detecting a stuck-at fault X/1 in a circuit?

a. During the forward drive phase of path sensitization, we set primary input values so
that the logic value at X becomes 0.

b. During the forward drive phase of path sensitization, we sensitize a path so that any
change in X is propagated to one of the primary outputs.

c. We avoid any fanout connection at line X by replicating gates.

d. None of these.

QUESTION 4:

What do you mean by aliasing in LFSR-based test data compaction?

a. Some error has occurred for which the faulty circuit is identical to the fault-free

circuit.

b. Two different faults occur that are equivalent faults.

c. During compaction, the fault-free and faulty signatures become identical.

d. None of these.
QUESTION 5:

Consider a scan path design where there are 15 scan flip-flops, 5 primary inputs, 3
primary outputs, and we have to apply 100 combinational test vectors. The total number
of clock cycles required for applying the test vectors and observing the outputs will be
_____________. Ignore the additional clock cycles required to test the scan chain.

QUESTION 6:

Which of the following test patterns must be applied to the input of a scan chain to test
faults in the scan flip-flops?

a. 1000 1000 1000 1000 ...

b. 1100 1100 1100 1100 ...

c. 1111 0000 1111 0000 ...

d. 0011 0011 0011 0011 ...

QUESTION 7:

For a 10-bit LFSR generating an m-sequence, the number of distinct patterns that can be

generated before they are repeated is ____________.

QUESTION 8:

For a 6-bit LFSR compacting a 3000-bit serial bit stream, the probability of aliasing is
given by ________________.

QUESTION 9:

Which of the following statements is/are true for full-scan based testing?

a. Test vectors cannot be applied at the maximum rated clock frequency.

b. Test vectors can be applied at the maximum rated clock frequency.

c. A sequential circuit ATPG tool is required for test generation.

d. A combinational circuit ATPG tool is required for test generation.

QUESTION 10:

Which of the following is/are true for BIST?

a. The number of required test patterns is less.

b. There is no hardware overhead to allow for self-testing.

c. Test application can be carried out at the maximum clock speed of the chip.

d. Test patterns are randomly generated.

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