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Week 8

The document presents a series of questions related to electrical engineering concepts, including resistance changes in wires, capacitance in capacitors, crosstalk effects, and VLSI layout generation. It discusses various scenarios and options regarding wire capacitance, transistor requirements for NAND gates, and design rules advantages. Additionally, it addresses the role of constraint graphs in layout compaction.

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I.Vivek Anand ECE
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2 views2 pages

Week 8

The document presents a series of questions related to electrical engineering concepts, including resistance changes in wires, capacitance in capacitors, crosstalk effects, and VLSI layout generation. It discusses various scenarios and options regarding wire capacitance, transistor requirements for NAND gates, and design rules advantages. Additionally, it addresses the role of constraint graphs in layout compaction.

Uploaded by

I.Vivek Anand ECE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Week 8

Consider an interconnection wire of length L = 20 units and width W = 6 units. If L changes to


30 units and W changes to 2 units, the resistance of the wire will increase by

a. 1.5 times

b. 3.0 times

c. 4.5 times

d. None of these.

Consider a parallel place capacitor with length, width and thickness as 10 units, 10 units and
2 units respectively. If the length and width changes to 6 units and the thickness changes to
3.6 units, the value of the capacitance will increase by

a. 2 times

b. 3 times

c. 4 times

d. None of these.

Miller effect concerns the crosstalk between two lines X and Y. Which of the following will

result in maximum crosstalk effect?

a. Both X and Y switch in the same direction.

b. X and Y switch in opposite directions.

c. X does not change, but Y switches.

d. Both X and Y do not change.

Which of the following wire capacitance values is the largest?

a. Polysilicon to substrate.

b. N+ diffusion to substrate.

c. Metal1 to substrate.

d. Metal2 to substrate.

How many transistors are required to construct a 4-input NAND gate in CMOS?

a. 4

b. 5

c. 6
d. 8

Which of the following layers is most suitable for routing power supply connections?

a. Polysilicon

b. Metal

c. Diffusion

d. None of these.

What is/are the advantages of using design rules in VLSI layout generation?

a. Reduces the chance of fabrication errors.

b. All feature geometries are in terms of the basic feature size.

c. Maximum speed of operation can be achieved.

d. All of these.

Crosstalk effect on a line carrying a signal can be controlled by:

a. Making the line wider.

b. Shielding it between parallel VDD and GND lines.

c. Making it run parallel to the aggressor line(s).

d. None of these.

In 1½-dimensional compaction, an X-Y adjacency graph is used, where:

a. Two blocks have a vertical edge if they share a horizontal boundary.

b. Two blocks have a vertical edge if they share a vertical boundary.

c. Two blocks have a horizontal edge if they share a horizontal boundary.

d. None of these.

What is/are the role of constraint graph in layout compaction?

a. It can specify connectivity constraints.

b. It can specify delay constrains.

c. It can specify separation constraints.

d. All of these.

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