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Week 2

The document contains a series of questions related to circuit design, including topics such as the Kernighan-Lin algorithm, performance-driven partitioning, floorplanning, wire length estimation, and combinational circuit modules. It presents multiple-choice questions that test knowledge on these subjects, with specific scenarios and parameters provided for calculations. The questions cover theoretical concepts and practical applications in electronic circuit design and layout.

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I.Vivek Anand ECE
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2 views2 pages

Week 2

The document contains a series of questions related to circuit design, including topics such as the Kernighan-Lin algorithm, performance-driven partitioning, floorplanning, wire length estimation, and combinational circuit modules. It presents multiple-choice questions that test knowledge on these subjects, with specific scenarios and parameters provided for calculations. The questions cover theoretical concepts and practical applications in electronic circuit design and layout.

Uploaded by

I.Vivek Anand ECE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Suppose for Kernighan-Lin algorithm unequal sized blocks can be used during partitioning.

Given a circuit
with 64 nodes where one block contains 26 nodes and another contains 38 nodes, what will be the
maximum number of exchanges?
a. 26
b. 38
c. 64
d. 32
1 point
Which of the following statement(s) is/are true for performance driven partitioning?
a. On chip delay is of the order of milliseconds
b. On chip delay is of the order of nanoseconds
c. On board delay is of the order of milliseconds
d. On board delay is of the order of nanoseconds
1 point
Which of the following statement(s) is/are true for floorplanning and placement?
a. For placement all blocks have well-defined geometric shapes.
b. For placement the block size is flexible and have fixed pin-locations.
c. For floorplanning the blocks can be flexible and the pin locations can be changed.
d. For floorplanning the blocks can be flexible and the pin locations cannot be changed.
1 point
Consider two rectangular blocks X and Y with their centers located at the co-ordinates (10,15) and (40,20)
respectively during floorplanning. There are 20 wires that connect the two blocks. What will be the wire
length estimate between X and Y?
a. 700 units
b. 600 units
c. 550 units
d. 580 units
1 point
Which of the following is/are true?
a. For a planar triangulated partition graph, it is always possible to find a rectangular floorplan.
b. For a planar triangulated partition graph, it may not be always possible to find a rectangular floorplan.
c. If the partition graph does not contain any complex triangle, it is not possible to find a rectangular
floorplan.
d. If the partition graph contains a complex triangle, it is not possible to find a rectangular floorplan.
Four blocks B1, B2, B3 and B4 are placed in a floorplan with center co-ordinates as (15,25), (25,55),
(45,65) and (55,75) respectively. The numbers of wires connecting B1 and B2 is 10, B1 and B3 is 8, B2
and B4 is 6, and B1 and B4 is 2. The estimated wire length will be _____________ units.
1 point
1 point
For which of the following combinational circuit modules, the set of input lines form a set of functionally
equivalent pins?
a. 4-input NAND gate
b. 4-input EXOR gate
c. 2-to-1 multiplexer
d. A circuit realizing the function F = A.B + B.C + A.C
Consider a 3-terminal net with terminal co-ordinates (30,10), (50,30), and (60,40) respectively. The
estimated length of the net using the complete graph topology will be __________ units.
1 point
Consider a 4-terminal net with terminal co-ordinates (10,5), (20,15), (30,40) and (70,20) respectively. The
estimated length of the net using the semi-perimeter topology will be __________ units.
1 point
1 point
With respect to modeling of interconnects during placement, which of the following topologies most closely
resembles the actual routing paths?
a. Rectangular Steiner tree
b. Minimum spanning tree
c. Complete graph
d. Semi-perimeter

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