MIC ROPROCeSsoR

S20330sgo83iM
) A micoopvo ce.SSOY. s a mulipurpose, progamnable
clock diven, Negister based ielechonic evice thg4
Yeads binaby instucign om a otage device
caled memoy ocessor is Digital Device
MikvoPr
Menog

MICo
Pxocessox ATAC
|o Device
980

ehve
") Tnput nig blay
biag dato oo
ProcessK Data a ccording to instucHon.
Result as aa output

-> The Pysica J.d Camponents oP tnis System

aTe

-) Set of 1nshu cion OTittem fot the oR mlcroprocesso

bask 1s
to Pers form a tasK is called a prog am
> group of Program called
283 AdaA
Soft o are.

the micao poocessors0s the Combolling element

91Bo a computor 8y stem& S Som etimEg
E1ot geferTedto as he CPU Ccentad Processiny vit
 |5touctue
ssox 8 Reglstex Demo
88B MicvoProce " e use too bit 2 ines
MicooPTOcessor
INPUT anen oe oddsessed 4 Register
9cb o olo
output tnemo
CPVMemov 4 d ebpgr

ntoris BUS Register enod

CONTR0 pato
Sto7e
ADDRESS Address Reglster
BUS AddoesS Bus\
DATA
) Tt 1s used to
caory addesS
DyS fo ComDe con SO address bus
USe
) Io a Sytem deten)neS the mumber o1 phgstca&
BetOBN Compd ets locatODS.
> BUS ) Co 0meciom Memo"g um)dire ciomal.
Ribbo n ca bie]
o Devlce.Flat > t s
for digitas. Data BUS
h a
Data.
Signas, to
rapidlg to caTsy Data
} t is used cioa.
) BuS Js used to
CaTIy moivosg.Data & )tt i Bìdioe
adoess
BuS is BudieeoG)0es tbat Basic ProceSSORS
psgorCarrieS Data.
(O3085
BTotel pocesat
8086
|CODCept of ADDRESS & DA TA
2239ga 80186
286
MemoayoL4 Register)
486
4 ||9teye Otuqomo oRegis+es 4

2 -0 654 ePFFFF|F Regist 2 InhodC 935)

1-00
Address of Regsior Register1
 Miczo proCcSSoT
|8086
ADDREs BUS 20 bit
used to address,
Memozy:
cell hat 8tores Umidire cioma,
is basìc
Aop | Data
bit of ") 7t 1s BldirecHoal
Store ") Tt is used +o
Fr Aip Hop (

Sequ ence Features of 8086

Aip Hop i
} Conect pìc¡oPTocesso.o the term IG-bit
3egiste ) the 8036 is a. ls bìt
&esb be come
unit,itemal Tegisters
o means dhat it's azithmatc Sogic
FF3|F2 FF)FEOs instzúcHons ate designed to Qak coith
Joole JFF FF FESFF4 &most of it's
cam Bead
data bus,so it.
Jomotoaribioy (2) The 8086 bas a l6
data om o oite data
bit
oo 2 ePooT
to memorg
port either

16 bit o 8bit at a t me.

bUS, so it can
bas a. 20 bìt address
8) the 8086 memor
,48,576 Cimb)
accesS 220
3 dinecty
Reg d the 8086Ca genesate ls bit Tlo addTess, hence
it ca acce6S 216 65 636 I|o Ports.
Merong 5 The 8086 provides
foutteen l6 bi+ egisters
oith Reglster. have ADDRESs & mulipleedaddress data bus Qhich
) memo The 8086 has
Stoe Deta in ohe Regste. 26 eeded, but does
Tduces the num bor of PiDs
data Cdracoback)
Slo docon toe tagos fer of
Register|
The 808G Require one phase clock oith 89
dutg dele to pooVide aphmi te jnternal dime.
22 Reqlsier 2 o) 2T|9 5 MHafor &03
ToN Tofr
Register o0
Range o¥ Clock Rates
 tidoS
8086 Syppoots PipeJining.
oFetchi he 8086 Axchiteciute 7 oos king
I+ js Hhe process cuTTnt instruCHon '9
the
obile erBCuHng of the
ImproVes Pe formance
Memor
Ioterface
9) 8086 bas 2 operaing
ome 8O8G CPU is
Mode :>ohen only -BVS
O Minimum Sstem.t;no0h
mìcro com puter
to be used im a CPU, dssues the
he
TG- In thìs mode device tbic
memo
Matimum Mode In mulipr0 Cessor(moTe thon

n maimum mode.
oPerrates
ots, In this mode Conhol signaS are gonetaBe
Bus COmolle
oit the help of eternoa
D.S
Bamks
D) So8.6 provide
) The enie memog each, in
2 baks 0f 5)2 k8 0de to tansfer
1o Ev,
oo ne bamks ae called

AH AL
3086 supports memoy seg mentation. A rithmahc

> segmetaion means. dividing

logicad components6 tt c0oules
> Hese memoy is divided imta 4 seq mentS
code seg ment Data segnent
Stack Segmen} im ) Bhra segment
2thampDI Elags
12
3086 bas 256 ioteiup+s.
 go86cam be
avchitectuoe of
Complete -7 Instacion poipier CP Reqster)
the
) divided Jnto +oo paat6. The s0 6tr ucti on poiter segister holdg ohe 6-bit
(BIU)
face um)t addoee9 oP the net code bte ohin tne ode
Totex
a) BUS unib. segnent
EU- Etecuion
b)
CBI V) ")Gen eratio oP 20-bit addreas
ioteface vo)t|
Bus
Paovide the
totexface of
g086 to oheY
Devhces phy sica addvees
oraton
Such QS the 20-b4
> Tt
Vatious machlme Cycles i Aith matic cicuit Tt generateS offset adiesss
> 3t pexfoa
ms
Read, 0 Ooite elc
to toansfer data
(eeonbA Phicq addaess using seg ment g
Mem
} Tlo DevÍces.
addhses X toh t offset addess
bit
Physica address Physica qddress - segment
t generate dhe 20
a memoTy. QueuepD
S+u Hom Psom
b) fetcbes
cata toom the memory 3 lo >Instucion QueueGbyte pre-fetch
) +3 ansfers Cuion,
; To speed upPsogoam eKE
4) suppoats pipedining using dhe 6-btes Jnsuc -btes"a9
queue. the ngt te Six imstacton
holds SBavèng Ab.of e;) l6T0 fetches tne queue.
Eegent Reqistess L Code Segments & stoxgs it into-
>funcHon of reglster holds the
som the
0n the principle
of f s t
") The CS [code
segment]
addoees of the Codo The queue operates 9b29+09o 2gbona
the stazng D60out: FIFO)
4PPer l6 b\+ of fetchig imstruCos fom
ohicn
seqment Rom code the e s carent ") Executom umit eE)oemoleso9
InsoucHon B. byte. Odhe Queue ecute nem:
dhe
e)ster is used for cohen least bytes
) the 6.s [stack segmont qddress for l6 bit data bus
CI6-bit) of the Starng
the yppor operdks ont
insucÀon oil)
0s

pr09Tam Stack Al stack velated

the

Ds [peta segment egster erobossb

) the S ra soq mont
l6-bi+ OP 6tarHng
sobouri8m)
are used to hold the ypper
menog Segmets
addsess of tne t00 data.
CUhjch ave used for
 -> comtod ciCuity 4 i0817acho n decoder:
the imtexTnl
ahile PeReCuhng dizectS all
instaucion Comhol cicuit o the EU
mert o: POOCe8s0r.
the dosrucdiom Called e pi opesatHos o dhe dhe snotrucon
")fetchlg
cuTent
s
O TheducHGni the U t zanslates
of actons
the JocoOses fetched fsom the mernory unto a 6er)es
the enecuHon Unit
Usefu
POe detetS a boach oerdhon, ") Aidh roaic loglc unit c0bVDrG 8-bì+pd hL
as soon as SO86 No he Peofor Ms addiHon,Sabtsacton
Hence enhre queue.
cads the
dhe Ne locaion Cbramch dddhes) Anth mati c ogi bu
un)+
jt cleaTs /dls Rom mathe maca
oPeaionsLSuch as
comversion 4 1ogl cal
bgtss
are fetched plaueie &plpeining srmHpli cation
division, data
Not, oR 0Y AND t
aso

22ueso1 X 28asbp foemgea oPeraHoos ike logi cal decsement 6hif. operaHon
289skbp poled9 PesfornSeot Iip ariDco o Hcsocs ro
ExBCuHom Unit(EU)o
Rreieiokraot
the locaion at opezond Regster
BohlchfosMS , t e BTÚ abot DataSto be 9rtiscal6bit 7egls+er e9 sedby the conhho&
Obich the n e tStTucHo o
JOgister to hol d the operad
tne
tempoT(Ti ly
progTamor.
pd Tismot, available to
from the queue Sn B,
7 Tt fetches imsbucHoms (Se
’
decodes & eecutes them o foreqo 909up 9dT bollpo o2lp 2i od bbo
Dataternal RegisteS :
aith maic, Jogic
t8amser OperatonS. puTpOSe egstes
to the
gnads
modules, Susup 9ds ( lgbled AH,A,BH,Bl, CH,CL, pH& DL
acess dne teNHal
folocoingfuncH ond
So050
oised ndi vËdualy
) these registrs can be
)ExRCion um) b CoDS6t op the
tor teopotazy Storage Of 8bit data.
inshucion decoders ) tse ALigeqìster Calleaccum latrr.
> Conto
)Flag eglstex. "> ALU - Arithmaic logic onir ") paiaS f dhe6e Aeneal puPose Tegsters
be used
">Genesa prPase Yeglster Cam together to sto e l6 -bìt
AatoSqch aS An, B*} Cx, DX
 In 8086
Banking MermosSegnertahonp
Memod to LCess ) segmenta tion mean[ dividig the memory into
memog dogicaly different parts, cqled segsrt6.
> SORG uses
in oe cycle.
l6 bit data 8086 has 20-bìt addtes buS t can access 2 1 MB
is divided to +ag Banks
20 bit Phy sicad address,
ProVldes 8 brtg. ohoisA byte compat ble numbor.
Cach bamk 20 bit addzsss C22 by te) is mot a
trat l0compat ble mymtor0e cre ate
> To aVol de ooking \th oltth 16 bit adress.
Contajas a. Vittuay moded oP Denoo2utDta -a
chlps, Hence each chipA Data, Ezha.
6 Di~ÁeTeut divide Jnto 4 3egmerts: code, Stack,
A0FsorOgo ocaionb10(19r096 t09196To2qddrs
all evon calledcthe
0ne bank Contajs the other bamk calJed od Code
ohle CS
(e Augrn ban k code sement
all odd addgss.
conkaining Totapeh brosogol OFPSet
ADD
)6 bit o PeraHo the evn ban k provide
dne odd tank prov)d8S the higner S}ack scgment SS ’ Stack segmont
stack po)nte’s
byte-DT poror , qlso
glealbd thete logor bqnk' Base poiT40Y’ p
") Hen ce the even bank s
nighor bamk»
7 odd bank às also called dhe Data
Segnent pS Data segment

2r0fep0r 3809 5|2kB Eha segmant

lnobivibo Addvess: 0000) H
00003 H o3
A.opl
ADDress: 00000
00002 H
H

"} Poogaammo cqn QcceS each l0caHon cojth Vttugl qdd.

Selected ohen HE-0 3eleted ohon Ao 0
erotalgor > Viatyal add is a Combinaton of Seq add t otse+ add.
Jia-ol BHE m9rtbopot ) Segmentahoa por mits the progamns to acess
8 bit fom 4 MA using only l6 bit+ addzess,o
o HighaBank
Rl 8 bit foom loer Bamk
’ Tdle
 9M
biH)
Flag Regiscss ( oVerfloc) lag (oF) 2o Mutnznz
ballps Flags? Auoila
Signed operaHon
Conhod
ca'd is too large to fit sn tne umber Of bits atailghlp
oFDEFTFSE 2FAE PE

16 bjt
|cON ROL Fiags
8- CoBo Hagsyh
) 6-status Flags >t S used to Set +ace rDode. imstruCHOn So that
ate affected b the
) up iS dnterupted after every
) staBu one instrucion E4ecute
oT sAPrOgam can be debugg ed Done by
aftex eVEry avth meic
Aive status of de
cuorent Result. Toteupt Eoable Aag (E)
Cdisable) oryn maske
to Çonbal the opeaion: t iS used to eee maske
> the conbol Hags used Cenable) be NTA Iteupt
3THE

dne proarammer
chenged DecHon
Quto- decTMEnHng
s atus fiags: F ohls Hag is Set, sT DI qrse in
mode in s i g operatons.
Ttis Set, OhemeVer there S a Cat
OCarTy flag
ca the SOSult
or bortoO out. of the MSB of TM

CPEJ
the Resu H has eVon party

95(e 7 t iS Set Ca enerated out of the odor

Nibble.
")t is Sed oly 8 bit oPeraion ke DAADAS

LopisiV
CS

") for 6igned op eratign , sch a mum bor s toecte

as -Ve.
 MINIMUM MoDERB
’ the o)nimnum mode is used
Srnall
aidelibvb
minimum mocde Conigio. ith a. S \e pIoceSsor stem
go86 in aeyy e l e

) TN mioimum mode MN /MA =1

) clock is povided by 8234. clock. enerer.
addxeSS rorm tne dddress bus iS Jatched inio 2222
ISMH2
S M H Z .

8bit Jatch
(8) > 3 latches ase needed i) a
System, as adaress
Clk ALE STB Oho bus is 20-bit.
RES 2) baay
8284 Reset ) ALE iS the address Jatch enable. it ls g10em by
noReadgß 9noRRvdsb2d 8282
Larch
Cu) Bo86 to 8232CLatch)
") The data s doven though 8286 8 bit
43anstecei v6r
a9
>8036 iS bidiaecioTa buper &also Knon
data ampli erS
TNTR separate the Vald data Pro m
") They ae used to
8286 muliplened ddd |data bus.
meeded becouse the data
HoLD 7 t 0 taa0s XEcOers a3e
DEN
LbA sobus ss l6 bit long:
(2) DEN Signa.
" 2 8236 emabled though the Comhrolled b the
the data bus
Disection of data om
Vcc MN/M wk RD M/1 -0 then 2eceive
DT/R Slgnad. DT/R-| - Tzansmit
Vcc
for all operatons
ls
") ContrO . Signoa RDOR

Aig - Ao
74138 qenerated b decodimg
-
-Ao\ ALE
o De codor MEMA RD Read
Ds Do memog
MBMU memoy ite
F|o Redd
Ap1s - ADo
gTite
 pe cod ed b 88Decode,
") M /RD,WR
,
Maximum Mode
7074138.
Request CDMA) maimum mode cCngao0
bobivoss el ools
HLDA Signals. (P2o2\f802 ) 2302 ot aDeea3o
esponse to
8O86, pfld
") TNTA
trd-oe
than. mazimum modo
sìmplrmul+iprocessi
SQppot &l 21A RES 22 atb 3282 BME
) The (oofpJDN9s& 8284
21
C3) Atg-Ae
bt does mob oom MDReset 22s2 3 bit
Ready ST6 Latch. 20

mode Read ycle

Timing Diag of mìnimum Sjs Ready
Eitb

Reset
Te 9603

TEST

AlG -A1g BHE

Sa- S6 S AIc- A19, AHE S3 -S7 baidomo 8286 DgDo
foy C2)
Data
Ao - Ais Data B

Se,51,s0 (2830) ToriE

ALE DEN
gidoeib 2i 9vj9pT ALE

1:MR MwTC
AMwTc
Dtbb (KercbrT 282ORc
BUS
ConlkALO

RD

DEN
 Max) mum mode,ohen MN)MA 0
can
ConDect mOTe BuS sequest is doe usiDg R IGT Sires Sntefaced
Im ma)msm
mode c0e coith R086
(8o87 /gogg) yTNTA is given b 3238 BUS Con noller, `n Responsc
ProcesSos to 8086
g284 c)ock generatoy, to a int. o INTR Sine of 8086.p
> clock provided by
P a t of the maimsm modo ) ma mode ci8cui4s S moe comple than min mode
signiicant
") the most bus con rollex but supports multi procesSing hen e alves betieyost
CTcuìts he 238
pesforman ce.
by 8288 1nmaimum
) ALL Bus combolled
ohis mod e
") 8282 8 bit latch used
busis 2o-bit
qe meeded as adesS
") tne dat a bus is diven thoougn 8286 8 bit
toansoe ceiue, t0o e asTeel y@y meeded
da+a bss às l6 bìt. T23T

o DEN DT/R are emab|ed Signas giVen by9o Hoo)as ofo

8288 Bus Comsollr
DEN AcH om. Sorce
DT|R
(ofg288)
Toamecejv is disable
Recei0e data
Toamsm)t data

ComhsoJd sigmals fos all OPeraHos aTe

genevated bg decoding S2,3 &So sigmado

"> S2, S,,s de coded 8288
Comollr.
bs
 8086 IoBerypts o
the psocessor is enecuhng a progarn C n a code
Specia
Comdiiom that D202teyca
qrises segmentI Sequen Hallg b inorermenHng tre P R
afte an i0Stsucto a intes 3upt
pt s a
) IteoNu yprocessoY l Suspend the ecuion 20 to J R
Subxoutne called Hmsb dne TSR PGgam Come back
etipotio 9bon 0 t i0stracHOM of main pgTam.
Roudme CsR 9d has its GSR
QteTyptS of O86 9d 7evey )DterTUpt rto TP dhen Prog7am
3 SouTce ot puts H's FSR addrse 3S
O Hatdeoade terTupts : (ExBesoal) B8ach to the
Signals ta keS a
-) These Qotess pts
OCCU ag i0 a Sequetia
pìns Of ea s it has to
etesna hardose RET instUctioo
accept stucHOn. of
>8086 has t0o Pims to oetuoU to the met
NMI & FNTR
qI'7TSR addeaS fox
3oftooaoe ToterzuptS: 45dhe ioteTUpt up Compete.
dhe pooceSS0r Aets address
ae caused by et i ostruction
0MShucHo INT n CuTTOmt l0&touctiom, eeded b p 3hil.
Softoare itesoUpt Jhere Poese)t m FP. Onìch
foom oto 25S (oOH to Pf back Psom FSA.
ca be amy Ualue comin io
et m
3aue thìs P address
ProcsSor
Comdiion Prodced by. special comdihons
Some Aast
cestai instructon n the CRetarn.
adl) stack
Occur Ohle eLecuting P
TPTSRadd
Push
POgram CoUse the NTO O
f eoor is division automaHally
\teTupt. tatn
LoteTupt StouctuTe

") A \oteoupt
that halts dhe p
coditon
tempoas
event
make3 Stack is used Cstack)
to Store
Return qdd-?

it recute FSR TnterTupt Serv)ce Routne PushRal

Push Rg2 P u s hR a 3

Prgammgy TPTSR Address TSR ce

pat
Jnt n pop
n=0-2SS PoP

TPERetum Addregs IReT

 pushed tn
otder fa
Ra | Rag
Ra 07dr Raa IVT -(Toteroupt Vectog +able)
Popped ln the a tabIe is
Stored i0 StructuYe ) 256 TSR address a8e stored in
fo maHon mamney o e called TUT toble. ohlch St0zed ln the memu
So the FO
Opexat es l o I nemo tolce

Pushes
OTo get JSR address 0 to FSR n nemo.
Duoing FSR
dhe PoPs.
should ) 0T l0esdirecHom to the up to go to tre5R
Stored
quad to No. 0f .) The adress of UT 1S Hxedt is alays
get Same addre qt dhe addsss 0000oH CPA)
then
for
> The Si2e oP TUT 0s thee
Pusb foPDo
me TRET
heo oH at the TP CS- dddess
Store io Stack. "} One imteypt has
Lond d4u8tti D of 20rbbre TP Cl6 bin) + CS Ck bit) = 2, bytes.
Laddess
-address ls
s aloay S im dhe foom o
aloays 2 bjtes
} TSR 256 iMt Erqpt
Offset address.
addoesSd SR of INT 4 iS

Pe of Branches
6000|1|2fTPH
00002H
same code scgmen
boanch 00003 4| CS H
boqaCh anothe code Scamor o0004+ INT
Intorseqmem INTA -single.
steP 00

Tora only zP oill change NT2- NMI So

Fntor P4 Os both ill change NT3-Breqkpoint S6789

-age needed When RET get. On oGro.

9
Resey ie
TNT-31

") So Oe ol| Push NT 32) yse

then push P obile SP-2 CsL dene.MAt
urning Ast po pp CSH 003FP 7NTSS
dhen pop CS.
 poipheralS10e fa cio
MeMorg &
IoBerfaclg Fg o00hsht2
O [Memog
Ssteh F8000H Staring Add.
Add. of EPROM.
8086 - based Ma mode
m loor SPeciHcnN
0 Desgn 6MH2 For e A a i a Ratired +0 calcalate Add. Jines.
coo king at chjps.
32kB EPROM using l6KB chips.onbp 16 KB = 24x2l0
l4
32 KB ChB ps. bbe srb inslde the chips
( 128 KB RAM
USIlng
Using 14 Address ine put

Soludon 99991
RAM:
0001
() EPROM Requized = 128kB
AVailab \e = 2 KB
Requized = 32kB Reauised 128 -4
Avaj la ble = |6KB NG.of chipS 32

4 chips
NO. Of chìps Requited (2) 2 ehips RAM.
for calculaHon o
Staoing ADDRESS of EPROM chìp Size Required
Address ime
32kB - Requised Si28 - 32x1K -
32k6 = 25 xgl0
the chips
2l5 -Address line, put mside
15
15- oDe's
RA M- Set 00000H e
F I5 0ne's give one u staring Add.-
oFFFE H
eVen chip End. Add.
PAM Addo00) Ho
End addeSS of Memory PPFPFH staing
RAM O0006H Godd chip End Add. 40000H

End> RoM RAM2Lollt -|g001 H

 ROM SeT stashng

EVen chip
End. Add.
StaxHng Add.
|Des)g:
End. Add
odd chìP
anlt b RotM RAM RAM RoM
MAA
3
H)
F8000
|FFFEnRAM
MermoA
Ao-A13
Da-b7
P7 AA4
Do- Do-b Ao-Ai
10000
H
Address A-, Ao
MeM A-S
Aj-A Ma

A
Ay oldplioVA
As
Ay
RAM RAM ,RoM
4
Do-D7 Ao-AB
So-i4 Do-D Ao-Ai4 -Da
Do
JA-sME MO M0Me

eA4
1||1 A

A19 beriupo

741383:3Decode
G2h
(BAnk
RAM
PAM
(H A18
L
Po
 mininym mode Slm
based :. starting Peaui red
8oR6
DeSigo qn the. foloc)ng 128 IK
QO
ab GMHe hauimg 32 KB chips,
I28 KB EPROM as)ng G4 KB Chips.
128 KB
RAM simg 1111311111J1113

Solukop :
SRAM: 128
KB No of chips = 64
Requlted - l28
KB
Available = G4 - 2 chips

RAM Chìp
singte
c64 KB

-2l6
l6 Adess imes CA, - Als)

EPROM6
Required: 28ke
Available:32kB
No. of chips -|28

Single ePROm cbip.

=32 kB = 321K

- 16 Advess Jines
CAj- As).