UNIT 1 ARCHITECTURE OF 8086 MICROPROCESSER

UNIT-1
ARCHITECTURE OF 8086 MICROPROCESSER
What is microprocessor?
Microprocessor is a general-purpose programmable LSI or VLSI device capable
of performing all the arithmetic and logical operations by a series of micro-
operations. It is a powerful as many as thousands of fundamental digital devices.
FEATURES OF 8086 MP
i. Multiplexed 16-bit data bus.
ii. 20-bit address bus can able to access up to 1MB memory.
iii. It uses a segmented addressing which facilitates the programmer to
address 4x64KB of memory at a time.
iv. It has pipeline processing facility which increases the speed of operation.
v. The 8086 is a 16-bit microprocessor.
vi. It has 14(16 bit) registers and ALU.
vii. It has 256 software vectored interrupts.
viii. It can be used in either single processor environment or multiprocessor
environment.
ix. Bit,byte,word processing ability.
x. It has advanced several instruction set.
xi. It supports the multiprogramming.

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INTERNAL ARCHITECTURE OF 8086

• Figure shows the internal architecture of MP.

• 8086 CPU is divided into two main block.
1. Bus Interface Unit (BIU).
2. Execution Unit (EU).
Bus Interface Unit:
It controls the all tranfers of data and address on a bus for the execution unit.
The BIU consist of following functional parts.
1. Instruction Stream Byte Queue.
2. Segment Registers.
3. Instruction Pointer.
Instruction Stream Byte Queue:
To speed up the program execution, the BIU fetches six instruction from
memory and held in a Queue and this Queue works on FIFO principle, BIU
fetches the instruction. While EU is decoding/executing an instruction when EU
is ready for its next instruction, it simply reads the instruction from Queue in the
BIU.
Segment Registers:
Segment registers are useful to increase the memory addressing capacity.

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The memory addressing capacity is increased by combining the addresses from

two 16-bit registers to form a 20-bit physical address.
Segment registers provides both base address and offset address. There are four
16-bit segment registers.
a. Code Segment Register (CS): It holds the upper 16 bits of the starting
address.
b. Stack Segment Register (SS): It holds the 16 bits of the starting address of
the stack.
c. Extra Segment Register (ES): It holds the 16 bits of the starting address of
two memory segment used for data.
d. Data Segment Register (DS): It is used to hold 16-bit starting address of
two memory segment used for data.
Instruction Pointer (IP):
IP holds address of the next instruction to be executed.
The address value present in IP is known as effective address or offset address
used to produce 20-bit physical address.
Execution Unit (EU)
EU performs the following functions
a. Tells the BIU where to fetch the Instruction or data from memory
b. Decodes Instructions
c. Executes Instruction ->It has the following parts
i. Control circuitry, Instruction decoder & ALU.
ii. Flag Registers.
iii. General purpose Registers.
iv. Stack pointer register and other pointer index register.
Control Circuitry, Instruction decoder & ALU
Control Circuitry directs the internal operations decoder the fetches the
instruction from memory and translate the instructions. ALU performs the add,
sub, mul ,div & logical operations.
Flag Register
It is used to indicate the condition of result after execution of an instruction.

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General Purpose Register

8086 has eight GPR & they are AH, AL, BH, BL, CH,CL,DH, &DL this register are
used for storing 8-bit data.
Stack Pointer Register Other & Pointer & Index Register
EU has the following 16-bit registers
1. Stack pointer (SP) register.
2. Base pointer (BP).
3. Source index (SI) register.
4. Destination index (DI) register.
Flag Register or Status Flag Register
- - - - OF DF IF TF SF ZF - AF - PF - CF

A Flag is a flipflop which indicates some condition of a result after execution of

a instruction.
It is a 16-bit register & has 9 active flags. Flags are divided into two types.
1. Conditional flag.
2. Control flag.
Conditional flag: condition flags are set or reset by EU on the basis of a result of
some arithmetic or logical operation. There are are six conditional flags.
a. Sign flag (SF): it indicates whether the previous result was negative or non-
negative. It will have 1 if MSB of a result is 1(negative number). It will have
0 if MSB of a result is 0(non-negative number).
b. Zero flag (ZF): it is set to 1 if the result is zero & 0 is the result is non-zero.
c. Parity flag (PF): it is set to 1 if the lower-order 8-bits of the results contain
an even number of 1’s, otherwise it will be 0.
d. Carry flag (CF): it is set to 1 if there is a carryout or borrow from MSB after
execution of a arithmetic instruction otherwise it is cleared.
e. Auxiliary carry flag (AF): it is set to 1 if there is a carryout from 3rd bit during
addition or subtraction or BCD arithmetic operation.
f. Overflow flag (OF): this flag is set to 1, if signed arithmetic result is too
large or the result of the signed arithmetic operation is overflow to MSB
bit. else it will be cleared.

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Control flags:
a. Direction flag (DF): if its sets, the string operation will be carried out in
reverse direction i.e. from the last string byte towards the first-string
byte.
b. Interrupt enable flag (IF): if it is set then the processor recognises the
maskable interrupt otherwise the maskable interrupt are ignored.
c. Trap flag (TF): if it is set, the processor goes into single-step mode.in
single-step mode processor executes one instruction at time, this type
of operation very useful for debugging programs.
Physical Address Calculation:
• The physical address is the 20-bit address normally available at address
line.
• The 20-bit physical address is used to access the external memory& input
device.
• But in the 8086 processor there are 20-bit registers to provide a 20-bit
physical address.
• But it uses tricky mechanism by using adder.
• In BIU to generate the 20-bit physical address.
• Adder takes the 16-bit address information from one of the 16-bit
segment register & another 16-bit address information from one of the
16-bit pointer or index register or general purpose register (BX) to form
20-bit physical address.
• The content of segment register is known as base address and content of
any other register known as offset address.
• These addresses are normally called as logical addresses.
• The adder shifts the segment register content by 4-bit position left or
multiply by 16 or 10h and then adds the offset address to form 20-bit
physical address.
EX:
1. If segment register CS = 3456 & offset from register IP = 1230.
• 3456x16 or 10h = 34560
+ 1230
35790
20-bit physical address 35790

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2. If DS = 1234 & SI= 5670

• 1234x16 or 10h = 12340
+ 5670
179B0
20-bit physical address 179B0
CS segment register: it is used to generate 20-bit physical address to fetch
instruction.
DS segment register: it is used to generate 20-bit physical address to access data
from memory or to access the source string.
SP segment register: it is used to generate 20-bit physical address to access data
from stack.
ES segment register: it is used to generate 20-bit physical address to access
destination string.
COMARISON BETWEEN MINMUM MODE AND MAXIMUM MODE:
Minimum mode Maximum mode
1. Only one processor i.e., 8086. Multiple processors with 8086, like
8087 & 8089.
2. MIN | MX is 1 indicate MIN | MX is 0 to indicate maximum
minimum mode. mode.
3. ALE for the latch is given by ALE for latch is given by 8288 bus
8086. controllers.
4. DEN & DT / R for the trans- DT / R for the trans- receiver given by
receiver given by 8086. 8288 bus controllers.
5. M | IO, RD, WR given by 8086 Instead of controls signals, like RD,
WR each processor generates status
signals called S2, S1, &S0.
6. INTA is given by 8086 in INTA is given by 8288 bus controllers.
response to an interrupt on
INTR line.
7. HOLD and HOLDA signals are RQ /GT lines are used for bus requests
used for bus request with DMA by other processors.
controller.
8. Circuit is simple. The circuit is complex.
9. Multi-processing cannot be Multi-processing can be performed.
performed .

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10.Performance is slower. High performance.

MINIMUM MODE CONFIGURATION:

• Below figure shows a minimum mode operation.
• In minimum mode only single processor is used.
• There is no multiprocessor configuration.
• MN/ MX pin is connected to +5V.
• All controls are generated by 8086 MP.
• The RAM, ROM and peripherals can directly interfaced to
microprocessor signals.

MINIMUM MODE
MAXIMUM MODE CONFIGURATION:
• This mode used in more complex systems containing co-processor
like 8087.
• Requires more control signals.
• MN/MX is connected to ground.
• 8086 MP does not generates control signals directly instead
generates a status signal.
• There is a multiprocessor configuration.

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• RQ/GTI and RQ/GTO, by using following two more processor added

for multiprocessor configuration.

MEMORY SEGMENTATION:
• The memory is an 8086 based system is organised as segmented memory.
• The CPU 8086 is able to access 1MB of physical memory.
• The complete 1MB of memory can be divided into 16 segments, each of
64KB size and is addressed by a one of the segment registers.
• Segment register point to starting location of a particular segment.
• The address of the segment may be assigned 0000h to F000h respectively.
• To address a specific memory location in a segment, we need an offset
address.
• The offset address values are from 0000h to FFFFh .

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PIN DIAGRAM OF 8086:

8086 developed by intel

It’s a 16-bit processor
It’s packaged in 40 pin DIP package
MULITPLEXED ADDRESS AND DATA BUS (AD15-AD0) (PIN 39&2-16)
• 8086 has 16-bit bidirectional data bus D15-D0.
• 20-bit address bus A19-0.
• To save pins D15-D0 & A15-A0 pin are multiplexed on A15-AD0.
MULTIPLEXED ADDRESS & STATUS BUS. A19-A16/S6-S3(pin 35-38)
• The address & status bus lines are multiplexed to prove the address
signals A19-16 & status bits S6-S3.
• S6 bit always remains A logic 0.
• S5 indicates the condition of the IF flag bits.
• S4 & S3 bit shows which segment is accessed during the current bus
cycle.

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S4 S3 function
0 0 Extra segment
0 1 Stack segment
1 0 Code or no
segment
1 1 Data segment
Read data(RD)-pin 32
• It is an active low o/p pin.
• Its activated whenever MP need information from m/l or i/o port.
• RD goes to high impedance state during hold acknowledge.
Ready signal Ready (pin 22)
• Its active high i/p pin.
• If ready pin is at logic 0 , MP enter into wait states & remain idle.
• If ready pin is at logic 1,it has no effect on the operation of MP.
Interrupt request INTR (pin 18):
• INTR is markable interrupt by i/o devices.
• MP will get interrupted only if all interrupt are enabled using ST1 (SET
interrupt flag) instruction.
• All interrupt are disabled using C21(CLEAR interrupt flag) instruction.
• INTR is non vectored interrupt(does not where to branch &to service).
• INTR =1 when IF=1,the MP enters an interrupt acknowledge cycle
Test interrupt (TEST) pin 23:
TEST is an input pin .
• TEST is tested by wait instruction when the MP is operating in maximum
mode.
• If TEST=1, the MP will stay in idle state.
• TEST is made “0” by 8087 coprocessor to indicate that computation is
finished.
• If TEST =0,the wait instruction functions as NOP.
Non maskable interrupt (NMI) pin 17:
• NMI is activated at the time of power failure & RAM parity error.
• When NMI activated by external devices , MP will be interrupts .

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• NMI is a vectored interrupt means it know where to branch & to service

& it cannot be masked.
• If INTR & NMI activated at a time , NMI serviced first because it has got
highest priority.
Reset Signal (Reset) pin 21:
• Reset input causes the MP to restart from scratch (predefined initial
state).
• This pin must be high for at least 4 clock cycles after reset of MP the values
of registers is as follows.
CS Register => FFFFh
IP Register => 0000h
DS Register => 0000h
ES Register => 0000h
SS Register => 0000h
Flag Register => 0000h
• After reset , the first instruction to be executed will be fetched from
FFFF0H.
Clock CLK (pin 19):
• Clock provides the necessary timing for the MP .
• Clock signal must have duty cycle of 33%.
• Clock generated using an external clock generator.
• 8086 MP comes in different clock speeds 5 MHz, 8MHz, & 10MHz.
+5V power supply input Vcc (pin 40):
• The power supply provides a +5V to the MP .
GND (Pin 1,20):
• Pin number 1 & 20 must be connected to the ground for proper operation.
MN / MX (Pin 33):
• MP works in 2 modes
1. Maximum mode.

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2. Minimum mode.
• MN / MX =1, MP works in Minimum mode.
• MN / MX =0, MP works in Maximum mode.
Bus High enable BHE / S7 (Pin 34):
• BHE is used to enable the most significant data bits (D15-D8) during read
& write operation.
• S7 is always logic 1.
Physical Memory Organisation:
• The physical memory of 8086 is shown in below figure.
• The number of bits stored in M/L is only 8-bits.
• Every byte stored in M/L has unique address.
• Physical memory is divided into two bank each of 512kb (total physical
memory size is of 1 MB)
• The banks are called lower bank and upper bank.
• The lower bank contain only even addresses like 0,2,4 etc , and D7-D0
data lines connected to it.
• The upper bank contains only odd addresses like 1,3,5 etc & D15-D8 data
lines connected to it .
• In order to select any M/L, the 19-bit address is obtained by A19-A1.
• To select lower bank A0 bit is used.
• To select/enable upper bank BHE pin is used

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