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Microarchitecture Lab

The lab session focuses on implementing a 16-bit accumulator machine using Logisim software, divided into four sessions where pairs of students will create and upload their results by June 2nd. Students must submit a zip archive containing their filled timetables, circuit files, and an optional explanation document, with points awarded for correct timetables, functional circuits, and understanding the program. The document outlines the processor's architecture, instruction set, and provides resources and tasks for completing the lab work.

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7 views7 pages

Microarchitecture Lab

The lab session focuses on implementing a 16-bit accumulator machine using Logisim software, divided into four sessions where pairs of students will create and upload their results by June 2nd. Students must submit a zip archive containing their filled timetables, circuit files, and an optional explanation document, with points awarded for correct timetables, functional circuits, and understanding the program. The document outlines the processor's architecture, instruction set, and provides resources and tasks for completing the lab work.

Uploaded by

ritaberrada06
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Fundamentals of Programming

Lab session – Implementation of an accumulator machine in


Logisim

Rules
• This lab session is split into 4 sessions of 1 hour and 30 minutes.
• You will be working in pairs.
• Each team must upload their result on edunao at the end of the last session, i.e., on the 2nd
of June, 17:00.
• You must deposit a zip archive named name1_name2.zip containing:
– The excel file containing the filled timetables and equations.
– Your circuit as a .circ file.
– The ese1010.jar file.
It is important that you respect all the criteria to receive all the points.
– (Optional) A word / text document explaining what the last program does.
• Here is how the points are distributed:
– 3 points for the correct timetables and equations.
– 3 points for the working circuit in Logisim.
– 1 bonus point if you manage to understand what the last program does.

Description of the processor


This lab session aims to design a simple processor using Logisim software. More precisely, we aim
to create a simple 16-bit accumulator machine with the following characteristics:
• operands are 16-bit integers
• addresses are 12 bits
• the instructions are 16-bit words with three fields:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A operation argument

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– the most significant bit (bit 15) indicates the addressing mode:
∗ 0 (Immediate): the argument contains the operand value.
∗ 1 (Indirect): the argument contains the address of the address of the operand value
(read it twice).
– bits 12 to 14 indicate the operation to be performed:

Textual opcode Binary opcode Description


LDA 000 Loading the content of the operand in the accumulator.
(immediate and indirect addressing modes)
STA 001 Store the content of the operand into memory using the address
contained in the argument (only in indirect addressing mode)
ADD 010 Add the content of the accumulator to the content of the operand
and store the result in the accumulator (immediate and indirect)
SUB 011 Subtract the content of the operand to the content of the accumulator
and store the result in the accumulator (immediate and indirect)
JMP 100 Unconditional jump
The address of the next instruction is in the argument.
JEQ 101 Jump if the content of the accumulator is zero (use the Z bit of the ALU)
The address of the next instruction is in the argument.
JLT 110 Jump if the content of the accumulator is strictly negative (use the N bit of
the ALU). The address of the next instruction is in the argument.
CLR 111 Set the accumulator content to zero.
(You can generate a zero from the UAL and send it to the accumulator)

– the least significant 12 bits contain the operation’s argument (value or address).

• Since the CLR instruction has no argument (implicit addressing mode), only the bits 12 to
14 are decoded.

Elements provided for the study


Logisim is a free software suitable for simulating logic, combinatorial and sequential circuits. In
particular, it is suited for the creation of small computers. Logisim has numerous standard com-
ponents. On top of it, we provide a library of components produced at CentraleSupelec called
ESE1010, which notably includes an arithmetic and logic unit (ALU) and a Control Unit.
The kit used for this lab session is a ZIP archive containing (once unzipped):

• the logisim-2.7.1.jar file: the Logisim simulator.

• the ese1010.jar file: the CentraleSupélec library of Logisim components.

• the ese1010.circ file: contains the described computer skeleton.

• the test files test_unit.mem and test_fct.mem: two test programs described below.

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The top part of the diagram includes 8 generic control signals called C1 to C8. You can use
these signals to turn on the controlled buffer components.
The main part of the diagram contains control signals of the data path elements. Their meaning
is given below:

• PCC: the program counter register command (PC register);

• CC command: determines what is loaded in the PC register when PCC is activited: 0 (PC
+ 1); 1 (PC register input);

• AccC: Accumulator register command (Acc register);

• MARC: Memory Address Register command (MAR register);

• IMC: the memory input command (MI);

• RW: the memory command (for reading RW=1 or writing RW=0). When reading command,
the memory word located at the address given by the MAR register is available at the output
memory (OM). In writing command, the value of the memory input (MI) is written to the
address given by the MAR register;

• IRC: Instruction register command (IR register);

• Sext: control of the extension sign for the 12 least significant bits of the IR register (argument
part) to 16 bits (extension if Sext = 1).

• U0 to U3: ALU command,

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On top of the previous explanations, here are additional resources to help you with logisim:
• A small documentation for the components provided in the ese1010 library (https://wdi.
centralesupelec.fr/architecture/BE/Ese1010-documentation-En)
• A description of the controlled buffer component which may prove useful: (https://www.
cburch.com/logisim/docs/2.3.0/libs/gates/controlled.html)
No prior knowledge of Logisim is expected of you. If you struggle too much with the software, ask
for help.

Work to do
0.1 Timetable and equations
• Determine the data path and timetable for executing all operations (and complete the micro-
processor schema).
• Write signal equations to be used by the Control Unit.
A Empty_Timetable.xlsx file is available on edunao for you to fill in with your answers.

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0.2 Implementation
Using Logisim, write the obtained equations into the Control Unit.

0.3 Tests
The skeleton of the computer is equipped with a clock component. To start the simulation, you
must activate it in the Simulate menu. Check that:

• Simulation Enabled is checked;

• Ticks Enabled is checked;

• In Tick Frequency, choose a frequency that is not too high (e.g. 8Hz) to start.

Two test programs are provided as files. To use one of them, you need to load it into the memory
component.
The first program file (test_unit.mem) tests each instruction according to the two addressing
modes. Lines labelled ERROR should not be executed by the designed processor.

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If the test program is correctly executed, you can now execute the second program (test_fct.mem)
and determine what it does and whether the obtained result is correct:

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