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Risc Processors

The document compares Reduced Instruction Set Architecture (RISC) and Complex Instruction Set Architecture (CISC), highlighting their fundamental differences in instruction complexity and execution. RISC focuses on simpler instructions that execute in a single clock cycle, while CISC uses complex instructions that may take multiple cycles. The document also outlines the advantages and disadvantages of RISC, including faster execution and easier pipelining, but notes the increased program length due to more instructions needed for operations.

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1 views5 pages

Risc Processors

The document compares Reduced Instruction Set Architecture (RISC) and Complex Instruction Set Architecture (CISC), highlighting their fundamental differences in instruction complexity and execution. RISC focuses on simpler instructions that execute in a single clock cycle, while CISC uses complex instructions that may take multiple cycles. The document also outlines the advantages and disadvantages of RISC, including faster execution and easier pipelining, but notes the increased program length due to more instructions needed for operations.

Uploaded by

Sandeep
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Computer Organization | RISC and CISC

Reduced Instruction Set Architecture (RISC) –

The main idea behind is to make hardware simpler by using an instruction set composed of a few
basic steps for loading, evaluating and storing operations just like a load command will load data,
store command will store the data.

Complex Instruction Set Architecture (CISC) –

The main idea is that a single instruction will do all loading, evaluating and storing operations
just like a multiplication command will do stuff like loading data, evaluating and storing it, hence
it’s complex.

Both approaches try to increase the CPU performance


• RISC: Reduce the cycles per instruction at the cost of the number of instructions per
program.
• CISC: The CISC approach attempts to minimize the number of instructions per
program but at the cost of increase in number of cycles per instruction.

When programming is done using assembly language, a need is felt to make instruction do more
task because programming in assembly is tedious and error prone due to which CISC architecture
evolved but with up rise of high level language dependency on assembly reduced RISC
architecture prevailed.

Characteristic of RISC –
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipeline can be achieved.
Characteristic of CISC –
1. Complex instruction, hence complex instruction decoding.
2. Instruction are larger than one word size.
3. Instruction may take more than single clock cycle to get executed.
4. Less number of general purpose register as operation get performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.

Example – Suppose we have to add two 8-bit number:


• CISC approach: There will be a single command or instruction for this like ADD
which will perform the task.
• RISC approach: Here programmer will write first load command to load data in
registers then it will use suitable operator and then it will store result in desired location.
So, add operation is divided into parts i.e. load, operate, store due to which RISC programs are
longer and require more memory to get stored but require less transistors due to less complex
command.
Difference –

RISC CISC

Focus on software Focus on hardware

Uses both hardwired and micro

Uses only Hardwired control unit programmed control unit

Transistors are used for storing complex

Transistors are used for more registers Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Can perform REG to REG or REG to

Arithmetic operations MEM or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

A instruction execute in single clock

cycle Instruction take more than one clock cycle

Instruction are larger than size of one

A instruction fit in one word word


Difference Between CISC and RISC

Architectural Complex Instruction Set Reduced Instruction Set


Characterstics Computer(CISC) Computer(RISC)

Instruction size and Large set of instructions with variable Small set of instructions
format formats (16-64 bits per instruction). with fixed format (32 bit).

Data transfer Memory to memory. Register to register.

Most micro coded using control memory


Mostly hardwired without
CPU control (ROM) but modern CISC use hardwired
control memory.
control.

Instruction type Not register based instructions. Register based instructions.

Memory access More memory access. Less memory access.

Clocks Includes multi-clocks. Includes single clock.

Instructions are reduced and


Instruction nature Instructions are complex.
simple.

RISC Processor Architecture (Block diagram)

RISC processor is implemented using the hardwired control unit. The hardwired control unit
produces control signals which regulate the working of processors hardware. RISC
architecture emphasizes on using the registers rather than memory.

This is because the registers are the ‘fastest’ available memory source. The registers are
physically small and are placed on the same chip where the ALU and the control unit are
placed on the processor. The RISC instructions operate on the operands present
in processor’s registers.

Below we have the block diagram for the RISC architecture.


Advantages and Disadvantages of RISC Processor

Advantages of RISC Processor

1. RISC instructions are simpler machine instruction.


2. RISC instructions are hardwired to fasten the execution.
3. There are very fewer instructions in s RISC instruction set.
4. RISC instruction has simple addressing modes.
5. RISC instruction executes faster because most of instruction operates on processor
register and there is no need to access memory for each instruction.
6. It is easy to pipeline RISC instruction as all instruction is of fixed size and opcode and
operand are located in the same position in the word.
7. RISC instructions execute one instruction per clock cycle.

Disadvantages of RISC Processor

1. RISC instruction size is reduced but more instructions are required to perform an operation
when compared with CISC. So, we can say that the length of the program is increased.
2. The machine instructions are hardwired in RISC so, it would cost if any instruction needs
modification.
3. It finds is difficulty in processing complex instruction and complex addressing mode.
4. RISC instructions do not allow direct memory to memory transfer, it requires Load and Store
instructions to do so.

Examples of RISC processors

MIPS, SPARC, IBM POWER instruction set, Alpha, RISC-V, ARM architecture.

Key Takeaways

• RISC instructions are simple and engages one word in memory.


• RISC instructions are of fixed size, the opcode and the operands in the instruction are located
in the same position within a word in different instructions.
• One instruction in RISC architecture executes in one clock cycle.
• The instruction size is reduced but, it has increased the program length.
• The pipelining of RISC instruction is easier.
• The machine instructions in RISC architecture are hardwired.
• RISC instruction operates only on register operands.
• RISC instruction executes faster as registers are placed in the processor chip which is faster
available memory resource.
• RISC instruction performs memory to memory transfer via Load and Store instruction.

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