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Verilog Answers VTU DSDV 2022

The document outlines the syllabus-based answers for VTU DSDV 2022, covering Verilog operators, their precedence, and examples of a 4-bit adder design. It explains non-blocking statements, the differences between tasks and functions, and provides structural descriptions of a half adder and binding of modules. The content includes Verilog code snippets for practical understanding.

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3 views5 pages

Verilog Answers VTU DSDV 2022

The document outlines the syllabus-based answers for VTU DSDV 2022, covering Verilog operators, their precedence, and examples of a 4-bit adder design. It explains non-blocking statements, the differences between tasks and functions, and provides structural descriptions of a half adder and binding of modules. The content includes Verilog code snippets for practical understanding.

Uploaded by

matlab2rs
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VTU DSDV 2022 Syllabus-Based Answers

Question 1a (10 Marks)

----------------------

Explain the operators of Verilog (any 5) and explain the precedence of operators.

Operators:

1. Arithmetic: +, -, *, /, %

2. Relational: ==, !=, >, <, >=, <=

3. Logical: &&, ||, !

4. Bitwise: &, |, ^, ~

5. Shift: <<, >>

Operator Precedence (High to Low):

1. Unary: ~, !

2. Multiplicative: *, /, %

3. Additive: +, -

4. Shift: <<, >>

5. Relational: <, >, <=, >=

6. Equality: ==, !=

7. Bitwise AND: &

8. Bitwise XOR/XNOR: ^, ^~

9. Bitwise OR: |

10. Logical AND: &&

11. Logical OR: ||

12. Conditional: ?:

13. Assignment: =, <=


Question 1b (10 Marks)

----------------------

Derive a Gate level design of 4-bit adder and show the assignment of ports using Verilog.

Verilog Code:

module full_adder(input a, b, cin, output sum, cout);

assign {cout, sum} = a + b + cin;

endmodule

module four_bit_adder(

input [3:0] a, b,

input cin,

output [3:0] sum,

output cout

);

wire c1, c2, c3;

full_adder fa0(a[0], b[0], cin, sum[0], c1);

full_adder fa1(a[1], b[1], c1, sum[1], c2);

full_adder fa2(a[2], b[2], c2, sum[2], c3);

full_adder fa3(a[3], b[3], c3, sum[3], cout);

endmodule

Question 1c (5 Marks)

---------------------

Explain non-blocking statements with example.


Non-blocking statements use '<=':

always @(posedge clk) begin

a <= b;

b <= c;

end

Question 4a (10 Marks)

----------------------

Difference between Tasks and Functions:

| Feature | Task | Function |

|---------------|-----------------------------|-------------------------------|

| Return value | None | Must return a value |

| Time Control | Allowed | Not allowed |

| Usage | Complex | Simple |

| Call method | Called independently | Called within expressions |

| I/O | Input/output allowed | Only inputs |

Task Example:

module task_demo;

task display_num;

input [3:0] num;

begin

$display("Number is %d", num);

end

endtask
initial begin

display_num(4'b1010);

end

endmodule

Question 4b (10 Marks)

----------------------

Structural description of Half Adder:

module xor_gate(a, b, y);

assign y = a ^ b;

endmodule

module and_gate(a, b, y);

assign y = a & b;

endmodule

module half_adder(a, b, sum, carry);

xor_gate x1(a, b, sum);

and_gate a1(a, b, carry);

endmodule

Question 4c (5 Marks)

---------------------

Binding two modules:

module adder(input a, b, output sum);


assign sum = a ^ b;

endmodule

module top_module;

wire s;

reg a = 1, b = 0;

adder my_adder(.a(a), .b(b), .sum(s));

initial begin

#1 $display("Sum = %b", s);

end

endmodule

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