Digital Computers

A Digital computer can be considered as a digital system that performs various computational tasks.

The first electronic digital computer was developed in the late 1940s and was used primarily for numerical
computations.

By convention, the digital computers use the binary number system, which has two digits: 0 and 1. A binary
digit is called a bit.

A computer system is subdivided into two functional entities: Hardware and Software.

The hardware consists of all the electronic components and electromechanical devices that comprise the
physical entity of the device.

The software of the computer consists of the instructions and data that the computer manipulates to perform
various data-processing tasks.

Block Diagram of a Digital Computer:

o The Central Processing Unit (CPU) contains an arithmetic and logic unit for manipulating data, a
number of registers for storing data, and a control circuit for fetching and executing instructions.
o The memory unit of a digital computer contains storage for instructions and data.
o The Random Access Memory (RAM) for real-time processing of the data.
o The Input-Output devices for generating inputs from the user and displaying the final results to the
user.
o The Input-Output devices connected to the computer include the keyboard, mouse, terminals,
magnetic disk drives, and other communication devices.
Interconnection between Functional Components
A computer consists of input unit that takes input, a CPU that processes the input and an output unit that
produces output. All these devices communicate with each other through a common bus. A bus is a
transmission path, made of a set of conducting wires over which data or information in the form of electric
signals is passed from one component to another in a computer. The bus can be of three types – Address
bus, Data bus and Control Bus.

Following figure shows the connection of various functional compon

components:
 The address bus carries the address location of the data or instruction. The data bus carries data from one
component to another and the control bus carries the control signals. The system bus is the common
communication path that carries signalss to/from CPU, main memory and input/output devices. The
input/output devices communicate with the system bus through the controller circuit which helps in
managing various input/output devices attached to the computer.

Computer Architecture:
 Computer Architecture is concerned with the way hardware components are connected together to
form a computer system.

 It acts as the interface between hardware and software.

 Computer Architecture helps us to understand the functionalities of a system.

 A programmer
mer can view architecture in terms of instructions, addressing modes and registers.

 While designing a computer system architecture is considered first.

 Computer Architecture deals with high

high-level design issues.

 Architecture involves Logic (Instruction sets, Addressing modes, Data types, Cache optimization)

Computer Organization:
 Computer Organization is concerned with the structure and behavior of a computer system as seen by
the user.

 It deals with the components of a connection in a system.

 Computer Organization tells us how exactly all the units in the system are arranged and interconnected.
  Whereas Organization expresses the realization of architecture.

 An organization is done on the basis of architecture.

 Computer Organization deals with low-level design issues.

 Organization involves Physical Components (Circuit design, Adders, Signals, Peripherals)

Computer Design:
Computer Design is the structure in which components relate to each other. The designer deals with a
particular level of system at a time and there are different types of issues at different levels. At each level,
the designer is concerned with the structure and function. The structure is the skeleton of the various
components related to each other for communication. The function is the activities involved in the system.
Following are the issues in computer design:

 Assumption of infinite speed:

It can’t be assumed the infinite speed of the computer as it is not practical to assume the infinite
speed. It creates problems in designers’ thinking as well.
 Assumption of infinite Memory:
Like the speed of the computer, memory also can’t be assumed infinite. Storage is always finite and
this is an issue in computer design.
 Speed mismatch between memory and processor:
Sometimes it is possible that the speed of memory and processor does not match. It may be memory
speed is faster or processor speed is faster. A mismatch between memory and processor leads to
create problems in designing.
 Handling of bugs and errors:
Handling bugs and errors are huge responsibility of any computer designer. Bugs and errors lead to
the failure of the computer system. Sometimes these errors may be more dangerous.
 Multiple processors:
Designing a computer system with multiple processors leads to the huge task of management and
programming. It is a big issue in computer design.
 Multiple threads:
A computer system with multiple threads is always a threat to the designer. A computer with
several threads should be able to multi-tasking and multi-processing.
 Shared memory:
If there are several processes to be executed at a time then all the processes share the same memory
space. It should be managed in a specific way so that collision does not happen.
 Disk access:
Disk management is the key to computer design. There are several issues with disk access. It may
be possible that the system does not support multiple disk access.
  Better performance:
It is always an issue. A designer always tries to simplify the system for better performance in
reducing power and less cost.
 Performance: One of the biggest challenges in computer design is optimizing performance.
Designers need to balance factors such as processing power, memory capacity, and input/output
speed to create a system that is fast and efficient.
 Power consumption: As computing devices become more ubiquitous, power consumption has
become a critical design consideration. Designers need to create systems that are energy-efficient to
reduce the impact on the environment and improve battery life.
 Security: With the growing amount of sensitive data being stored and processed on computing
devices, security is a major issue. Designers need to build in strong encryption and authentication
measures to prevent unauthorized access and data breaches.
 Compatibility: As computing devices become more diverse, ensuring compatibility across
platforms and devices is a key challenge. Designers need to create systems that can run seamlessly
on a variety of operating systems and hardware configurations.
 User experience: The user experience is a critical consideration in computer design. Designers
need to create intuitive interfaces and experiences that are easy to use and navigate.
 Reliability: Computing devices are expected to work reliably and consistently. Designers need to
create systems that are resilient and can operate without failure for extended periods of time.

Logic Gates
o The logic gates are the main structural part of a digital system.
o Logic Gates are a block of hardware that produces signals of binary 1 or 0 when input logic requirements
are satisfied.
o Each gate has a distinct graphic symbol, and its operation can be described by means of algebraic
expressions.
o The seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
o The relationship between the input-output binary variables for each gate can be represented in tabular
form by a truth table.
o Each gate has one or two binary input variables designated by A and B and one binary output variable
designated by x.

AND GATE:
The AND gate is an electronic circuit which gives a high output only if all its inputs are high. The AND operation is
represented by a dot (.) sign.
OR GATE:
The OR gate is an electronic circuit which gives a high output if one or more of its inputs are high. The operation
performed by an OR gate is represented by a plus (+) sign.

NOT GATE:
The NOT gate is an electronic circuit which produces an inverted version of the input at its output. It is also known
as an Inverter.

NAND GATE:
The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT gate. The NAND gate gives a high
output if any of the inputs are low. The NAND gate is represented by a AND gate with a small circle on the output.
The small circle represents inversion.
NOR GATE:
The NOT-OR (NOR)) gate which is equal to an OR gate followed by a NOT gate. The NOR gate gives a low output if
any of the inputs are high. The NOR gate is represented by an OR gate with a small circle on the output. The small
circle represents inversion.

Exclusive-OR/ XOR
OR GATE:
The 'Exclusive-OR'
OR' gate is a circuit which will give a high output if one of its inputs is high but not both of them. The
XOR operation is represented by an encircled plus sign.
EXCLUSIVE-NOR/Equivalence
NOR/Equivalence GATE:
The 'Exclusive-NOR' gate is a circuit that does the inverse operation to the XOR gate. It will give a low output if one
of its inputs is high but not both of them. The small circle represents inversion.

Flip-Flop:

S-R Flip-flop/Basic Flip-Flop

Flip flops are an application of logic gates. A flip

flip-flop
flop circuit can remain in a binary state indefinitely (as long
as power is delivered to the circuit) until directed by an input signal to switch states.

S-R flip-flop stands for SET-RESET

RESET flip
flip-flops.

The SET-RESET flip-flop

flop neither consists of two NOR gates and also two NAND gates.

These flip-flops are also called S-R

R Latch.

The design of these flip flops also includes two inputs, called the SET [S] and RESET [R]. There are also two
outputs, Q and Q'.
Clocked S-R Flip-Flop

The operation of a basic flip-flop

flop can be modified by providing an additional control input that determines
when the state of the circuit is to be changed.

The limitation with a S-R flip-flop

flop using NOR and NAND gate is the invalid state. This problem can be
overcome by using a stable SR flip-flop
flop that can change outputs when certain invalid states are met, regardless
of the condition of either the Set or the Reset inputs.
A clock pulse is given to the inputs of the AND Gate. If the value of the clock pulse is '0', the out
outputs of both
the AND Gates remain '0'.
 Computer Registers:

Registers are a type of computer memory used to quickly accept, store, and transfer data and instructions that
are being used immediately by the CPU. The registers used by the CPU are often termed as Processor
registers.

A processor register may hold an instruction, a storage address, or any data (such as bit sequence or individual
characters).

The computer needs processor registers for manipulating data and a register for holding a memory address.
The register holding the memory location is used to calculate the address of the next instruction after the
execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer:

Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.
 o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the memory location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the memory
location.
o The Program Counter (PC) also contains 12 bits which hold the address of the next instruction to be
read from memory after the current instruction is executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input data.

Register Transfer
Registers define the storage area that influences the data and instructions. It can send data and instructions
from one register to another register, memory to register, and memory to memory, the register transfer
approach is used. This register is used in the transmission of data and instructions between memory and
processors to implement the particular tasks.

The data transfer from one register to another is named in representative design using a replacement operator.
The statement is

R2←R1
It indicates a transfer of the content of register R1 into register R2. It labeled a replacement of the content of
R2 by the content of R1. The content of the source register R1 does not shift after the transfer.

A statement that specifies a register transfer involves that circuits are accessible from the outputs of the source
register to the inputs of the destination register and that the destination register has a corresponding load
efficiency.

We need the transfer to appear only under a fixed control condition. This can be displayed using an if-then
statement.

If (P = 1) then (R2 ← R1)

Where P is a control signal created in the control area. A control function is a Boolean variable that is similar
to 1 or 0. The control function is contained in the statement as follows −

P: R2 ← R1

The control condition is terminated with a colon. It represents the specification that the transfer operation is
implemented by the hardware only if P = 1. Each statement written in a register transfer notation indicates a
hardware structure for executing the transfer.

The diagram demonstrates the block diagram that shows the transfer from R1 to R2. The n outputs of register
R1 are linked to the n inputs of register R2. The letter n can denote any number of bits for the register. It will
be restored by an actual number when the duration of the register is established.

Register R2 has a load input that is activated by the control variable P. It is considered that the control variable
is synchronized with the equivalent clock like the one used to the register.
As displayed in the timing diagram, P is activated in the control area by the increasing edge of a clock pulse at
time t. The next positive transition of the clock at time t + 1 discovers the load input active and the data inputs
of R2 are then loaded into the register in parallel. P can go back to 0 at time t + 1. The transfer will appear
with each clock pulse transition while P stays active.

The clock is not contained as a variable in the register transfer statements. It is considered that all transfers
appear during a clock edge transition. The control condition including P becomes active only after time t, the
actual transfer does not appear until the register is triggered by the next positive transition of the clock at time
t + 1.

Basic symbols of Register Transfer Language (RTL) :

Symbol Description Example

Letters and Numbers Denotes a Register MAR, R1, R2

R1(8-bit)
() Denotes a part of register
R1(0-7)

<- Denotes a transfer of information (Replacement Operator) R2 <- R1

 Symbol Description Example

R1 <- R2
, Specify two micro-operations
micro of Register Transfer
R2 <- R1

P : R2 <- R1
: Denotes conditional operations
if P=1

Naming Operator (:=) Denotes another name for an already existing register/alias Ra := R1

Multiplexers:
A Multiplexer (MUX) can be described as a combinational circuit that receives binary information from one
of the 2^n input data lines and directs it to a single output line.

The selection of a particular input data line for the output is decided on the basis of selection lines.

The multiplexer is often called as data selector since it selects only one of many data inputs.

Note: A 2^n-to-11 multiplexer has 2^n input data lines and n input selection
selection lines whose bit combinations
determine which input data are selected for the output.

The following image shows the block diagram of a 4 * 1 Multiplexer.

Out of these four input data lines, a particular input data line will be connected to the output based on the
combination of inputs present at these two selection lines.
Note: A truth table describing the circuit needs 64 rows since six input variables can have 2^n binary
combinations. This will result in an excessively long table. Therefore, a more convenient way to describe the
operation of multiplexers is using a function table.

The function table for a 4 * 1 Multiplexer can be represented as:

S1 S0 y

0 0 I0

0 1 I1

1 0 I2

1 1 13

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer information from one
register to another. The number of wires connecting all of the registers will be excessive if separate lines are
used between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information between registers in a multi-
register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary information is
transferred one at a time. Control signals determine which register is selected by the bus during a particular
register transfer.

The following block diagram shows a Bus system for four registers. It is constructed with the help of four 4 *
1 Multiplexers each having four data inputs (0 through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand the input-output configuration of a Bus
system for four registers. For instance, output 1 of register A is connected to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers. The selection
lines choose the four bits of one register and transfer them into the four-line
four common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are
selected and applied to the outputs that forms the bus. This, in turn, causes the bus lines to receive the content
of register A since the outputs of this register are connected
connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content provided by
register B.

The following function table shows the register that is selected by the bus for each of the four
f possible binary
values of the Selection lines.
A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered as a digital circuit that has three gates, two of which are signals
equivalent to logic 1 and 0 as in a conventional gate. However, the third gate exhibits a high-impedance state.

The most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.

o The outputs generated by the four buffers are connected to form a single bus line.
o Only one buffer can be in active state at a given point of time.
o The control inputs to the buffers determine which of the four normal inputs will communicate with
the bus line.
o A 2 * 4 decoder ensures that no more than one control input is active at any given point of time.
 Memory Transfer

Most of the standard notations used for specifying operations on memory transfer are stated below.

o The transfer of information from a memory unit to the user end is called a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from the memory
word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory word (M)
selected by address register (AR).
 Combinational Circuits
A combinational circuit comprises of logic gates whose outputs at any time are determined directly from the
present combination of inputs without any regard to previous inputs.

A combinational circuit performs a specific information-processing

information processing operation fully specified logically by a set
of Boolean functions.

The basic components of a combinational circuit are: input variables, logic gates, and output variables.

The 'n' input variables come from an external source whereas the 'm' output variables go to an external
destination. In many applications, the source or destination is storage registers.

Design procedure of a Combinational Circuit

The design procedure of a combinational circuit involves the following steps:

1. The problem is stated.

2. The total number of available input variables and required output variables is determined.
3. The input and output variables are allocated with letter symbols.
4. The exact truth table that defines the required relationships between inputs and outputs is derived.
5. The simplified Boolean function is obtained from each output.
6. The logic diagram is drawn.

The combinational circuit that performs the addition of two bits is called a half adder and the one that
performs the addition of three bits (two significant bits and a previous carry) is a full adder.

Half – Adder:
A Half-adder
adder circuit needs two binary inputs and two binary outputs. The input variable shows the
t augend and
addend bits whereas the output variable produces the sum and carry. We can understand the function of a half
half-
adder by formulating a truth table. The truth table for a half
half-adder is:

o 'x' and 'y' are the two inputs, and S (Sum) and C (Carry) are the two outputs.
o The Carry output is '0' unless both the inputs are 1.
 o 'S' represents the least significant bit of the sum.

The simplified sum of products (SOP) expressions is:

S = x'y+xy', C = xy

The logic diagram for a half-adder

adder circuit can be repre
represented as:

Full – Adder:
This circuit needs three binary inputs and two binary outputs. The truth table for a full
full-adder
adder is:

o Two of the input variable 'x' and 'y', represent the two significant bits to be added.
o The third input variable 'z', represents the carry from the previous lower significant position.
o The outputs are designated by the symbol 'S' for sum and 'C' for carry.
o The eight rows under the input variables designate all possible combinations of 0's, and 1's that these
variables may have.
o The input-output
output logical relationship of the full-adder
full adder circuit may be expressed in two Boolean
functions, one for each output variable.
o Each output Boolean function can be simplified by using a unique map method.
The logic diagram for a full-adder
adder circuit can be represented as:

Arithmetic Micro-operations
operations:

In general, the Arithmetic Micro-operations

operations deals with the operations performed on numeric data stored in the
registers.

The basic Arithmetic Micro-operations

operations are classified in the following categories:
categorie

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift

Some additional Arithmetic Micro-operations

operations are classified as:

1. Add with carry

2. Subtract with borrow
3. Transfer/Load, etc.
 The following table shows the symbolic representation of various Arithmetic Micro-operations.

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 – 1 Decrement the contents of R1 by one

1. Binary Adder

The Add micro-operation requires registers that can hold the data and the digital components that can perform
the arithmetic addition.

A Binary Adder is a digital circuit that performs the arithmetic sum of two binary numbers provided with any
length.

A Binary Adder is constructed using full-adder circuits connected in series, with the output carry from one
full-adder connected to the input carry of the next full-adder.

The following block diagram shows the interconnections of four full-adder circuits to provide a 4-bit binary
adder.
 o The augend bits (A) and the addend bits (B) are designated by subscript numbers from right to left,
with subscript '0' denoting the low-order bit.
o The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C4 is the resultant
output carry generated by the last full-adder circuit.
o The output carry from each full-adder is connected to the input carry of the next-high-order full-adder.
o The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend bits.
o The n data bits for the A and B inputs come from different source registers. For instance, data bits
for A input comes from source register R1 and data bits for B input comes from source register R2.
o The arithmetic sum of the data inputs of A and B can be transferred to a third register or to one of the
source registers (R1 or R2).

Binary Adder-Subtractor

The Subtraction micro-operation can be done easily by taking the 2's compliment of addend bits and adding it
to the augend bits.

The Arithmetic micro-operations like addition and subtraction can be combined into one common circuit by
including an exclusive-OR gate with each full adder.

The block diagram for a 4-bit adder-subtractor circuit can be represented as:

o When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and when the mode input
is at a high logic, i.e. '1', the circuit act as a subtractor.
o The exclusive-OR gate connected in series receives input M and one of the inputs B.
 o When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit performs A plus B.
o When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The circuit performs the
operation A plus the 2's complement of B.

Binary Incrementer

The increment micro-operation adds one binary value to the value of binary variables stored in a register. For
instance, a 4-bit register has a binary value 0110, when incremented by one the value becomes 0111.

The increment micro-operation is best implemented by a 4-bit combinational circuit incrementer. A 4-bit
combinational circuit incrementer can be represented by the following block diagram.

o A logic-1 is applied to one of the inputs of least significant half-adder, and the other input is
connected to the least significant bit of the number to be incremented.
o The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-
adder.
o The binary incrementer circuit receives the four bits from A0 through A3, adds one to it, and
generates the incremented output in S0 through S3.
o The output carry C4 will be 1 only after incrementing binary 1111.
Hardware Implementation of arithmetic circuits
Logic Micro-operations:
 There are 16 different logic operations that can be performed with two binary variables.

 They can be determined from all possible truth tables obtained with two binary variables as shown
in Table below.

 In this table, each of the 16 columns F0 through F15 represents a truth table of one possible Boolean
function for the two variables x and y.

 Note that the functions are determined from the 16 binary combinations that can be assigned to F.
The 16 Boolean functions of two variables x and y are expressed in algebraic form in the first column
of Table below.

 The 16 logic micro-operations are derived from these functions by replacing variable x by the binary
content of register A and variable y by the binary content of register B.

 It is important to realize that the Boolean functions listed in the first column of Table below
represent a relationship between two binary variables x and y.

 The logic micro-operations listed in the second column represent a relationship between the binary
content of two registers A and B.

 Each bit of the register is treated as a binary variable and the micro-operation is performed on the
string of bits stored in the registers.
 

Hardware Implementation:
 The hardware implementation of logic rnicrooperations requires that logic gates be inserted for
each bit or pair of bits in the registers to perform the required logic function.

 Although there are 16 logic rnicrooperations, most computers use only four-AND, OR, XOR
(exclusive-OR), and complement from which all others can be derived.

 Figure below shows one stage of a circuit that generates the four basic logic rnicrooperations .

 It consists of four gates and a multiplexer. Each of the four logic operations is generated through a
gate that performs the required logic.

 The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs
S1 and S0 choose one of the data inputs of the multiplexer and direct its value to the output.

 The diagram shows one typical stage with subscript i. For a logic circuit with n bits, the diagram
must be repeated n times for i = 0, 1, 2, ... , n - 1.

 The selection variables are applied to all stages. The function table in Fig. below lists the logic
rnicro-operations obtained for each combination of the selection variables.
 

Shift Micro-Operations:
Shift micro-operations are those micro-operations that are used for the serial transfer of information. These
are also used in conjunction with arithmetic micro-operation, logic micro-operation, and other data-
processing operations. There are three types of shift micro-operations: 1.
1. Logical Shift:
It transfers the 0 zero through the serial input. We use the symbols ‘<<‘ for the logical left shift and ‘>>‘ for
the logical right shift.
Logical Left Shift:
In this shift, one position moves each bit to the left one by one. The Empty least significant bit (LSB) is filled
with zero (i.e, the serial input), and the most significant bit (MSB) is rejected.

The left shift operator is denoted by the double left arrow key (<<). The general syntax for the left shift is
shift-expression << k.
 Logical Left Shift

Note: Every time we shift a number towards the left by 1 bit it multiplies that number by 2.

Logical Right Shift

In this shift, each bit moves to the right one by one and the least significant bit(LSB) is rejected and the
empty MSB is filled with zero.

The right shift operator is denoted by the double right arrow key (>>). The general syntax for the right shift
is “shift-expression >> k”.

Logical Right Shift

Note: Every time we shift a number towards the right by 1 bit it divides that number by 2.
2. Arithmetic Shift:
The arithmetic shift micro-operation moves the signed binary number either to the left or to the
right position.
Following are the two ways to perform the arithmetic shift.

1. Arithmetic Left Shift

2. Arithmetic Right Shift
Arithmetic Left Shift:
In this shift, each bit is moved to the left one by one. The empty least significant bit (LSB) is filled
with zero and the most significant bit (MSB) is rejected. Same as the Left Logical Shift.
 Arithmetic Left Shift

Arithmetic Right Shift:

In this shift, each bit is moved to the right one by one and the least significant (LSB) bit is rejected
and the empty most significant bit(MSB) is filled with the value of the previous MSB.

Arithmetic Right Shift

3. Circular Shift:
The circular shift circulates the bits in the sequence of the register around both ends without any
loss of information.
Following are the two ways to perform the circular shift.

1. Circular Shift Left

2. Circular Shift Right
Circular Left Shift:
In this micro shift operation each bit in the register is shifted to the left one by one. After shifting,
the LSB becomes empty, so the value of the MSB is filled in there.
 Circular Left Shift

Circular Right Shift:

In this micro shift operation each bit in the register is shifted to the right one by one. After shifting,
the MSB becomes empty, so the value of the LSB is filled in there.

Circular Right Shift

Arithmetic Logic Shift Unit (ALSU): is a member of the Arithmetic Logic Unit
(ALU) in a computer system. It is a digital circuit that performs logical, arithmetic, and shift
operations. Rather than having individual registers calculating the micro operations directly, the
computer deploys a number of storage registers which is connected to a common operational unit
known as an arithmetic logic unit or ALU.
Now, to implement the micro operation, the contents of specified registers are allocated in the
inputs of the common Arithmetic Logic Unit. The Arithmetic Logic Unit performs an operation that
leads as a result and gets transferred to a destination register. Arithmetic Logic Unit may be a
combinatory circuit in order that the complete register transfer operation from the supply registers
through the ALU and into the destination register is performed throughout one clock pulse amount.
Sometimes, the shift micro operations are performed in a separate unit, but sometimes it is made as
a part of full ALU.

One stage of ALSU

We can combine and make one ALU with common selection variables by adding arithmetic, logic,
and shift circuits. We can see the, One stage of an arithmetic logic shift unit in the diagram below.
Some particular micro operations are selected through the inputs S1 and S0.

4 x 1 multiplexer at the output chooses between associate arithmetic output betwe

between
en Ei and a logic
output in Hi. The data in the multiplexer are selected through inputs S3 and S2 and the other two
data inputs to the multiplexer obtain the inputs Ai – 1 for the shr operation and Ai + 1 for
the shl operation.
Note: The output carry Ci + 1 of a specified arithmetic stage must be attached to the input carry Ci
of the next stage in the sequence.
 The circuit whose one stage is given in the below diagram provides 8 arithmetic operations, 4 logic
operations, and 2 shift operations, and Each operation is selected by the 5 variables S3, S2, S1, S0,
and Cin.

The below table shows the 14 operations perform by the Arithmetic Logic Unit:

1. The first 8 are arithmetic operations which are selected by S3 S2 = 00

2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 = 10 & 11

Function table of ALSU