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Microcontrollers
Lecture 2

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 Most common microcontrollers
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• 8-bit microcontrollers
(the CPU can work on only 8 bits of data at a time)
AVR, PIC, 8051

• 32-bit microcontrollers
ARM, AVR32, PIC32, CodeFire

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 AVR Family
 The AVR is an 8-bit RISC single-chip
microcontroller with Harvard architecture that
comes with some standard features such as on-
chip program (code) ROM, data RAM, data EEPROM,
timers and I/O ports
 Why Harvard-RISC Architecture
 There are three ways available to microprocessor
designers to increase the processing power of
the CPU:
 Increase the clock frequency of the chip, but it
increase heat dissipation.
 Use Harvard architecture by increasing the
number of buses to bring more information (code
and data) into the CPU, but (for general purpose
microprocessors this architecture is very expensive
and unrealistic).
 Change the internal architecture of the CPU and
use what is called RISC architecture, not CISC
(complex instruction set computer)
 Von Neumann vs. Harvard architecture
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Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus

• Harvard architecture

Code Data
Memory Memory

Data bus
CPU Address bus
Control bus

• Von Neumann architecture

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 Von Neumann vs Harvard architecture - 2
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CISC Vs. RISC

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 AVR internal architecture
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RAM EEPROM Timers

PROGRAM
ROM

Program
Bus Bus
CPU

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

8
 Memory Types In AVR
VCC
 Flash ROM
 Not deleted when power is off GND VCC

 Big in size 8
D0-D7
 Suitable for codes, tables and fixed data n
A0-An-1

 EEPROM (write enable) WE

 Not deleted when power is off (output enable) OE

CS
 Not very big in size (Chip selector)

 Suitable for small data that may be modified but should not
be lost when power is off
 RAM
 deleted when power is off
 Suitable for storing the data we want to manipulate
because we have fast access to read or modify them.
AVR microcontroller peripherals
 AVR’s CPU
 AVR’s CPU
 Arithmetic & Logic
Unit (ALU)
R0

32 General Purpose
R1
 ALU
R2
registers (GPRs),

…
R0-R31
SREG: I T H S V N Z C
R15

 Program Counter
CPU R16
R17

(PC) register

…
PC

R30
Instruction decoder
 Instruction Decoder R31

contains Instruction
Instruction Register
registers

Register (IR)
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THE GENERAL PURPOSE REGISTERS (GPRs)

 AVR microcontrollers have many registers

used to store information temporarily for
arithmetic and logic operations.

 In AVR there are 32 general purpose

registers (GPRs). They are R0–R31 and are
located in the lowest location of memory.

 That information in the GPRs could be a byte

of data to be processed, or an address
pointing to the data to be fetched.

 Any data larger than 8 bits must be broken

into 8-bit chunks before it is processed.
 Allocation of AVR’s Memory
 There are two kinds of memory space:
 data memory space
 code memory space

 Data memory space is composed of three parts:

 GPRs,
 I/O memory
 Internal data SRAM
 Allocation of AVR’s Memory - 2
Data Data
R0
Address R1
Address
$0000 R2 $0000
General General

...
Purpose Purpose

...
...

R31
$001F Registers $001F Registers
$0020 $0020
Standard I/O I/O Address Standard I/O
Registers $00 Registers
...

...
$01
(SFRs) (SFRs)
$005F $005F

...
$0060 $0060
$3E
Extended SREG $3F Extended
...

I/O Memory I/O Memory

$00FF $01FF
$0100 $0200
Internal Internal
...

...
SRAM SRAM
$21FF
$2200
External External
SRAM SRAM
$FFFF $FFFF
ATmega640/V
ATmega328 ATmega1280/V
ATmega64 ATmega1281/V
ATmega128 ATmega2560/V
ATmega2561/V
Data Address Space

General RAM EEPROM Timers

Purpose
PROGRAM
Registers
ROM

Program CPU Data

Bus Bus address bus
data bus
control bus
Data
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

15
I/O memory (SFRs) (special function registers)

 The I/O memory is dedicated to specific function

registers (SFRs) such as status register, timers,
serial communication, I/O ports, ADC, and so on.

 The function of each I/O memory location is fixed

by the CPU designer at the time of design
because it is used for control of the
microcontroller or peripherals.

 In contrast to SFRs, the GPRs do not have any

specific function and are used for storing general
data.
I/O memory (SFRs) (special function registers)
Address Name Address Name Address Name
Mem. I/O Mem. I/O Mem. I/O
$20 $00 - $36 $16 TIFR1 $4C $2C SPCR0
$21 $01 - $37 $17 TIFR2 $4D $2D SPSR0
$22 $02 - $38 $18 - $4E $2E SPDR0
$23 $03 PINB $39 $19 - $4F $2F -
$24 $04 DDRB $3A $1A - $50 $30 ACSR
$25 $05 PORTB $3B $1B PCIFR $51 $31 DWDR
$26 $06 PINC $3C $1C EIFR $52 $32 -
$27 $07 DDRC $3D $1D EIMSK $53 $33 SMCR
$28 $08 PORTC $3E $1E GPIOR0 $54 $34 MCUSR
$29 $09 PIND $3F $1F EECR $55 $35 MCUCR
$2A $0A DDRD $40 $20 EEDR $56 $36 -
$2B $0B PORTD $41 $21 EEARL $57 $37 SPMCSR
$2C $0C - $42 $22 EEARH $58 $38 -
$2D $0D - $43 $23 GTCCR $59 $39 -
$2E $0E - $44 $24 TCCR0A $5A $3A -
$2F $0F - $45 $25 TCCR0B $5B $3B -
$30 $10 - $46 $26 TCNT0 $5C $3C -
$31 $11 - $47 $27 OCR0A $5D $3D SPL
$32 $12 - $48 $28 OCR0B $5E $3E SPH
$33 $13 - $49 $29 - $5F $3F SREG
$34 $14 - $4A $2A GPIOR1
$35 $15 TIFR0 $4A $2A GPIOR2

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 Internal data SRAM
 Internal data SRAM is widely used for storing
data and parameters by AVR programmers and C
compilers.

 Generally, this is called scratch pad, which is a

high-speed internal memory.

 Each location of the SRAM can be accessed

directly by its address.
 EEPROM vs. SRAM
 The three parts of the data memory (GPRs, SFRs,
and the internal SRAM) are made of SRAM.

 whereas the SRAM is used for storing data and

parameters that are changed frequently.

 The AVR has an EEPROM memory that is used for

storing data. EEPROM does not lose its data when
power is off, whereas SRAM does.

 So, the EEPROM is used for storing data that should

rarely be changed and should not be lost when the
power is off (e.g., options and settings);
 ROM width in the AVR
 The code ROM 16 bits wide (word data size) is
to match it with the instruction width of the AVR
because the vast majority of the instructions are
2-byte instructions.

 The AVR designers have made all instructions

either 2-byte or 4-byte.

 There are no 1-byte or 3-byte instructions, as is

the case with the x86 and 8051 chips. This is part
of the RISC architectural philosophy.
 Fetch and execute
Old Architectures
00 E205
 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

22
 Pipelining
Pipelining
00 E205
 01 E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU

PC: Data
CPU Bus
Execute Program Instruction dec.

Bus

Interrupt Other
OSC Ports
Unit Peripherals

I/O
PINS

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 Status Register (SREG)
SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign Data Address
Half carry N+V Space
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
the
the status of
status
status ofthe
of
of theC,
the
the C,H,
C,
C, H,$0000
H,
H, andZZ
and
and
and ZZ flagsafter
flags
flags
flags afterthe
after
after theaddition
the
the addition
$0001 General
subtraction
subtraction
of
of 0x9C of
of 0x9C
0x23
0x73 from
from
from 0x9C
0xA5
0x52 in
in the
the following
following
0x64 in the following instructions:
0x38 and 0x2F instructions:
instructions:
Purpose

...
LDI LDILDI 0x38
LDI
R16, R20, 0x9C
R20,
R20, 0x9C
0xA5
0x52;R16 = 0x38
Registers
R0 $001F IO Address
ALU LDI LDI 0x2F
LDI
LDI
R17, R21,
R21,
R21, 0x9C
0x23
0x73
R1 0x64
;R17 = $0020
0x2F
$00
$01
R2 Standard IO
SUB R17R20,
SUB
ADD R20, R21
R20, R21;add R17;add
R21 ;subtract
;subtract
R21 toR21R21 from R20
R20from R20

...
ADD R16, to Registers
R16

...
…

SPH $3E
SREG: I T H S V N Z C $005F
Solution:
Solution:
Solution: R15 11
SREG $3F
Solution:
CPU
$0060
$52
$9C
$A5 0101
R16 0010
1001 1100
1010 1100
0101
$38
$9C 0011
1001 1000
- $73 0111
R17 0011
...
+-- +$64
$9C
$23
$2F 10010100
0010
0110 1100
0011
1111
$DF 1101 1111 R20
R20 == $DF
…

PC $00
$82
$67 00000000
1000
0110 0000
0010
0111 R20
R16 == 00
$00
$82
0x67
$100 1 0000 R20
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
CC===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20 andbit.
and
the D7 there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C == 00 decoder
because
because the
thereR20
is has
no a value
carry otherthe
beyond than
D7zero after the subtraction.
Instruction
ZZ =
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
to theafter the subtraction.
D4 bit.
H = 1 because there isR31 a borrow
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH
H =
= 00 because
because there
there is
is no
no borrow
borrow from
from D4
D4 to
to D3.
D3.
Z = 0 because the R16 (the result) has a value 0other
= 1 because
Instruction Register the R20 (the
registers
result) has a value in it after
than 0 the addition.
after the addition.
$FFFF

24
The End

QUESTIONS?

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