Advanced Digital System Design

TestBench

Dr. Dipali Borakhade

Assistant professor
St. Vincent Pallotti college of engineering and
technology , Nagpur
Testbench is used to verify the functionality of design at
each step.
qTestbenches are written in separate VHDL file.
qEntity of testbench is always empty i.e. no ports are defined in the entity.
qThe signals are defined inside the architecture body; these signals are
then connected to actual half adder design using structural modeling.
qStimulus is automatically applied to entity (or Unit) under test (UUT)
 Write testbench for half adder
VHDL Code

library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (a, b : in std_logic;
sum, carry : out std_logic );
end half_adder;
architecture arch of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end arch;
Testbench:-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY halfadder_tb IS
END halfadder_tb;

ARCHITECTURE behavior OF halfadder_tb is

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT halfadder
PORT( a : IN std_logic;
b : IN std_logic;
sum : OUT std_logic;
carry : OUT std_logic);
END COMPONENT;
a
--Inputs
signal a : std_logic := '0';
signal b : std_logic := '0';

--Outputs
signal sum : std_logic;
signal carry : std_logic;
begin
uut: halfadder PORT MAP ( a => a, b => b, sum => sum, carry => carry );

tb1 : process
begin
a <= '0'; b <= '1';
wait for 10ns;
a <= ‘1'; b <= ‘0';
wait for 10ns;
a <= ‘1'; b <= '1';
wait for 10ns;
end process;
END;
 Write a test bench for 1 bit full adder ckt.
VHDL Code

library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port(a, b,cin : in std_logic;
s, cout : out std_logic);
end fulladder;
architecture dataflow of fulladder is
begin
S <= A xor b xor cin;
Cout < = (a and b )or ( a and cin) or ( b and cin);
End dataflow;
Testbench: UUT : Fulladder port map (a <= a, b <= b, cin < = cin , s <= s , cout
<= cout);
Stimuli : process
begin
a <= '0'; b <= ‘0‘; cin <=‘1’;
library ieee; wait for 10ns;
use ieee.std_logic_1164.all;
a <= '0'; b <= ‘1‘; cin <=‘0’;
entity FA_TB is
wait for 10ns;
End entity;
Architecture behavior of FA_TB is a <= '0'; b <= ‘1‘; cin <=‘1’;
Component Fulladder wait for 10ns;
Port (a,b,cin : std_logic; a <= ‘1'; b <= ‘0‘; cin <=‘0’;
s ,cout : std_logic); wait for 10ns;
End component; a <= ‘1'; b <= ‘0‘; cin <=‘1’;
Signal a : std_logic :=‘0’; wait for 10ns;
Signal b : : std_logic := ‘0’ ; a <= ‘1'; b <= ‘1‘; cin <=‘0’;
Signal cin : std_logic:= ‘0’ ; wait for 10ns;
Signal s : std_logic;
a <= ‘1'; b <= ‘1‘; cin <=‘1’;
Signal cout : std_logic;
wait for 10ns;
begin
end process;
END;
 Write a test bench for 8:1 MUX.
VHDL Code
if S=“000” then
Z <= I(0);
Elsif S=“001” then
library IEEE;
Z <= I(1);
use IEEE.STD_LOGIC_1164.all; Elsif S=“010” then
Z <= I(2);
entity mux8to1 is
Elsif S=“011” then
port( I : in STD_LOGIC_vector(7 downto 0); Z <= I(3);
S: in STD_LOGIC_vector(2 downto 0); Elsif (S=“100”) then
Z: out STD_LOGIC ); Z <= I(4);
end mux8to1; Elsif (S=“101”) then
Z <= I(5);
architecture bhv of mux8to1 is Elsif (S=“110”) then
begin Z <= I(6);
process (I,S) is Else
begin Z<= I(7);
end if;
end process;
Testbench: BEGIN
uut: mux8to1 PORT MAP ( i => i, s => s, z => z);
library ieee;
stim_proc: process
use ieee.std_logic_1164.all; begin
I <=“10100011”;
entity FA_TB is S <= “000”;
End entity; wait for 10 ns;
S <= “001”;
Architecture behavior of mux_TB is wait for 10 ns;
Component mux8to1 S <= “010”;
port( I : in STD_LOGIC_vector(7 downto 0); wait for 10 ns;
S: in STD_LOGIC_vector(2 downto 0); S <= “011”;
Z: out STD_LOGIC ); wait for 10 ns;
S <= “100”;
End component; wait for 10 ns;
S <= “101”;
--Inputs
wait for 10 ns;
signal i : std_logic_vector(7 downto 0) := (others => '0'); S <= “110”;
wait for 10 ns;
signal s : std_logic_vector(2 downto 0) := (others => '0'); S <= “111”;
wait for 10 ns;
--Outputs
End process;
signal z : std_logic; End behavior;
Write a test bench to test the functionality of 16 to 1 multiplexer.
 Write a test bench to test the functionality of 4 bit Counter

use ieee.std_logic_1164.all; Begin

use ieee.std_logic_unsigned.all; If reset = ‘1’ then

entity counter4 is tmp <= “0000”;

Elsif (clocK’event and clock = ‘1’ ) then
port(Clock, reset : in std_logic;
tmp < = tmp +1;
Q : out std_logic_vector(3 downto 0));
Else
end counter4;
Tmp <= tmp;
architecture archi of counter is
End if;
signal tmp: std_logic_vector(3 downto 0); End process;
begin Q < = tmp ;
process (Clock, reset) End archi;
;
TESTBENCH
LIBRARY ieee; -- Clock period definitions
constant clock_period : time := 10 ns;
USE ieee.std_logic_1164.ALL;
BEGIN
ENTITY counter_tb IS uut: counter PORT MAP (clock => clock, reset => reset,
END counter_tb; q => q);

clock_process :process
ARCHITECTURE behavior OF counter_tb IS begin
COMPONENT counter clock <= '0';
PORT(clock : IN std_logic; wait for clock_period/2; --(wait for 20 ns; )
reset : IN std_logic; clock <= '1';
wait for clock_period/2;
q : OUT std_logic_vector(3 downto 0)); end process;
END COMPONENT;
signal clock : std_logic := '0'; Wait for 20ns;
signal reset : std_logic := '0'; Reset <= ‘1’;
Wait for 20ns;
signal q : std_logic_vector(3 downto 0);
END;
Write VHDL code for 3 input XOR gate .Also write test bench for the same.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity XOR_3 is
port ( A: in STD_LOGIC_vector(2 downto 0);
F : out STD_LOGIC );
end XOR_3;
architecture dataflow of XOR_3 is
begin
F <= A(0) XOR A(1) XOR A(2);
END DATAFLOW;
 uut: XOR_3 PORT MAP (A => A,F => F);
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
stim_proc: process
USE ieee.std_logic_arith.ALL; begin
USE ieee.std_logic_unsigned.ALL; A<="000"; wait for 100 ns;
A<="001"; wait for 100 ns;
ENTITY XOR_3_TB IS A<="010"; wait for 100 ns;
END XOR_3_TB;
A<="011"; wait for 100 ns;
ARCHITECTURE behavior OF XOR_3_TB IS A<="100"; wait for 100 ns;
COMPONENT XOR_3 A<="101"; wait for 100 ns;
PORT( A : IN std_logic_vector(2 downto 0); A<="110"; wait for 100 ns;
F : OUT std_logic); A<="111"; wait for 100 ns;
END COMPONENT; end process;

signal A : std_logic_vector(2 downto 0) := (others => '0');

signal F : std_logic; END;
 TESTBENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; uut: XOR_3 PORT MAP (A => A,F => F);
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL; stim_proc: process
begin
ENTITY XOR_3_TB IS a<="000";
END XOR_3_TB;
for i in 0 to 7 loop
ARCHITECTURE behavior OF XOR_3_TB IS
wait for 20ns;
COMPONENT XOR_3 a<= a + '1';
PORT( A : IN std_logic_vector(2 downto 0); wait for 20ns;
F : OUT std_logic); end loop;
END COMPONENT; end process;

signal A : std_logic_vector(2 downto 0) := (others => '0'); END;

signal F : std_logic;